1 /* 2 * Copyright (C) 2017 Vasily Khoruzhick <anarsoul@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <errno.h> 10 #include <i2c.h> 11 #include <edid.h> 12 #include <video_bridge.h> 13 #include "../anx98xx-edp.h" 14 15 #define DP_MAX_LINK_RATE 0x001 16 #define DP_MAX_LANE_COUNT 0x002 17 #define DP_MAX_LANE_COUNT_MASK 0x1f 18 19 struct anx6345_priv { 20 u8 edid[EDID_SIZE]; 21 }; 22 23 static int anx6345_write(struct udevice *dev, unsigned int addr_off, 24 unsigned char reg_addr, unsigned char value) 25 { 26 uint8_t buf[2]; 27 struct i2c_msg msg; 28 int ret; 29 30 msg.addr = addr_off; 31 msg.flags = 0; 32 buf[0] = reg_addr; 33 buf[1] = value; 34 msg.buf = buf; 35 msg.len = 2; 36 ret = dm_i2c_xfer(dev, &msg, 1); 37 if (ret) { 38 debug("%s: write failed, reg=%#x, value=%#x, ret=%d\n", 39 __func__, reg_addr, value, ret); 40 return ret; 41 } 42 43 return 0; 44 } 45 46 static int anx6345_read(struct udevice *dev, unsigned int addr_off, 47 unsigned char reg_addr, unsigned char *value) 48 { 49 uint8_t addr, val; 50 struct i2c_msg msg[2]; 51 int ret; 52 53 msg[0].addr = addr_off; 54 msg[0].flags = 0; 55 addr = reg_addr; 56 msg[0].buf = &addr; 57 msg[0].len = 1; 58 msg[1].addr = addr_off; 59 msg[1].flags = I2C_M_RD; 60 msg[1].buf = &val; 61 msg[1].len = 1; 62 ret = dm_i2c_xfer(dev, msg, 2); 63 if (ret) { 64 debug("%s: read failed, reg=%.2x, value=%p, ret=%d\n", 65 __func__, (int)reg_addr, value, ret); 66 return ret; 67 } 68 *value = val; 69 70 return 0; 71 } 72 73 static int anx6345_write_r0(struct udevice *dev, unsigned char reg_addr, 74 unsigned char value) 75 { 76 struct dm_i2c_chip *chip = dev_get_parent_platdata(dev); 77 78 return anx6345_write(dev, chip->chip_addr, reg_addr, value); 79 } 80 81 static int anx6345_read_r0(struct udevice *dev, unsigned char reg_addr, 82 unsigned char *value) 83 { 84 struct dm_i2c_chip *chip = dev_get_parent_platdata(dev); 85 86 return anx6345_read(dev, chip->chip_addr, reg_addr, value); 87 } 88 89 static int anx6345_write_r1(struct udevice *dev, unsigned char reg_addr, 90 unsigned char value) 91 { 92 struct dm_i2c_chip *chip = dev_get_parent_platdata(dev); 93 94 return anx6345_write(dev, chip->chip_addr + 1, reg_addr, value); 95 } 96 97 static int anx6345_read_r1(struct udevice *dev, unsigned char reg_addr, 98 unsigned char *value) 99 { 100 struct dm_i2c_chip *chip = dev_get_parent_platdata(dev); 101 102 return anx6345_read(dev, chip->chip_addr + 1, reg_addr, value); 103 } 104 105 static int anx6345_set_backlight(struct udevice *dev, int percent) 106 { 107 return -ENOSYS; 108 } 109 110 static int anx6345_aux_wait(struct udevice *dev) 111 { 112 int ret = -ETIMEDOUT; 113 u8 v; 114 int retries = 1000; 115 116 do { 117 anx6345_read_r0(dev, ANX9804_DP_AUX_CH_CTL_2, &v); 118 if (!(v & ANX9804_AUX_EN)) { 119 ret = 0; 120 break; 121 } 122 udelay(100); 123 } while (retries--); 124 125 if (ret) { 126 debug("%s: timed out waiting for AUX_EN to clear\n", __func__); 127 return ret; 128 } 129 130 ret = -ETIMEDOUT; 131 retries = 1000; 132 do { 133 anx6345_read_r1(dev, ANX9804_DP_INT_STA, &v); 134 if (v & ANX9804_RPLY_RECEIV) { 135 ret = 0; 136 break; 137 } 138 udelay(100); 139 } while (retries--); 140 141 if (ret) { 142 debug("%s: timed out waiting to receive reply\n", __func__); 143 return ret; 144 } 145 146 /* Clear RPLY_RECEIV bit */ 147 anx6345_write_r1(dev, ANX9804_DP_INT_STA, v); 148 149 anx6345_read_r0(dev, ANX9804_AUX_CH_STA, &v); 150 if ((v & ANX9804_AUX_STATUS_MASK) != 0) { 151 debug("AUX status: %d\n", v & ANX9804_AUX_STATUS_MASK); 152 ret = -EIO; 153 } 154 155 return ret; 156 } 157 158 static void anx6345_aux_addr(struct udevice *dev, u32 addr) 159 { 160 u8 val; 161 162 val = addr & 0xff; 163 anx6345_write_r0(dev, ANX9804_DP_AUX_ADDR_7_0, val); 164 val = (addr >> 8) & 0xff; 165 anx6345_write_r0(dev, ANX9804_DP_AUX_ADDR_15_8, val); 166 val = (addr >> 16) & 0x0f; 167 anx6345_write_r0(dev, ANX9804_DP_AUX_ADDR_19_16, val); 168 } 169 170 static int anx6345_aux_transfer(struct udevice *dev, u8 req, 171 u32 addr, u8 *buf, size_t len) 172 { 173 int i, ret; 174 u8 ctrl1 = req; 175 u8 ctrl2 = ANX9804_AUX_EN; 176 177 if (len > 16) 178 return -E2BIG; 179 180 if (len) 181 ctrl1 |= ANX9804_AUX_LENGTH(len); 182 else 183 ctrl2 |= ANX9804_ADDR_ONLY; 184 185 if (len && !(req & ANX9804_AUX_TX_COMM_READ)) { 186 for (i = 0; i < len; i++) 187 anx6345_write_r0(dev, ANX9804_BUF_DATA_0 + i, buf[i]); 188 } 189 190 anx6345_aux_addr(dev, addr); 191 anx6345_write_r0(dev, ANX9804_DP_AUX_CH_CTL_1, ctrl1); 192 anx6345_write_r0(dev, ANX9804_DP_AUX_CH_CTL_2, ctrl2); 193 ret = anx6345_aux_wait(dev); 194 if (ret) { 195 debug("AUX transaction timed out\n"); 196 return ret; 197 } 198 199 if (len && (req & ANX9804_AUX_TX_COMM_READ)) { 200 for (i = 0; i < len; i++) 201 anx6345_read_r0(dev, ANX9804_BUF_DATA_0 + i, &buf[i]); 202 } 203 204 return 0; 205 } 206 207 static int anx6345_read_aux_i2c(struct udevice *dev, u8 chip_addr, 208 u8 offset, size_t count, u8 *buf) 209 { 210 int i, ret; 211 size_t cur_cnt; 212 u8 cur_offset; 213 214 for (i = 0; i < count; i += 16) { 215 cur_cnt = (count - i) > 16 ? 16 : count - i; 216 cur_offset = offset + i; 217 ret = anx6345_aux_transfer(dev, ANX9804_AUX_TX_COMM_MOT, 218 chip_addr, &cur_offset, 1); 219 if (ret) { 220 debug("%s: failed to set i2c offset: %d\n", 221 __func__, ret); 222 return ret; 223 } 224 ret = anx6345_aux_transfer(dev, ANX9804_AUX_TX_COMM_READ, 225 chip_addr, buf + i, cur_cnt); 226 if (ret) { 227 debug("%s: failed to read from i2c device: %d\n", 228 __func__, ret); 229 return ret; 230 } 231 } 232 233 return 0; 234 } 235 236 static int anx6345_read_dpcd(struct udevice *dev, u32 reg, u8 *val) 237 { 238 int ret; 239 240 ret = anx6345_aux_transfer(dev, 241 ANX9804_AUX_TX_COMM_READ | 242 ANX9804_AUX_TX_COMM_DP_TRANSACTION, 243 reg, val, 1); 244 if (ret) { 245 debug("Failed to read DPCD\n"); 246 return ret; 247 } 248 249 return 0; 250 } 251 252 static int anx6345_read_edid(struct udevice *dev, u8 *buf, int size) 253 { 254 struct anx6345_priv *priv = dev_get_priv(dev); 255 256 if (size > EDID_SIZE) 257 size = EDID_SIZE; 258 memcpy(buf, priv->edid, size); 259 260 return size; 261 } 262 263 static int anx6345_attach(struct udevice *dev) 264 { 265 /* No-op */ 266 return 0; 267 } 268 269 static int anx6345_enable(struct udevice *dev) 270 { 271 u8 chipid, colordepth, lanes, data_rate, c; 272 int ret, i, bpp; 273 struct display_timing timing; 274 struct anx6345_priv *priv = dev_get_priv(dev); 275 276 /* Deassert reset and enable power */ 277 ret = video_bridge_set_active(dev, true); 278 if (ret) 279 return ret; 280 281 /* Reset */ 282 anx6345_write_r1(dev, ANX9804_RST_CTRL_REG, 1); 283 mdelay(100); 284 anx6345_write_r1(dev, ANX9804_RST_CTRL_REG, 0); 285 286 /* Write 0 to the powerdown reg (powerup everything) */ 287 anx6345_write_r1(dev, ANX9804_POWERD_CTRL_REG, 0); 288 289 ret = anx6345_read_r1(dev, ANX9804_DEV_IDH_REG, &chipid); 290 if (ret) 291 debug("%s: read id failed: %d\n", __func__, ret); 292 293 switch (chipid) { 294 case 0x63: 295 debug("ANX63xx detected.\n"); 296 break; 297 default: 298 debug("Error anx6345 chipid mismatch: %.2x\n", (int)chipid); 299 return -ENODEV; 300 } 301 302 for (i = 0; i < 100; i++) { 303 anx6345_read_r0(dev, ANX9804_SYS_CTRL2_REG, &c); 304 anx6345_write_r0(dev, ANX9804_SYS_CTRL2_REG, c); 305 anx6345_read_r0(dev, ANX9804_SYS_CTRL2_REG, &c); 306 if ((c & ANX9804_SYS_CTRL2_CHA_STA) == 0) 307 break; 308 309 mdelay(5); 310 } 311 if (i == 100) 312 debug("Error anx6345 clock is not stable\n"); 313 314 /* Set a bunch of analog related register values */ 315 anx6345_write_r0(dev, ANX9804_PLL_CTRL_REG, 0x00); 316 anx6345_write_r1(dev, ANX9804_ANALOG_DEBUG_REG1, 0x70); 317 anx6345_write_r0(dev, ANX9804_LINK_DEBUG_REG, 0x30); 318 319 /* Force HPD */ 320 anx6345_write_r0(dev, ANX9804_SYS_CTRL3_REG, 321 ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL); 322 323 /* Power up and configure lanes */ 324 anx6345_write_r0(dev, ANX9804_ANALOG_POWER_DOWN_REG, 0x00); 325 anx6345_write_r0(dev, ANX9804_TRAINING_LANE0_SET_REG, 0x00); 326 anx6345_write_r0(dev, ANX9804_TRAINING_LANE1_SET_REG, 0x00); 327 anx6345_write_r0(dev, ANX9804_TRAINING_LANE2_SET_REG, 0x00); 328 anx6345_write_r0(dev, ANX9804_TRAINING_LANE3_SET_REG, 0x00); 329 330 /* Reset AUX CH */ 331 anx6345_write_r1(dev, ANX9804_RST_CTRL2_REG, 332 ANX9804_RST_CTRL2_AUX); 333 anx6345_write_r1(dev, ANX9804_RST_CTRL2_REG, 0); 334 335 /* Powerdown audio and some other unused bits */ 336 anx6345_write_r1(dev, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO); 337 anx6345_write_r0(dev, ANX9804_HDCP_CONTROL_0_REG, 0x00); 338 anx6345_write_r0(dev, 0xa7, 0x00); 339 340 anx6345_read_aux_i2c(dev, 0x50, 0x0, EDID_SIZE, priv->edid); 341 if (edid_get_timing(priv->edid, EDID_SIZE, &timing, &bpp) != 0) { 342 debug("Failed to parse EDID\n"); 343 return -EIO; 344 } 345 debug("%s: panel found: %dx%d, bpp %d\n", __func__, 346 timing.hactive.typ, timing.vactive.typ, bpp); 347 if (bpp == 6) 348 colordepth = 0x00; /* 6 bit */ 349 else 350 colordepth = 0x10; /* 8 bit */ 351 anx6345_write_r1(dev, ANX9804_VID_CTRL2_REG, colordepth); 352 353 if (anx6345_read_dpcd(dev, DP_MAX_LINK_RATE, &data_rate)) { 354 debug("%s: Failed to DP_MAX_LINK_RATE\n", __func__); 355 return -EIO; 356 } 357 debug("%s: data_rate: %d\n", __func__, (int)data_rate); 358 if (anx6345_read_dpcd(dev, DP_MAX_LANE_COUNT, &lanes)) { 359 debug("%s: Failed to read DP_MAX_LANE_COUNT\n", __func__); 360 return -EIO; 361 } 362 lanes &= DP_MAX_LANE_COUNT_MASK; 363 debug("%s: lanes: %d\n", __func__, (int)lanes); 364 365 /* Set data-rate / lanes */ 366 anx6345_write_r0(dev, ANX9804_LINK_BW_SET_REG, data_rate); 367 anx6345_write_r0(dev, ANX9804_LANE_COUNT_SET_REG, lanes); 368 369 /* Link training */ 370 anx6345_write_r0(dev, ANX9804_LINK_TRAINING_CTRL_REG, 371 ANX9804_LINK_TRAINING_CTRL_EN); 372 mdelay(5); 373 for (i = 0; i < 100; i++) { 374 anx6345_read_r0(dev, ANX9804_LINK_TRAINING_CTRL_REG, &c); 375 if ((chipid == 0x63) && (c & 0x80) == 0) 376 break; 377 378 mdelay(5); 379 } 380 if (i == 100) { 381 debug("Error anx6345 link training timeout\n"); 382 return -ENODEV; 383 } 384 385 /* Enable */ 386 anx6345_write_r1(dev, ANX9804_VID_CTRL1_REG, 387 ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE); 388 /* Force stream valid */ 389 anx6345_write_r0(dev, ANX9804_SYS_CTRL3_REG, 390 ANX9804_SYS_CTRL3_F_HPD | 391 ANX9804_SYS_CTRL3_HPD_CTRL | 392 ANX9804_SYS_CTRL3_F_VALID | 393 ANX9804_SYS_CTRL3_VALID_CTRL); 394 395 return 0; 396 } 397 398 static int anx6345_probe(struct udevice *dev) 399 { 400 if (device_get_uclass_id(dev->parent) != UCLASS_I2C) 401 return -EPROTONOSUPPORT; 402 403 return anx6345_enable(dev); 404 } 405 406 struct video_bridge_ops anx6345_ops = { 407 .attach = anx6345_attach, 408 .set_backlight = anx6345_set_backlight, 409 .read_edid = anx6345_read_edid, 410 }; 411 412 static const struct udevice_id anx6345_ids[] = { 413 { .compatible = "analogix,anx6345", }, 414 { } 415 }; 416 417 U_BOOT_DRIVER(analogix_anx6345) = { 418 .name = "analogix_anx6345", 419 .id = UCLASS_VIDEO_BRIDGE, 420 .of_match = anx6345_ids, 421 .probe = anx6345_probe, 422 .ops = &anx6345_ops, 423 .priv_auto_alloc_size = sizeof(struct anx6345_priv), 424 }; 425