dt-bindings: Rename AST2600 RSA/ECC clock

Rename the RSACLK to RSAECCCLK as the HW
crypto engine includes both algo.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: I925d57595

dt-bindings: Rename AST2600 RSA/ECC clock

Rename the RSACLK to RSAECCCLK as the HW
crypto engine includes both algo.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: I925d57595cc35f4a2498758d2ed16eb5fba73a4f

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update

add ast2400 clk

add ast2400 include file

add fsi clk enable

add huartx clk and fix uart5 clk cal

update uart clk

add support 2 apb clk

hotfix add dpll define - ast2500

update for clk in dtsi and update ast2500 uart clk

update uart clk

modify for mac clk

update for reset and clk

update for clk

modify clk

modify ast2500-scu.h -> ast2500-clock.h

update clk

add ast2600 clk

dts: stm32mp1: clock tree update

- Add st,digbypass on clk_hse node (needed for board rev.C)
- MLAHB/AHB max frequency increased from 200 to 209MHz, with:
- PLL3P set to 208.8MHz for MCU sub-syste

dts: stm32mp1: clock tree update

- Add st,digbypass on clk_hse node (needed for board rev.C)
- MLAHB/AHB max frequency increased from 200 to 209MHz, with:
- PLL3P set to 208.8MHz for MCU sub-system
- PLL3Q set to 24.57MHz for 48kHz SAI/SPI2S
- PLL3R set to 11.29MHz for 44.1kHz SAI/SPI2S
- PLL4P set to 99MHz for SDMMC and SPDIFRX
- PLL4Q set to 74.25MHz for EVAL board

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

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poplar: sync up device tree with kernel 4.20

It adds missing pinctrl headers, updates clock header and sync up Poplar
device tree with kernel 4.20 release.

Signed-off-by: Shawn Guo <shawn.guo@linar

poplar: sync up device tree with kernel 4.20

It adds missing pinctrl headers, updates clock header and sync up Poplar
device tree with kernel 4.20 release.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

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sunxi: A64: Update sun50i-a64-ccu.h

Update sun50i-a64-ccu.h from the Linux sunxi/dt64-for-4.20 tree:
commit 679294497be31596e1c9c61507746d72b6b05f26
Author: Rodrigo Exterckötter Tjäder <rodrigo@tjad

sunxi: A64: Update sun50i-a64-ccu.h

Update sun50i-a64-ccu.h from the Linux sunxi/dt64-for-4.20 tree:
commit 679294497be31596e1c9c61507746d72b6b05f26
Author: Rodrigo Exterckötter Tjäder <rodrigo@tjader.xyz>
Date: Wed Sep 26 19:48:24 2018 +0000
arm64: dts: allwinner: a64: a64-olinuxino: set the PHY TX delay

This should be a part of previous sync patch from
commit 1b39a1834ed182bbd8036a5cd74a9ea111fa4691
Author: Andre Przywara <andre.przywara@arm.com>
Date: Mon Oct 29 00:56:47 2018 +0000

sunxi: A64: Update .dts/.dtsi files

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>

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ARM: dts: sun8i: Update A80 dts(i) from Linux-v4.18-rc3

Update all A80 devicetree dtsi and dtsi files from
Linux-v4.18-rc3 with below commits.

arch/arm/boot/dts/sun9i-a80*:

commit 190e3138f9577885

ARM: dts: sun8i: Update A80 dts(i) from Linux-v4.18-rc3

Update all A80 devicetree dtsi and dtsi files from
Linux-v4.18-rc3 with below commits.

arch/arm/boot/dts/sun9i-a80*:

commit 190e3138f9577885691540dca59c2f07540bde04
Merge: cafc87023b0d a7affb13b271
Author: Arnd Bergmann <arnd@arndb.de>
Date: Tue Mar 27 14:58:00 2018 +0200

Merge tag 'sunxi-h3-h5-for-4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt

include/dt-bindings/*/sun9i-a80-*:

commit 783ab76ae553abc23f80ef7511052d055697531b
Author: Chen-Yu Tsai <wens@csie.org>
Date: Sat Jan 28 20:22:36 2017 +0800

clk: sunxi-ng: Add A80 Display Engine CCU

Note: sun9i-a80-cx-a99.dts is updated only uart0, since the same
dts is not available in Linux.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

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