1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 /* 3 * Copyright (c) 2018 Microsemi Corporation 4 */ 5 6 #ifndef __ASM_MACH_COMMON_H 7 #define __ASM_MACH_COMMON_H 8 9 #if defined(CONFIG_SOC_OCELOT) 10 #include <mach/ocelot/ocelot.h> 11 #include <mach/ocelot/ocelot_devcpu_gcb.h> 12 #include <mach/ocelot/ocelot_devcpu_gcb_miim_regs.h> 13 #include <mach/ocelot/ocelot_icpu_cfg.h> 14 #elif defined(CONFIG_SOC_LUTON) 15 #include <mach/luton/luton.h> 16 #include <mach/luton/luton_devcpu_gcb.h> 17 #include <mach/luton/luton_devcpu_gcb_miim_regs.h> 18 #include <mach/luton/luton_icpu_cfg.h> 19 #elif defined(CONFIG_SOC_JR2) 20 #include <mach/jr2/jr2.h> 21 #include <mach/jr2/jr2_devcpu_gcb.h> 22 #include <mach/jr2/jr2_devcpu_gcb_miim_regs.h> 23 #include <mach/jr2/jr2_icpu_cfg.h> 24 #else 25 #error Unsupported platform 26 #endif 27 28 #define MSCC_DDR_TO 0x20000000 /* DDR RAM base offset */ 29 #define MSCC_MEMCTL1_TO 0x40000000 /* SPI/PI base offset */ 30 #define MSCC_MEMCTL2_TO 0x50000000 /* SPI/PI base offset */ 31 #define MSCC_FLASH_TO MSCC_MEMCTL1_TO /* Flash base offset */ 32 33 #define VCOREIII_TIMER_DIVIDER 25 /* Clock tick ~ 0.1 us */ 34 35 /* Common utility functions */ 36 37 /* 38 * Perform a number of NOP instructions, blocks of 8 instructions. 39 * The (inlined) function will not affect cache or processor state. 40 */ 41 static inline void mscc_vcoreiii_nop_delay(int delay) 42 { 43 while (delay > 0) { 44 #define DELAY_8_NOPS() asm volatile("nop; nop; nop; nop; nop; nop; nop; nop;") 45 switch (delay) { 46 case 8: 47 DELAY_8_NOPS(); 48 /* fallthrough */ 49 case 7: 50 DELAY_8_NOPS(); 51 /* fallthrough */ 52 case 6: 53 DELAY_8_NOPS(); 54 /* fallthrough */ 55 case 5: 56 DELAY_8_NOPS(); 57 /* fallthrough */ 58 case 4: 59 DELAY_8_NOPS(); 60 /* fallthrough */ 61 case 3: 62 DELAY_8_NOPS(); 63 /* fallthrough */ 64 case 2: 65 DELAY_8_NOPS(); 66 /* fallthrough */ 67 case 1: 68 DELAY_8_NOPS(); 69 } 70 delay -= 8; 71 #undef DELAY_8_NOPS 72 } 73 } 74 75 int mscc_phy_rd_wr(u8 read, 76 u32 miim_controller, 77 u8 miim_addr, 78 u8 addr, 79 u16 *value); 80 81 int mscc_phy_rd(u32 miim_controller, 82 u8 miim_addr, 83 u8 addr, 84 u16 *value); 85 86 int mscc_phy_wr(u32 miim_controller, 87 u8 miim_addr, 88 u8 addr, 89 u16 value); 90 91 void mscc_gpio_set_alternate(int gpio, int mode); 92 93 #endif /* __ASM_MACH_COMMON_H */ 94