1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 * 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <ram.h> 12 #include <regmap.h> 13 #include <reset.h> 14 #include <asm/io.h> 15 #include <asm/arch/scu_ast2600.h> 16 #include <asm/arch/sdram_ast2600.h> 17 #include <linux/err.h> 18 #include <linux/kernel.h> 19 #include <dt-bindings/clock/ast2600-clock.h> 20 #include "sdram_phy_ast2600.h" 21 22 /* in order to speed up DRAM init time, write pre-defined values to registers 23 * directly */ 24 #define AST2600_SDRAMMC_MANUAL_CLK 25 26 /* register offset */ 27 #define AST_SCU_FPGA_STATUS 0x004 28 #define AST_SCU_HANDSHAKE 0x100 29 #define AST_SCU_MPLL 0x220 30 #define AST_SCU_MPLL_EXT 0x224 31 #define AST_SCU_FPGA_PLL 0x400 32 #define AST_SCU_HW_STRAP 0x500 33 #define AST_SCU_EFUSE_DATA 0x594 34 35 36 /* bit-field of AST_SCU_HW_STRAP */ 37 #define SCU_HWSTRAP_VGAMEM_SHIFT 13 38 #define SCU_HWSTRAP_VGAMEM_MASK GENMASK(14, 13) 39 40 /* bit-field of AST_SCU_EFUSE_DATA */ 41 #define SCU_EFUSE_DATA_VGA_DIS_MASK BIT(14) 42 43 /* bit-field of AST_SCU_HANDSHAKE */ 44 #define SCU_SDRAM_INIT_READY_MASK BIT(6) 45 #define SCU_SDRAM_INIT_BY_SOC_MASK BIT(7) 46 47 /* bit-field of AST_SCU_MPLL */ 48 #define SCU_MPLL_RESET BIT(25) 49 #define SCU_MPLL_BYPASS BIT(24) 50 #define SCU_MPLL_TURN_OFF BIT(23) 51 #define SCU_MPLL_FREQ_MASK GENMASK(22, 0) 52 53 #define SCU_MPLL_FREQ_400M 0x0008405F 54 #define SCU_MPLL_EXT_400M 0x0000002F 55 //#define SCU_MPLL_FREQ_400M 0x0038007F 56 //#define SCU_MPLL_EXT_400M 0x0000003F 57 #define SCU_MPLL_FREQ_333M 0x00488299 58 #define SCU_MPLL_EXT_333M 0x0000014C 59 #define SCU_MPLL_FREQ_200M 0x0078007F 60 #define SCU_MPLL_EXT_200M 0x0000003F 61 #define SCU_MPLL_FREQ_100M 0x0078003F 62 #define SCU_MPLL_EXT_100M 0x0000001F 63 /* MPLL configuration */ 64 #if defined(CONFIG_ASPEED_DDR4_1600) 65 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_400M 66 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_400M 67 #elif defined(CONFIG_ASPEED_DDR4_1333) 68 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_333M 69 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_333M 70 #elif defined(CONFIG_ASPEED_DDR4_800) 71 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_200M 72 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_200M 73 #elif defined(CONFIG_ASPEED_DDR4_400) 74 #define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_100M 75 #define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_100M 76 #else 77 #error "undefined DDR4 target rate\n" 78 #endif 79 80 /* AC timing and SDRAM mode registers */ 81 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 82 /* mode register settings for FPGA are fixed */ 83 #define DDR4_MR01_MODE 0x03010100 84 #define DDR4_MR23_MODE 0x00000000 85 #define DDR4_MR45_MODE 0x04C00000 86 #define DDR4_MR6_MODE 0x00000050 87 #define DDR4_TRFC_FPGA 0x17263434 88 89 /* FPGA need for an additional initialization procedure: search read window */ 90 #define SEARCH_RDWIN_ANCHOR_0 (CONFIG_SYS_SDRAM_BASE + 0x0000) 91 #define SEARCH_RDWIN_ANCHOR_1 (CONFIG_SYS_SDRAM_BASE + 0x0004) 92 #define SEARCH_RDWIN_PTRN_0 0x12345678 93 #define SEARCH_RDWIN_PTRN_1 0xaabbccdd 94 #define SEARCH_RDWIN_PTRN_SUM 0xbcf02355 95 #else 96 /* mode register setting for real chip are derived from the model GDDR4-1600 */ 97 #define DDR4_MR01_MODE 0x03010510 98 #define DDR4_MR23_MODE 0x00000000 99 #define DDR4_MR45_MODE 0x04000000 100 #define DDR4_MR6_MODE 0x00000400 101 #define DDR4_TRFC_1600 0x467299f1 102 #define DDR4_TRFC_1333 0x3a5f80c9 103 #define DDR4_TRFC_800 0x23394c78 104 #define DDR4_TRFC_400 0x111c263c 105 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 106 defined(CONFIG_ASPEED_PALLADIUM)" */ 107 108 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 109 #define DDR4_TRFC DDR4_TRFC_FPGA 110 #else 111 /* real chip setting */ 112 #if defined(CONFIG_ASPEED_DDR4_1600) 113 #define DDR4_TRFC DDR4_TRFC_1600 114 #define DDR4_PHY_TRAIN_TRFC 0xc30 115 #elif defined(CONFIG_ASPEED_DDR4_1333) 116 #define DDR4_TRFC DDR4_TRFC_1333 117 #define DDR4_PHY_TRAIN_TRFC 0xa25 118 #elif defined(CONFIG_ASPEED_DDR4_800) 119 #define DDR4_TRFC DDR4_TRFC_800 120 #define DDR4_PHY_TRAIN_TRFC 0x618 121 #elif defined(CONFIG_ASPEED_DDR4_400) 122 #define DDR4_TRFC DDR4_TRFC_400 123 #define DDR4_PHY_TRAIN_TRFC 0x30c 124 #else 125 #error "undefined tRFC setting" 126 #endif /* end of "#if (SCU_MPLL_FREQ_CFG == SCU_MPLL_FREQ_400M)" */ 127 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 128 defined(CONFIG_ASPEED_PALLADIUM)" */ 129 130 /* supported SDRAM size */ 131 #define SDRAM_SIZE_1KB (1024U) 132 #define SDRAM_SIZE_1MB (SDRAM_SIZE_1KB * SDRAM_SIZE_1KB) 133 #define SDRAM_MIN_SIZE (256 * SDRAM_SIZE_1MB) 134 #define SDRAM_MAX_SIZE (2048 * SDRAM_SIZE_1MB) 135 136 137 DECLARE_GLOBAL_DATA_PTR; 138 139 /* 140 * Bandwidth configuration parameters for different SDRAM requests. 141 * These are hardcoded settings taken from Aspeed SDK. 142 */ 143 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 144 static const u32 ddr4_ac_timing[4] = { 0x030C0207, 0x04451133, 0x0E010200, 145 0x00000140 }; 146 147 static const u32 ddr_max_grant_params[4] = { 0x88888888, 0x88888888, 0x88888888, 148 0x88888888 }; 149 #else 150 static const u32 ddr4_ac_timing[4] = { 0x040e0307, 0x0f4711f1, 0x0e060304, 151 0x00001240 }; 152 153 static const u32 ddr_max_grant_params[4] = { 0x44444444, 0x44444466, 0x44444444, 154 0x44444444 }; 155 #endif 156 157 struct dram_info { 158 struct ram_info info; 159 struct clk ddr_clk; 160 struct ast2600_sdrammc_regs *regs; 161 void __iomem *scu; 162 struct ast2600_ddr_phy *phy; 163 void __iomem *phy_setting; 164 void __iomem *phy_status; 165 ulong clock_rate; 166 }; 167 168 static void ast2600_sdramphy_kick_training(struct dram_info *info) 169 { 170 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 171 struct ast2600_sdrammc_regs *regs = info->regs; 172 u32 volatile data; 173 174 writel(SDRAM_PHYCTRL0_NRST, ®s->phy_ctrl[0]); 175 udelay(5); 176 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]); 177 udelay(1000); 178 179 while (1) { 180 data = readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT; 181 if (~data) { 182 break; 183 } 184 } 185 186 #if 0 187 while (1) { 188 data = readl(0x1e6e0400) & BIT(1); 189 if (data) { 190 break; 191 } 192 } 193 #endif 194 #endif 195 } 196 197 /** 198 * @brief load DDR-PHY configurations table to the PHY registers 199 * @param[in] p_tbl - pointer to the configuration table 200 * @param[in] info - pointer to the DRAM info struct 201 * 202 * There are two sets of MRS (Mode Registers) configuration in ast2600 memory 203 * system: one is in the SDRAM MC (memory controller) which is used in run 204 * time, and the other is in the DDR-PHY IP which is used during DDR-PHY 205 * training. 206 */ 207 static void ast2600_sdramphy_init(u32 *p_tbl, struct dram_info *info) 208 { 209 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 210 u32 reg_base = (u32)info->phy_setting; 211 u32 addr = p_tbl[0]; 212 u32 data; 213 int i = 1; 214 215 writel(0, &info->regs->phy_ctrl[0]); 216 udelay(10); 217 //writel(SDRAM_PHYCTRL0_NRST, ®s->phy_ctrl[0]); 218 219 220 /* load PHY configuration table into PHY-setting registers */ 221 while (1) { 222 if (addr < reg_base) { 223 debug("invalid DDR-PHY addr: 0x%08x\n", addr); 224 break; 225 } 226 data = p_tbl[i++]; 227 228 if (DDR_PHY_TBL_END == data) { 229 break; 230 } else if (DDR_PHY_TBL_CHG_ADDR == data) { 231 addr = p_tbl[i++]; 232 } else { 233 writel(data, addr); 234 addr += 4; 235 } 236 } 237 238 data = readl(info->phy_setting + 0x84) & ~GENMASK(16, 0); 239 data |= DDR4_PHY_TRAIN_TRFC; 240 writel(data, info->phy_setting + 0x84); 241 #endif 242 } 243 244 static int ast2600_sdramphy_check_status(struct dram_info *info) 245 { 246 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM) 247 u32 value, tmp; 248 u32 reg_base = (u32)info->phy_status; 249 int need_retrain = 0; 250 251 debug("\nSDRAM PHY training report:\n"); 252 /* training status */ 253 value = readl(reg_base + 0x00); 254 debug("rO_DDRPHY_reg offset 0x00 = 0x%08x\n", value); 255 if (value & BIT(3)) { 256 debug("\tinitial PVT calibration fail\n"); 257 } 258 if (value & BIT(5)) { 259 debug("\truntime calibration fail\n"); 260 } 261 262 /* PU & PD */ 263 value = readl(reg_base + 0x30); 264 debug("rO_DDRPHY_reg offset 0x30 = 0x%08x\n", value); 265 debug(" PU = 0x%02x\n", value & 0xff); 266 debug(" PD = 0x%02x\n", (value >> 16) & 0xff); 267 268 /* read eye window */ 269 value = readl(reg_base + 0x68); 270 if (0 == (value & GENMASK(7, 0))) { 271 need_retrain = 1; 272 } 273 274 debug("rO_DDRPHY_reg offset 0x68 = 0x%08x\n", value); 275 debug(" rising edge of read data eye training pass window\n"); 276 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 277 debug(" B0:%d%%\n", tmp); 278 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 279 debug(" B1:%d%%\n", tmp); 280 281 value = readl(reg_base + 0xC8); 282 debug("rO_DDRPHY_reg offset 0xC8 = 0x%08x\n", value); 283 debug(" falling edge of read data eye training pass window\n"); 284 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 285 debug(" B0:%d%%\n", tmp); 286 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 287 debug(" B1:%d%%\n", tmp); 288 289 /* write eye window */ 290 value = readl(reg_base + 0x7c); 291 if (0 == (value & GENMASK(7, 0))) { 292 need_retrain = 1; 293 } 294 295 debug("rO_DDRPHY_reg offset 0x7C = 0x%08x\n", value); 296 debug(" rising edge of write data eye training pass window\n"); 297 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 298 debug(" B0:%d%%\n", tmp); 299 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; 300 debug(" B1:%d%%\n", tmp); 301 302 /* read Vref training result */ 303 value = readl(reg_base + 0x88); 304 debug("rO_DDRPHY_reg offset 0x88 = 0x%08x\n", value); 305 debug(" read Vref training result\n"); 306 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 127; 307 debug(" B0:%d%%\n", tmp); 308 tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 127; 309 debug(" B1:%d%%\n", tmp); 310 311 /* write Vref training result */ 312 value = readl(reg_base + 0x90); 313 debug("rO_DDRPHY_reg offset 0x90 = 0x%08x\n", value); 314 #if 0 315 tmp = (((value & GENMASK(5, 0)) >> 0) * 100) / 127; 316 debug(" write Vref training result = %d%%\n", tmp); 317 #endif 318 319 /* gate train */ 320 value = readl(reg_base + 0x50); 321 if ((0 == (value & GENMASK(15, 0))) || 322 (0 == (value & GENMASK(31, 16)))) { 323 need_retrain = 1; 324 } 325 #if 0 326 if (((value >> 24) & 0xff) < 3) 327 need_retrain = 1; 328 else 329 need_retrain = 0; 330 #endif 331 debug("rO_DDRPHY_reg offset 0x50 = 0x%08x\n", value); 332 #if 0 333 debug(" gate training pass window\n"); 334 tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; 335 debug(" module 0: %d.%03d\n", (value >> 8) & 0xff, tmp); 336 tmp = (((value & GENMASK(23, 16)) >> 0) * 100) / 255; 337 debug(" module 1: %d.%03d\n", (value >> 24) & 0xff, tmp); 338 #endif 339 340 return need_retrain; 341 #else 342 return 0; 343 #endif 344 } 345 #ifndef CONFIG_ASPEED_BYPASS_SELFTEST 346 #define MC_TEST_PATTERN_N 8 347 static u32 as2600_sdrammc_test_pattern[MC_TEST_PATTERN_N] = { 348 0xcc33cc33, 0xff00ff00, 0xaa55aa55, 0x88778877, 349 0x92cc4d6e, 0x543d3cde, 0xf1e843c7, 0x7c61d253 350 }; 351 352 #define TIMEOUT_DRAM 5000000 353 int ast2600_sdrammc_dg_test(struct dram_info *info, unsigned int datagen, u32 mode) 354 { 355 unsigned int data; 356 unsigned int timeout = 0; 357 struct ast2600_sdrammc_regs *regs = info->regs; 358 359 writel(0, ®s->ecc_test_ctrl); 360 if (mode == 0) 361 writel(0x00000085 | (datagen << 3), ®s->ecc_test_ctrl); 362 else 363 writel(0x000000C1 | (datagen << 3), ®s->ecc_test_ctrl); 364 365 do { 366 data = readl(®s->ecc_test_ctrl) & GENMASK(13, 12); 367 368 if (data & BIT(13)) 369 return 0; 370 371 if (++timeout > TIMEOUT_DRAM) { 372 printf("Timeout!!\n"); 373 writel(0, ®s->ecc_test_ctrl); 374 375 return 0; 376 } 377 } while (!data); 378 379 writel(0, ®s->ecc_test_ctrl); 380 381 return 1; 382 } 383 384 int ast2600_sdrammc_cbr_test(struct dram_info *info) 385 { 386 struct ast2600_sdrammc_regs *regs = info->regs; 387 u32 i; 388 389 clrsetbits_le32(®s->test_addr, GENMASK(30, 4), 0x7ffff0); 390 391 /* single */ 392 for (i = 0; i < 8; i++) { 393 if (!ast2600_sdrammc_dg_test(info, i, 0)) 394 return (0); 395 } 396 397 /* burst */ 398 for (i = 0; i < 8; i++) { 399 if (!ast2600_sdrammc_dg_test(info, i, i)) 400 return (0); 401 } 402 403 return(1); 404 } 405 406 static int ast2600_sdrammc_test(struct dram_info *info) 407 { 408 struct ast2600_sdrammc_regs *regs = info->regs; 409 410 u32 pass_cnt = 0; 411 u32 fail_cnt = 0; 412 u32 target_cnt = 2; 413 u32 test_cnt = 0; 414 u32 pattern; 415 u32 i = 0; 416 bool finish = false; 417 418 debug("sdram mc test:\n"); 419 while (finish == false) { 420 pattern = as2600_sdrammc_test_pattern[i++]; 421 i = i % MC_TEST_PATTERN_N; 422 debug(" pattern = %08X : ",pattern); 423 writel(pattern, ®s->test_init_val); 424 425 if (!ast2600_sdrammc_cbr_test(info)) { 426 debug("fail\n"); 427 fail_cnt++; 428 } else { 429 debug("pass\n"); 430 pass_cnt++; 431 } 432 433 if (++test_cnt == target_cnt) { 434 finish = true; 435 } 436 } 437 debug("statistics: pass/fail/total:%d/%d/%d\n", pass_cnt, fail_cnt, 438 target_cnt); 439 return fail_cnt; 440 } 441 #endif 442 /** 443 * scu500[14:13] 444 * 2b'00: VGA memory size = 16MB 445 * 2b'01: VGA memory size = 16MB 446 * 2b'10: VGA memory size = 32MB 447 * 2b'11: VGA memory size = 64MB 448 * 449 * mcr04[3:2] 450 * 2b'00: VGA memory size = 8MB 451 * 2b'01: VGA memory size = 16MB 452 * 2b'10: VGA memory size = 32MB 453 * 2b'11: VGA memory size = 64MB 454 */ 455 static size_t ast2600_sdrammc_get_vga_mem_size(struct dram_info *info) 456 { 457 u32 vga_hwconf; 458 size_t vga_mem_size_base = 8 * 1024 * 1024; 459 460 vga_hwconf = 461 (readl(info->scu + AST_SCU_HW_STRAP) & SCU_HWSTRAP_VGAMEM_MASK) >> 462 SCU_HWSTRAP_VGAMEM_SHIFT; 463 464 if (vga_hwconf == 0) { 465 vga_hwconf = 1; 466 writel(vga_hwconf << SCU_HWSTRAP_VGAMEM_SHIFT, 467 info->scu + AST_SCU_HW_STRAP); 468 } 469 470 clrsetbits_le32(&info->regs->config, SDRAM_CONF_VGA_SIZE_MASK, 471 ((vga_hwconf << SDRAM_CONF_VGA_SIZE_SHIFT) & 472 SDRAM_CONF_VGA_SIZE_MASK)); 473 474 /* no need to reserve VGA memory if efuse[VGA disable] is set */ 475 if (readl(info->scu + AST_SCU_EFUSE_DATA) & SCU_EFUSE_DATA_VGA_DIS_MASK) 476 return 0; 477 478 return vga_mem_size_base << vga_hwconf; 479 } 480 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 481 static void ast2600_sdrammc_fpga_set_pll(struct dram_info *info) 482 { 483 u32 data; 484 u32 scu_base = (u32)info->scu; 485 486 writel(0x00000303, scu_base + AST_SCU_FPGA_PLL); 487 488 do { 489 data = readl(scu_base + AST_SCU_FPGA_STATUS); 490 } while (!(data & 0x100)); 491 492 writel(0x00000103, scu_base + AST_SCU_FPGA_PLL); 493 } 494 495 static int ast2600_sdrammc_search_read_window(struct dram_info *info) 496 { 497 u32 pll, pll_min, pll_max, dat1, offset; 498 u32 win = 0x03, gwin = 0, gwinsize = 0; 499 u32 phy_setting = (u32)info->phy_setting; 500 501 #ifdef CONFIG_ASPEED_PALLADIUM 502 writel(0xc, phy_setting + 0x0000); 503 return 1; 504 #endif 505 writel(SEARCH_RDWIN_PTRN_0, SEARCH_RDWIN_ANCHOR_0); 506 writel(SEARCH_RDWIN_PTRN_1, SEARCH_RDWIN_ANCHOR_1); 507 508 while (gwin == 0) { 509 while (!(win & 0x80)) { 510 debug("Window = 0x%X\n", win); 511 writel(win, phy_setting + 0x0000); 512 513 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 514 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 515 while (dat1 == SEARCH_RDWIN_PTRN_SUM) { 516 ast2600_sdrammc_fpga_set_pll(info); 517 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 518 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 519 } 520 521 pll_min = 0xfff; 522 pll_max = 0x0; 523 pll = 0; 524 while (pll_max > 0 || pll < 256) { 525 ast2600_sdrammc_fpga_set_pll(info); 526 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 527 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 528 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 529 if (pll_min > pll) 530 pll_min = pll; 531 532 if (pll_max < pll) 533 pll_max = pll; 534 535 debug("%3d_(%3d:%3d)\n", pll, pll_min, 536 pll_max); 537 } else if (pll_max > 0) { 538 pll_min = pll_max - pll_min; 539 if (gwinsize < pll_min) { 540 gwin = win; 541 gwinsize = pll_min; 542 } 543 break; 544 } 545 pll += 1; 546 } 547 548 if (gwin != 0 && pll_max == 0) 549 break; 550 551 win = win << 1; 552 } 553 if (gwin == 0) 554 win = 0x7; 555 } 556 debug("Set PLL Read Gating Window = %x\n", gwin); 557 writel(gwin, phy_setting + 0x0000); 558 559 debug("PLL Read Window training\n"); 560 pll_min = 0xfff; 561 pll_max = 0x0; 562 563 debug("Search Window Start\n"); 564 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 565 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 566 while (dat1 == SEARCH_RDWIN_PTRN_SUM) { 567 ast2600_sdrammc_fpga_set_pll(info); 568 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 569 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 570 } 571 572 debug("Search Window Margin\n"); 573 pll = 0; 574 while (pll_max > 0 || pll < 256) { 575 ast2600_sdrammc_fpga_set_pll(info); 576 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 577 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 578 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 579 if (pll_min > pll) 580 pll_min = pll; 581 582 if (pll_max < pll) 583 pll_max = pll; 584 585 debug("%3d_(%3d:%3d)\n", pll, pll_min, pll_max); 586 } else if (pll_max > 0 && (pll_max - pll_min) > 20) { 587 break; 588 } else if (pll_max > 0) { 589 pll_min = 0xfff; 590 pll_max = 0x0; 591 } 592 pll += 1; 593 } 594 if (pll_min < pll_max) { 595 debug("PLL Read window = %d\n", (pll_max - pll_min)); 596 offset = (pll_max - pll_min) >> 1; 597 pll_min = 0xfff; 598 pll = 0; 599 while (pll < (pll_min + offset)) { 600 ast2600_sdrammc_fpga_set_pll(info); 601 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 602 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 603 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 604 if (pll_min > pll) { 605 pll_min = pll; 606 } 607 debug("%d\n", pll); 608 } else { 609 pll_min = 0xfff; 610 pll_max = 0x0; 611 } 612 pll += 1; 613 } 614 return (1); 615 } else { 616 debug("PLL Read window training fail\n"); 617 return 0; 618 } 619 } 620 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) || \ 621 defined(CONFIG_ASPEED_PALLADIUM)" */ 622 623 /* 624 * Find out RAM size and save it in dram_info 625 * 626 * The procedure is taken from Aspeed SDK 627 */ 628 static void ast2600_sdrammc_calc_size(struct dram_info *info) 629 { 630 /* The controller supports 256/512/1024/2048 MB ram */ 631 size_t ram_size = SDRAM_MIN_SIZE; 632 const int write_test_offset = 0x100000; 633 u32 test_pattern = 0xdeadbeef; 634 u32 cap_param = SDRAM_CONF_CAP_2048M; 635 u32 refresh_timing_param = DDR4_TRFC; 636 const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset; 637 638 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 639 ram_size >>= 1) { 640 writel(test_pattern, write_addr_base + (ram_size >> 1)); 641 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 642 } 643 644 /* One last write to overwrite all wrapped values */ 645 writel(test_pattern, write_addr_base); 646 647 /* Reset the pattern and see which value was really written */ 648 test_pattern = 0xdeadbeef; 649 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 650 ram_size >>= 1) { 651 if (readl(write_addr_base + (ram_size >> 1)) == test_pattern) 652 break; 653 654 --cap_param; 655 refresh_timing_param >>= 8; 656 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 657 } 658 659 clrsetbits_le32(&info->regs->ac_timing[1], 660 (SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT), 661 ((refresh_timing_param & SDRAM_AC_TRFC_MASK) 662 << SDRAM_AC_TRFC_SHIFT)); 663 664 info->info.base = CONFIG_SYS_SDRAM_BASE; 665 info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info) - CONFIG_ASPEED_SSP_RERV_MEM; 666 667 clrsetbits_le32( 668 &info->regs->config, SDRAM_CONF_CAP_MASK, 669 ((cap_param << SDRAM_CONF_CAP_SHIFT) & SDRAM_CONF_CAP_MASK)); 670 } 671 672 static int ast2600_sdrammc_init_ddr4(struct dram_info *info) 673 { 674 const u32 power_ctrl = MCR34_CKE_EN | MCR34_AUTOPWRDN_EN | 675 MCR34_MREQ_BYPASS_DIS | MCR34_RESETN_DIS | 676 MCR34_ODT_EN | MCR34_ODT_AUTO_ON | 677 (0x1 << MCR34_ODT_EXT_SHIFT); 678 679 /* init SDRAM-PHY only on real chip */ 680 ast2600_sdramphy_init(ast2600_sdramphy_config, info); 681 writel((MCR34_CKE_EN | MCR34_MREQI_DIS | MCR34_RESETN_DIS), 682 &info->regs->power_ctrl); 683 udelay(5); 684 ast2600_sdramphy_kick_training(info); 685 udelay(500); 686 writel(SDRAM_RESET_DLL_ZQCL_EN, &info->regs->refresh_timing); 687 688 writel(MCR30_SET_MR(3), &info->regs->mode_setting_control); 689 writel(MCR30_SET_MR(6), &info->regs->mode_setting_control); 690 writel(MCR30_SET_MR(5), &info->regs->mode_setting_control); 691 writel(MCR30_SET_MR(4), &info->regs->mode_setting_control); 692 writel(MCR30_SET_MR(2), &info->regs->mode_setting_control); 693 writel(MCR30_SET_MR(1), &info->regs->mode_setting_control); 694 writel(MCR30_SET_MR(0) | MCR30_RESET_DLL_DELAY_EN, 695 &info->regs->mode_setting_control); 696 697 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 698 699 writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN | 700 (0x5d << SDRAM_REFRESH_PERIOD_SHIFT), 701 &info->regs->refresh_timing); 702 #else 703 writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN | 704 (0x5f << SDRAM_REFRESH_PERIOD_SHIFT), 705 &info->regs->refresh_timing); 706 #endif 707 708 /* wait self-refresh idle */ 709 while (readl(&info->regs->power_ctrl) & MCR34_SELF_REFRESH_STATUS_MASK) 710 ; 711 712 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 713 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | 714 SDRAM_REFRESH_ZQCS_EN | 715 (0x5d << SDRAM_REFRESH_PERIOD_SHIFT) | 716 (0x4000 << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), 717 &info->regs->refresh_timing); 718 #else 719 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | 720 SDRAM_REFRESH_ZQCS_EN | 721 (0x5f << SDRAM_REFRESH_PERIOD_SHIFT) | 722 (0x42aa << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), 723 &info->regs->refresh_timing); 724 #endif 725 726 writel(power_ctrl, &info->regs->power_ctrl); 727 udelay(500); 728 729 #if defined(CONFIG_FPGA_ASPEED) 730 /* toggle Vref training */ 731 setbits_le32(&info->regs->mr6_mode_setting, 0x80); 732 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), 733 &info->regs->mode_setting_control); 734 clrbits_le32(&info->regs->mr6_mode_setting, 0x80); 735 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), 736 &info->regs->mode_setting_control); 737 #endif 738 return 0; 739 } 740 741 static void ast2600_sdrammc_unlock(struct dram_info *info) 742 { 743 writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key); 744 while (!readl(&info->regs->protection_key)) 745 ; 746 } 747 748 static void ast2600_sdrammc_lock(struct dram_info *info) 749 { 750 writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key); 751 while (readl(&info->regs->protection_key)) 752 ; 753 } 754 755 static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs) 756 { 757 int i; 758 759 writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, ®s->power_ctrl); 760 writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key); 761 writel(0x101010, ®s->arbitration_ctrl); 762 writel(0x0FFFFCFC, ®s->req_limit_mask); 763 764 for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i) 765 writel(ddr_max_grant_params[i], ®s->max_grant_len[i]); 766 767 writel(MCR50_RESET_ALL_INTR, ®s->intr_ctrl); 768 769 /* FIXME: the sample code does NOT match the datasheet */ 770 writel(0x07FFFFFF, ®s->ecc_range_ctrl); 771 772 writel(0, ®s->ecc_test_ctrl); 773 writel(0x80000001, ®s->test_addr); 774 writel(0, ®s->test_fail_dq_bit); 775 writel(0, ®s->test_init_val); 776 777 writel(0xFFFFFFFF, ®s->req_input_ctrl); 778 writel(0x0, ®s->req_high_pri_ctrl); 779 780 udelay(600); 781 782 #ifdef CONFIG_ASPEED_DDR4_DUALX8 783 writel(0x37, ®s->config); 784 #else 785 writel(0x17, ®s->config); 786 #endif 787 788 /* load controller setting */ 789 for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i) 790 writel(ddr4_ac_timing[i], ®s->ac_timing[i]); 791 792 writel(DDR4_MR01_MODE, ®s->mr01_mode_setting); 793 writel(DDR4_MR23_MODE, ®s->mr23_mode_setting); 794 writel(DDR4_MR45_MODE, ®s->mr45_mode_setting); 795 writel(DDR4_MR6_MODE, ®s->mr6_mode_setting); 796 } 797 /* 798 * Update size info according to the ECC HW setting 799 * 800 * Assume SDRAM has been initialized by SPL or the host. To get the RAM size, we 801 * don't need to calculate the ECC size again but read from MCR04 and derive the 802 * size from its value. 803 */ 804 static void ast2600_sdrammc_update_size(struct dram_info *info) 805 { 806 struct ast2600_sdrammc_regs *regs = info->regs; 807 size_t hw_size; 808 size_t ram_size = SDRAM_MAX_SIZE; 809 u32 cap_param; 810 811 cap_param = (readl(&info->regs->config) & SDRAM_CONF_CAP_MASK) >> SDRAM_CONF_CAP_SHIFT; 812 switch (cap_param) 813 { 814 case SDRAM_CONF_CAP_2048M: 815 ram_size = 2048 * SDRAM_SIZE_1MB; 816 break; 817 case SDRAM_CONF_CAP_1024M: 818 ram_size = 1024 * SDRAM_SIZE_1MB; 819 break; 820 case SDRAM_CONF_CAP_512M: 821 ram_size = 512 * SDRAM_SIZE_1MB; 822 break; 823 case SDRAM_CONF_CAP_256M: 824 ram_size = 256 * SDRAM_SIZE_1MB; 825 break; 826 } 827 828 info->info.base = CONFIG_SYS_SDRAM_BASE; 829 info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info) - CONFIG_ASPEED_SSP_RERV_MEM; 830 831 if (0 == (readl(®s->config) & SDRAM_CONF_ECC_SETUP)) 832 return; 833 834 hw_size = readl(®s->ecc_range_ctrl) & GENMASK(30, 20); 835 hw_size += (1 << 20); 836 837 info->info.size = hw_size; 838 } 839 #ifdef CONFIG_ASPEED_ECC 840 static void ast2600_sdrammc_ecc_enable(struct dram_info *info) 841 { 842 struct ast2600_sdrammc_regs *regs = info->regs; 843 size_t conf_size; 844 u32 reg; 845 846 conf_size = CONFIG_ASPEED_ECC_SIZE * SDRAM_SIZE_1MB; 847 if (conf_size > info->info.size) { 848 printf("warning: ECC configured %dMB but actual size is %dMB\n", 849 CONFIG_ASPEED_ECC_SIZE, 850 info->info.size / SDRAM_SIZE_1MB); 851 conf_size = info->info.size; 852 } else if (conf_size == 0) { 853 conf_size = info->info.size; 854 } 855 856 info->info.size = (((conf_size / 9) * 8) >> 20) << 20; 857 writel(((info->info.size >> 20) - 1) << 20, ®s->ecc_range_ctrl); 858 reg = readl(®s->config) | SDRAM_CONF_ECC_SETUP; 859 writel(reg, ®s->config); 860 861 writel(0, ®s->test_init_val); 862 writel(0x80000001, ®s->test_addr); 863 writel(0x221, ®s->ecc_test_ctrl); 864 while (0 == (readl(®s->ecc_test_ctrl) & BIT(12))) 865 ; 866 writel(0, ®s->ecc_test_ctrl); 867 writel(BIT(31), ®s->intr_ctrl); 868 writel(0, ®s->intr_ctrl); 869 } 870 #endif 871 872 static int ast2600_sdrammc_probe(struct udevice *dev) 873 { 874 struct dram_info *priv = (struct dram_info *)dev_get_priv(dev); 875 struct ast2600_sdrammc_regs *regs = priv->regs; 876 struct udevice *clk_dev; 877 int ret; 878 volatile uint32_t reg; 879 880 /* find SCU base address from clock device */ 881 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 882 &clk_dev); 883 if (ret) { 884 debug("clock device not defined\n"); 885 return ret; 886 } 887 888 priv->scu = devfdt_get_addr_ptr(clk_dev); 889 if (IS_ERR(priv->scu)) { 890 debug("%s(): can't get SCU\n", __func__); 891 return PTR_ERR(priv->scu); 892 } 893 894 if (readl(priv->scu + AST_SCU_HANDSHAKE) & SCU_SDRAM_INIT_READY_MASK) { 895 printf("already initialized, "); 896 ast2600_sdrammc_update_size(priv); 897 return 0; 898 } 899 900 #ifdef AST2600_SDRAMMC_MANUAL_CLK 901 reg = readl(priv->scu + AST_SCU_MPLL); 902 reg &= ~(BIT(24) | GENMASK(22, 0)); 903 reg |= (BIT(25) | BIT(23) | SCU_MPLL_FREQ_CFG); 904 writel(reg, priv->scu + AST_SCU_MPLL); 905 writel(SCU_MPLL_EXT_CFG, priv->scu + AST_SCU_MPLL_EXT); 906 udelay(100); 907 reg &= ~(BIT(25) | BIT(23)); 908 writel(reg, priv->scu + AST_SCU_MPLL); 909 while(0 == (readl(priv->scu + AST_SCU_MPLL_EXT) & BIT(31))); 910 #else 911 ret = clk_get_by_index(dev, 0, &priv->ddr_clk); 912 if (ret) { 913 debug("DDR:No CLK\n"); 914 return ret; 915 } 916 clk_set_rate(&priv->ddr_clk, priv->clock_rate); 917 #endif 918 919 #if 0 920 /* FIXME: enable the following code if reset-driver is ready */ 921 struct reset_ctl reset_ctl; 922 ret = reset_get_by_index(dev, 0, &reset_ctl); 923 if (ret) { 924 debug("%s(): Failed to get reset signal\n", __func__); 925 return ret; 926 } 927 928 ret = reset_assert(&reset_ctl); 929 if (ret) { 930 debug("%s(): SDRAM reset failed: %u\n", __func__, ret); 931 return ret; 932 } 933 #endif 934 935 ast2600_sdrammc_unlock(priv); 936 ast2600_sdrammc_common_init(regs); 937 L_ast2600_sdramphy_train: 938 ast2600_sdrammc_init_ddr4(priv); 939 940 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM) 941 ast2600_sdrammc_search_read_window(priv); 942 #else 943 /* make sure DDR-PHY is ready before access */ 944 do { 945 reg = readl(priv->phy_status) & BIT(1); 946 } while(reg == 0); 947 #endif 948 949 if (0 != ast2600_sdramphy_check_status(priv)) { 950 printf("DDR4 PHY training fail, retrain\n"); 951 goto L_ast2600_sdramphy_train; 952 } 953 954 ast2600_sdrammc_calc_size(priv); 955 956 #ifndef CONFIG_ASPEED_BYPASS_SELFTEST 957 if (0 != ast2600_sdrammc_test(priv)) { 958 printf("%s: DDR4 init fail\n", __func__); 959 return -EINVAL; 960 } 961 #endif 962 963 #ifdef CONFIG_ASPEED_ECC 964 ast2600_sdrammc_ecc_enable(priv); 965 #endif 966 967 writel(readl(priv->scu + AST_SCU_HANDSHAKE) | SCU_SDRAM_INIT_READY_MASK, 968 priv->scu + AST_SCU_HANDSHAKE); 969 970 clrbits_le32(®s->intr_ctrl, MCR50_RESET_ALL_INTR); 971 ast2600_sdrammc_lock(priv); 972 return 0; 973 } 974 975 static int ast2600_sdrammc_ofdata_to_platdata(struct udevice *dev) 976 { 977 struct dram_info *priv = dev_get_priv(dev); 978 979 priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0); 980 priv->phy_setting = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1); 981 priv->phy_status = (void *)(uintptr_t)devfdt_get_addr_index(dev, 2); 982 983 priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 984 "clock-frequency", 0); 985 if (!priv->clock_rate) { 986 debug("DDR Clock Rate not defined\n"); 987 return -EINVAL; 988 } 989 990 return 0; 991 } 992 993 static int ast2600_sdrammc_get_info(struct udevice *dev, struct ram_info *info) 994 { 995 struct dram_info *priv = dev_get_priv(dev); 996 997 *info = priv->info; 998 999 return 0; 1000 } 1001 1002 static struct ram_ops ast2600_sdrammc_ops = { 1003 .get_info = ast2600_sdrammc_get_info, 1004 }; 1005 1006 static const struct udevice_id ast2600_sdrammc_ids[] = { 1007 { .compatible = "aspeed,ast2600-sdrammc" }, 1008 { } 1009 }; 1010 1011 U_BOOT_DRIVER(sdrammc_ast2600) = { 1012 .name = "aspeed_ast2600_sdrammc", 1013 .id = UCLASS_RAM, 1014 .of_match = ast2600_sdrammc_ids, 1015 .ops = &ast2600_sdrammc_ops, 1016 .ofdata_to_platdata = ast2600_sdrammc_ofdata_to_platdata, 1017 .probe = ast2600_sdrammc_probe, 1018 .priv_auto_alloc_size = sizeof(struct dram_info), 1019 }; 1020