1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * ASPEED AST2500 FMC/SPI Controller driver 4 * 5 * Copyright (c) 2015-2018, IBM Corporation. 6 */ 7 8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 10 #include <common.h> 11 #include <clk.h> 12 #include <dm.h> 13 #include <spi.h> 14 #include <spi_flash.h> 15 #include <asm/io.h> 16 #include <linux/ioport.h> 17 18 #define ASPEED_SPI_MAX_CS 3 19 20 struct aspeed_spi_regs { 21 u32 conf; /* 0x00 CE Type Setting */ 22 u32 ctrl; /* 0x04 Control */ 23 u32 intr_ctrl; /* 0x08 Interrupt Control and Status */ 24 u32 cmd_ctrl; /* 0x0c Command Control */ 25 u32 ce_ctrl[ASPEED_SPI_MAX_CS]; /* 0x10 .. 0x18 CEx Control */ 26 u32 _reserved0[5]; /* .. */ 27 u32 segment_addr[ASPEED_SPI_MAX_CS]; 28 /* 0x30 .. 0x38 Segment Address */ 29 u32 _reserved1[17]; /* .. */ 30 u32 dma_ctrl; /* 0x80 DMA Control/Status */ 31 u32 dma_flash_addr; /* 0x84 DMA Flash Side Address */ 32 u32 dma_dram_addr; /* 0x88 DMA DRAM Side Address */ 33 u32 dma_len; /* 0x8c DMA Length Register */ 34 u32 dma_checksum; /* 0x90 Checksum Calculation Result */ 35 u32 timings; /* 0x94 Read Timing Compensation */ 36 37 /* not used */ 38 u32 soft_strap_status; /* 0x9c Software Strap Status */ 39 u32 write_cmd_filter_ctrl; /* 0xa0 Write Command Filter Control */ 40 u32 write_addr_filter_ctrl; /* 0xa4 Write Address Filter Control */ 41 u32 lock_ctrl_reset; /* 0xa8 Lock Control (SRST#) */ 42 u32 lock_ctrl_wdt; /* 0xac Lock Control (Watchdog) */ 43 u32 write_addr_filter[5]; /* 0xb0 Write Address Filter */ 44 }; 45 46 /* CE Type Setting Register */ 47 #define CONF_ENABLE_W2 BIT(18) 48 #define CONF_ENABLE_W1 BIT(17) 49 #define CONF_ENABLE_W0 BIT(16) 50 #define CONF_FLASH_TYPE2 4 51 #define CONF_FLASH_TYPE1 2 /* Hardwired to SPI */ 52 #define CONF_FLASH_TYPE0 0 /* Hardwired to SPI */ 53 #define CONF_FLASH_TYPE_NOR 0x0 54 #define CONF_FLASH_TYPE_SPI 0x2 55 56 /* CE Control Register */ 57 #define CTRL_EXTENDED2 BIT(2) /* 32 bit addressing for SPI */ 58 #define CTRL_EXTENDED1 BIT(1) /* 32 bit addressing for SPI */ 59 #define CTRL_EXTENDED0 BIT(0) /* 32 bit addressing for SPI */ 60 61 /* Interrupt Control and Status Register */ 62 #define INTR_CTRL_DMA_STATUS BIT(11) 63 #define INTR_CTRL_CMD_ABORT_STATUS BIT(10) 64 #define INTR_CTRL_WRITE_PROTECT_STATUS BIT(9) 65 #define INTR_CTRL_DMA_EN BIT(3) 66 #define INTR_CTRL_CMD_ABORT_EN BIT(2) 67 #define INTR_CTRL_WRITE_PROTECT_EN BIT(1) 68 69 /* CEx Control Register */ 70 #define CE_CTRL_IO_MODE_MASK GENMASK(31, 28) 71 #define CE_CTRL_IO_DUAL_DATA BIT(29) 72 #define CE_CTRL_IO_DUAL_ADDR_DATA (BIT(29) | BIT(28)) 73 #define CE_CTRL_IO_QUAD_DATA BIT(30) 74 #define CE_CTRL_IO_QUAD_ADDR_DATA (BIT(30) | BIT(28)) 75 #define CE_CTRL_CMD_SHIFT 16 76 #define CE_CTRL_CMD_MASK 0xff 77 #define CE_CTRL_CMD(cmd) \ 78 (((cmd) & CE_CTRL_CMD_MASK) << CE_CTRL_CMD_SHIFT) 79 #define CE_CTRL_DUMMY_HIGH_SHIFT 14 80 #define CE_CTRL_DUMMY_HIGH_MASK 0x1 81 #define CE_CTRL_CLOCK_FREQ_SHIFT 8 82 #define CE_CTRL_CLOCK_FREQ_MASK 0xf 83 #define CE_CTRL_CLOCK_FREQ(div) \ 84 (((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT) 85 #define CE_G6_CTRL_CLOCK_FREQ(div) \ 86 ((((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT) | (((div) & 0xf0) << 20)) 87 #define CE_CTRL_DUMMY_LOW_SHIFT 6 /* 2 bits [7:6] */ 88 #define CE_CTRL_DUMMY_LOW_MASK 0x3 89 #define CE_CTRL_DUMMY(dummy) \ 90 (((((dummy) >> 2) & CE_CTRL_DUMMY_HIGH_MASK) \ 91 << CE_CTRL_DUMMY_HIGH_SHIFT) | \ 92 (((dummy) & CE_CTRL_DUMMY_LOW_MASK) << CE_CTRL_DUMMY_LOW_SHIFT)) 93 #define CE_CTRL_STOP_ACTIVE BIT(2) 94 #define CE_CTRL_MODE_MASK 0x3 95 #define CE_CTRL_READMODE 0x0 96 #define CE_CTRL_FREADMODE 0x1 97 #define CE_CTRL_WRITEMODE 0x2 98 #define CE_CTRL_USERMODE 0x3 99 100 /* 101 * The Segment Register uses a 8MB unit to encode the start address 102 * and the end address of the AHB window of a SPI flash device. 103 * Default segment addresses are : 104 * 105 * CE0 0x20000000 - 0x2fffffff 128MB 106 * CE1 0x28000000 - 0x29ffffff 32MB 107 * CE2 0x2a000000 - 0x2bffffff 32MB 108 * 109 * The full address space of the AHB window of the controller is 110 * covered and CE0 start address and CE2 end addresses are read-only. 111 */ 112 #define SEGMENT_ADDR_START(reg) ((((reg) >> 16) & 0xff) << 23) 113 #define SEGMENT_ADDR_END(reg) ((((reg) >> 24) & 0xff) << 23) 114 #define SEGMENT_ADDR_VALUE(start, end) \ 115 (((((start) >> 23) & 0xff) << 16) | ((((end) >> 23) & 0xff) << 24)) 116 117 #define G6_SEGMENT_ADDR_START(reg) (reg & 0xffff) 118 #define G6_SEGMENT_ADDR_END(reg) ((reg >> 16) & 0xffff) 119 #define G6_SEGMENT_ADDR_VALUE(start, end) \ 120 ((((start) >> 16) & 0xffff) | ((end) & 0xffff0000)) 121 122 /* DMA Control/Status Register */ 123 #define DMA_CTRL_DELAY_SHIFT 8 124 #define DMA_CTRL_DELAY_MASK 0xf 125 #define DMA_CTRL_FREQ_SHIFT 4 126 #define DMA_CTRL_FREQ_MASK 0xf 127 #define TIMING_MASK(div, delay) \ 128 (((delay & DMA_CTRL_DELAY_MASK) << DMA_CTRL_DELAY_SHIFT) | \ 129 ((div & DMA_CTRL_FREQ_MASK) << DMA_CTRL_FREQ_SHIFT)) 130 #define DMA_CTRL_CALIB BIT(3) 131 #define DMA_CTRL_CKSUM BIT(2) 132 #define DMA_CTRL_WRITE BIT(1) 133 #define DMA_CTRL_ENABLE BIT(0) 134 135 /* 136 * 137 */ 138 struct aspeed_spi_flash { 139 u8 cs; 140 bool init; /* Initialized when the SPI bus is 141 * first claimed 142 */ 143 void __iomem *ahb_base; /* AHB Window for this device */ 144 u32 ahb_size; /* AHB Window segment size */ 145 u32 ce_ctrl_user; /* CE Control Register for USER mode */ 146 u32 ce_ctrl_fread; /* CE Control Register for FREAD mode */ 147 u32 iomode; 148 149 struct spi_flash *spi; /* Associated SPI Flash device */ 150 }; 151 152 struct aspeed_spi_priv { 153 struct aspeed_spi_regs *regs; 154 void __iomem *ahb_base; /* AHB Window for all flash devices */ 155 int new_ver; 156 u32 ahb_size; /* AHB Window segments size */ 157 158 ulong hclk_rate; /* AHB clock rate */ 159 u32 max_hz; 160 u8 num_cs; 161 bool is_fmc; 162 163 struct aspeed_spi_flash flashes[ASPEED_SPI_MAX_CS]; 164 u32 flash_count; 165 166 u8 cmd_buf[16]; /* SPI command in progress */ 167 size_t cmd_len; 168 }; 169 170 static struct aspeed_spi_flash *aspeed_spi_get_flash(struct udevice *dev) 171 { 172 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 173 struct aspeed_spi_priv *priv = dev_get_priv(dev->parent); 174 u8 cs = slave_plat->cs; 175 176 if (cs >= priv->flash_count) { 177 pr_err("invalid CS %u\n", cs); 178 return NULL; 179 } 180 181 return &priv->flashes[cs]; 182 } 183 184 static u32 aspeed_g6_spi_hclk_divisor(struct aspeed_spi_priv *priv, u32 max_hz) 185 { 186 u32 hclk_rate = priv->hclk_rate; 187 /* HCLK/1 .. HCLK/16 */ 188 const u8 hclk_masks[] = { 189 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0 190 }; 191 u8 base_div = 0; 192 // int done = 0; 193 u32 i, j; 194 u32 hclk_div_setting = 0; 195 196 //for ast2600 spi freq = hclk / (([27:24] * 16) + [11:8]) 197 for (j = 0; j < ARRAY_SIZE(hclk_masks); i++) { 198 for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) { 199 if (max_hz >= (hclk_rate / ((i + 1) + (j * 16)))) { 200 base_div = j * 16; 201 // done = 1; 202 break; 203 } 204 } 205 // if (done) 206 // break; 207 if( j == 0) break; // todo check 208 } 209 210 printf("hclk=%d required=%d base_div is %d (mask %x, base_div %x) speed=%d\n", 211 hclk_rate, max_hz, i + 1, hclk_masks[i], base_div, hclk_rate / ((i + 1) + base_div)); 212 213 hclk_div_setting = ((j << 4) | hclk_masks[i]); 214 215 return hclk_div_setting; 216 217 } 218 219 static u32 aspeed_spi_hclk_divisor(struct aspeed_spi_priv *priv, u32 max_hz) 220 { 221 u32 hclk_rate = priv->hclk_rate; 222 /* HCLK/1 .. HCLK/16 */ 223 const u8 hclk_masks[] = { 224 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0 225 }; 226 u8 base_div = 0; 227 // int done = 0; 228 u32 i, j; 229 u32 hclk_div_setting = 0; 230 231 for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) { 232 if (max_hz >= (hclk_rate / (i + 1))) 233 break; 234 } 235 debug("hclk=%d required=%d divisor is %d (mask %x) speed=%d\n", 236 hclk_rate, max_hz, i + 1, hclk_masks[i], hclk_rate / (i + 1)); 237 238 hclk_div_setting = hclk_masks[i]; 239 240 return hclk_div_setting; 241 } 242 243 /* 244 * Use some address/size under the first flash device CE0 245 */ 246 static u32 aspeed_spi_fmc_checksum(struct aspeed_spi_priv *priv, u8 div, 247 u8 delay) 248 { 249 u32 flash_addr = (u32)priv->ahb_base + 0x10000; 250 u32 flash_len = 0x200; 251 u32 dma_ctrl; 252 u32 checksum; 253 254 writel(flash_addr, &priv->regs->dma_flash_addr); 255 writel(flash_len, &priv->regs->dma_len); 256 257 /* 258 * When doing calibration, the SPI clock rate in the CE0 259 * Control Register and the data input delay cycles in the 260 * Read Timing Compensation Register are replaced by bit[11:4]. 261 */ 262 dma_ctrl = DMA_CTRL_ENABLE | DMA_CTRL_CKSUM | DMA_CTRL_CALIB | 263 TIMING_MASK(div, delay); 264 writel(dma_ctrl, &priv->regs->dma_ctrl); 265 266 while (!(readl(&priv->regs->intr_ctrl) & INTR_CTRL_DMA_STATUS)) 267 ; 268 269 writel(0x0, &priv->regs->intr_ctrl); 270 271 checksum = readl(&priv->regs->dma_checksum); 272 273 writel(0x0, &priv->regs->dma_ctrl); 274 275 return checksum; 276 } 277 278 static u32 aspeed_spi_read_checksum(struct aspeed_spi_priv *priv, u8 div, 279 u8 delay) 280 { 281 /* TODO(clg@kaod.org): the SPI controllers do not have the DMA 282 * registers. The algorithm is the same. 283 */ 284 if (!priv->is_fmc) { 285 pr_warn("No timing calibration support for SPI controllers"); 286 return 0xbadc0de; 287 } 288 289 return aspeed_spi_fmc_checksum(priv, div, delay); 290 } 291 292 #define TIMING_DELAY_DI_4NS BIT(3) 293 #define TIMING_DELAY_HCYCLE_MAX 5 294 295 static int aspeed_spi_timing_calibration(struct aspeed_spi_priv *priv) 296 { 297 /* HCLK/5 .. HCLK/1 */ 298 const u8 hclk_masks[] = { 13, 6, 14, 7, 15 }; 299 u32 timing_reg = 0; 300 u32 checksum, gold_checksum; 301 int i, hcycle; 302 303 debug("Read timing calibration :\n"); 304 305 /* Compute reference checksum at lowest freq HCLK/16 */ 306 gold_checksum = aspeed_spi_read_checksum(priv, 0, 0); 307 308 /* 309 * Set CE0 Control Register to FAST READ command mode. The 310 * HCLK divisor will be set through the DMA Control Register. 311 */ 312 writel(CE_CTRL_CMD(0xb) | CE_CTRL_DUMMY(1) | CE_CTRL_FREADMODE, 313 &priv->regs->ce_ctrl[0]); 314 315 /* Increase HCLK freq */ 316 if (priv->new_ver) { 317 for (i = 0; i < ARRAY_SIZE(hclk_masks) - 1; i++) { 318 u32 hdiv = 5 - i; 319 u32 hshift = (hdiv - 1) << 2; 320 bool pass = false; 321 u8 delay; 322 323 if (priv->hclk_rate / hdiv > priv->max_hz) { 324 debug("skipping freq %ld\n", priv->hclk_rate / hdiv); 325 continue; 326 } 327 328 /* Increase HCLK cycles until read succeeds */ 329 for (hcycle = 0; hcycle <= TIMING_DELAY_HCYCLE_MAX; hcycle++) { 330 /* Try first with a 4ns DI delay */ 331 delay = TIMING_DELAY_DI_4NS | hcycle; 332 checksum = aspeed_spi_read_checksum(priv, hclk_masks[i], 333 delay); 334 pass = (checksum == gold_checksum); 335 printf(" HCLK/%d, 4ns DI delay, %d HCLK cycle : %s\n", 336 hdiv, hcycle, pass ? "PASS" : "FAIL"); 337 338 /* Try again with more HCLK cycles */ 339 if (!pass) 340 continue; 341 342 /* Try without the 4ns DI delay */ 343 delay = hcycle; 344 checksum = aspeed_spi_read_checksum(priv, hclk_masks[i], 345 delay); 346 pass = (checksum == gold_checksum); 347 printf(" HCLK/%d, no DI delay, %d HCLK cycle : %s\n", 348 hdiv, hcycle, pass ? "PASS" : "FAIL"); 349 350 /* All good for this freq */ 351 if (pass) 352 break; 353 } 354 355 if (pass) { 356 timing_reg &= ~(0xfu << hshift); 357 timing_reg |= delay << hshift; 358 } 359 } 360 } else { 361 for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) { 362 u32 hdiv = 5 - i; 363 u32 hshift = (hdiv - 1) << 2; 364 bool pass = false; 365 u8 delay; 366 367 if (priv->hclk_rate / hdiv > priv->max_hz) { 368 debug("skipping freq %ld\n", priv->hclk_rate / hdiv); 369 continue; 370 } 371 372 /* Increase HCLK cycles until read succeeds */ 373 for (hcycle = 0; hcycle <= TIMING_DELAY_HCYCLE_MAX; hcycle++) { 374 /* Try first with a 4ns DI delay */ 375 delay = TIMING_DELAY_DI_4NS | hcycle; 376 checksum = aspeed_spi_read_checksum(priv, hclk_masks[i], 377 delay); 378 pass = (checksum == gold_checksum); 379 debug(" HCLK/%d, 4ns DI delay, %d HCLK cycle : %s\n", 380 hdiv, hcycle, pass ? "PASS" : "FAIL"); 381 382 /* Try again with more HCLK cycles */ 383 if (!pass) 384 continue; 385 386 /* Try without the 4ns DI delay */ 387 delay = hcycle; 388 checksum = aspeed_spi_read_checksum(priv, hclk_masks[i], 389 delay); 390 pass = (checksum == gold_checksum); 391 debug(" HCLK/%d, no DI delay, %d HCLK cycle : %s\n", 392 hdiv, hcycle, pass ? "PASS" : "FAIL"); 393 394 /* All good for this freq */ 395 if (pass) 396 break; 397 } 398 399 if (pass) { 400 timing_reg &= ~(0xfu << hshift); 401 timing_reg |= delay << hshift; 402 } 403 } 404 } 405 debug("Read Timing Compensation set to 0x%08x\n", timing_reg); 406 writel(timing_reg, &priv->regs->timings); 407 408 /* Reset CE0 Control Register */ 409 writel(0x0, &priv->regs->ce_ctrl[0]); 410 411 return 0; 412 } 413 414 static int aspeed_spi_controller_init(struct aspeed_spi_priv *priv) 415 { 416 int cs, ret; 417 418 /* 419 * Enable write on all flash devices as USER command mode 420 * requires it. 421 */ 422 setbits_le32(&priv->regs->conf, 423 CONF_ENABLE_W2 | CONF_ENABLE_W1 | CONF_ENABLE_W0); 424 425 /* 426 * Set the Read Timing Compensation Register. This setting 427 * applies to all devices. 428 */ 429 ret = aspeed_spi_timing_calibration(priv); 430 if (ret) 431 return ret; 432 433 /* 434 * Set safe default settings for each device. These will be 435 * tuned after the SPI flash devices are probed. 436 */ 437 if (priv->new_ver) { 438 for (cs = 0; cs < priv->flash_count; cs++) { 439 struct aspeed_spi_flash *flash = &priv->flashes[cs]; 440 u32 seg_addr = readl(&priv->regs->segment_addr[cs]); 441 switch(cs) { 442 case 0: 443 flash->ahb_base = cs ? (void *)G6_SEGMENT_ADDR_START(seg_addr) : 444 priv->ahb_base; 445 printf("cs0 mem-map : %x ", (u32)flash->ahb_base); 446 break; 447 case 1: 448 flash->ahb_base = priv->flashes[0].ahb_base + 0x8000000; //cs0 + 128Mb 449 printf("cs1 mem-map : %x ", (u32)flash->ahb_base); 450 break; 451 case 2: 452 flash->ahb_base = priv->flashes[0].ahb_base + 0xc000000; //cs0 + 196Mb 453 printf("cs2 mem-map : %x ", (u32)flash->ahb_base); 454 break; 455 } 456 flash->cs = cs; 457 flash->ce_ctrl_user = CE_CTRL_USERMODE; 458 flash->ce_ctrl_fread = CE_CTRL_READMODE; 459 } 460 } else { 461 for (cs = 0; cs < priv->flash_count; cs++) { 462 struct aspeed_spi_flash *flash = &priv->flashes[cs]; 463 u32 seg_addr = readl(&priv->regs->segment_addr[cs]); 464 /* 465 * The start address of the AHB window of CE0 is 466 * read-only and is the same as the address of the 467 * overall AHB window of the controller for all flash 468 * devices. 469 */ 470 flash->ahb_base = cs ? (void *)SEGMENT_ADDR_START(seg_addr) : 471 priv->ahb_base; 472 473 flash->cs = cs; 474 flash->ce_ctrl_user = CE_CTRL_USERMODE; 475 flash->ce_ctrl_fread = CE_CTRL_READMODE; 476 } 477 } 478 return 0; 479 } 480 481 static int aspeed_spi_read_from_ahb(void __iomem *ahb_base, void *buf, 482 size_t len) 483 { 484 size_t offset = 0; 485 486 if (!((uintptr_t)buf % 4)) { 487 readsl(ahb_base, buf, len >> 2); 488 offset = len & ~0x3; 489 len -= offset; 490 } 491 readsb(ahb_base, (u8 *)buf + offset, len); 492 493 return 0; 494 } 495 496 static int aspeed_spi_write_to_ahb(void __iomem *ahb_base, const void *buf, 497 size_t len) 498 { 499 size_t offset = 0; 500 501 if (!((uintptr_t)buf % 4)) { 502 writesl(ahb_base, buf, len >> 2); 503 offset = len & ~0x3; 504 len -= offset; 505 } 506 writesb(ahb_base, (u8 *)buf + offset, len); 507 508 return 0; 509 } 510 511 static void aspeed_spi_start_user(struct aspeed_spi_priv *priv, 512 struct aspeed_spi_flash *flash) 513 { 514 u32 ctrl_reg = flash->ce_ctrl_user | CE_CTRL_STOP_ACTIVE; 515 516 /* Deselect CS and set USER command mode */ 517 writel(ctrl_reg, &priv->regs->ce_ctrl[flash->cs]); 518 519 /* Select CS */ 520 clrbits_le32(&priv->regs->ce_ctrl[flash->cs], CE_CTRL_STOP_ACTIVE); 521 } 522 523 static void aspeed_spi_stop_user(struct aspeed_spi_priv *priv, 524 struct aspeed_spi_flash *flash) 525 { 526 /* Deselect CS first */ 527 setbits_le32(&priv->regs->ce_ctrl[flash->cs], CE_CTRL_STOP_ACTIVE); 528 529 /* Restore default command mode */ 530 writel(flash->ce_ctrl_fread, &priv->regs->ce_ctrl[flash->cs]); 531 } 532 533 static int aspeed_spi_read_reg(struct aspeed_spi_priv *priv, 534 struct aspeed_spi_flash *flash, 535 u8 opcode, u8 *read_buf, int len) 536 { 537 aspeed_spi_start_user(priv, flash); 538 aspeed_spi_write_to_ahb(flash->ahb_base, &opcode, 1); 539 aspeed_spi_read_from_ahb(flash->ahb_base, read_buf, len); 540 aspeed_spi_stop_user(priv, flash); 541 542 return 0; 543 } 544 545 static int aspeed_spi_write_reg(struct aspeed_spi_priv *priv, 546 struct aspeed_spi_flash *flash, 547 u8 opcode, const u8 *write_buf, int len) 548 { 549 aspeed_spi_start_user(priv, flash); 550 aspeed_spi_write_to_ahb(flash->ahb_base, &opcode, 1); 551 aspeed_spi_write_to_ahb(flash->ahb_base, write_buf, len); 552 aspeed_spi_stop_user(priv, flash); 553 554 switch(opcode) { 555 case SPINOR_OP_EN4B: 556 writel(readl(&priv->regs->ctrl) | BIT(flash->cs), &priv->regs->ctrl); 557 break; 558 case SPINOR_OP_EX4B: 559 writel(readl(&priv->regs->ctrl) & ~BIT(flash->cs), &priv->regs->ctrl); 560 break; 561 } 562 return 0; 563 } 564 565 static void aspeed_spi_send_cmd_addr(struct aspeed_spi_priv *priv, 566 struct aspeed_spi_flash *flash, 567 const u8 *cmdbuf, unsigned int cmdlen) 568 { 569 int i; 570 u8 byte0 = 0x0; 571 u8 addrlen = cmdlen - 1; 572 573 /* First, send the opcode */ 574 aspeed_spi_write_to_ahb(flash->ahb_base, &cmdbuf[0], 1); 575 576 /* 577 * The controller is configured for 4BYTE address mode. Fix 578 * the address width and send an extra byte if the SPI Flash 579 * layer uses 3 bytes addresses. 580 */ 581 if (addrlen == 3 && readl(&priv->regs->ctrl) & BIT(flash->cs)) 582 aspeed_spi_write_to_ahb(flash->ahb_base, &byte0, 1); 583 584 /* Then the address */ 585 for (i = 1 ; i < cmdlen; i++) 586 aspeed_spi_write_to_ahb(flash->ahb_base, &cmdbuf[i], 1); 587 } 588 589 static ssize_t aspeed_spi_read_user(struct aspeed_spi_priv *priv, 590 struct aspeed_spi_flash *flash, 591 unsigned int cmdlen, const u8 *cmdbuf, 592 unsigned int len, u8 *read_buf) 593 { 594 u8 dummy = 0xff; 595 int i; 596 597 aspeed_spi_start_user(priv, flash); 598 599 /* cmd buffer = cmd + addr + dummies */ 600 aspeed_spi_send_cmd_addr(priv, flash, cmdbuf, 601 cmdlen - (flash->spi->read_dummy/8)); 602 603 for (i = 0 ; i < (flash->spi->read_dummy/8); i++) 604 aspeed_spi_write_to_ahb(flash->ahb_base, &dummy, 1); 605 606 if (flash->iomode) { 607 clrbits_le32(&priv->regs->ce_ctrl[flash->cs], 608 CE_CTRL_IO_MODE_MASK); 609 setbits_le32(&priv->regs->ce_ctrl[flash->cs], flash->iomode); 610 } 611 612 aspeed_spi_read_from_ahb(flash->ahb_base, read_buf, len); 613 aspeed_spi_stop_user(priv, flash); 614 615 return 0; 616 } 617 618 static ssize_t aspeed_spi_write_user(struct aspeed_spi_priv *priv, 619 struct aspeed_spi_flash *flash, 620 unsigned int cmdlen, const u8 *cmdbuf, 621 unsigned int len, const u8 *write_buf) 622 { 623 aspeed_spi_start_user(priv, flash); 624 625 /* cmd buffer = cmd + addr */ 626 aspeed_spi_send_cmd_addr(priv, flash, cmdbuf, cmdlen); 627 aspeed_spi_write_to_ahb(flash->ahb_base, write_buf, len); 628 629 aspeed_spi_stop_user(priv, flash); 630 631 return 0; 632 } 633 634 static u32 aspeed_spi_flash_to_addr(struct aspeed_spi_flash *flash, 635 const u8 *cmdbuf, unsigned int cmdlen) 636 { 637 u8 addrlen = cmdlen - 1; 638 u32 addr = (cmdbuf[1] << 16) | (cmdbuf[2] << 8) | cmdbuf[3]; 639 640 /* 641 * U-Boot SPI Flash layer uses 3 bytes addresses, but it might 642 * change one day 643 */ 644 if (addrlen == 4) 645 addr = (addr << 8) | cmdbuf[4]; 646 647 return addr; 648 } 649 650 /* TODO(clg@kaod.org): add support for XFER_MMAP instead ? */ 651 static ssize_t aspeed_spi_read(struct aspeed_spi_priv *priv, 652 struct aspeed_spi_flash *flash, 653 unsigned int cmdlen, const u8 *cmdbuf, 654 unsigned int len, u8 *read_buf) 655 { 656 /* cmd buffer = cmd + addr + dummies */ 657 u32 offset = aspeed_spi_flash_to_addr(flash, cmdbuf, 658 cmdlen - (flash->spi->read_dummy/8)); 659 660 /* 661 * Switch to USER command mode if the AHB window configured 662 * for the device is too small for the read operation 663 */ 664 if (offset + len >= flash->ahb_size) { 665 return aspeed_spi_read_user(priv, flash, cmdlen, cmdbuf, 666 len, read_buf); 667 } 668 669 memcpy_fromio(read_buf, flash->ahb_base + offset, len); 670 671 return 0; 672 } 673 674 static int aspeed_spi_xfer(struct udevice *dev, unsigned int bitlen, 675 const void *dout, void *din, unsigned long flags) 676 { 677 struct udevice *bus = dev->parent; 678 struct aspeed_spi_priv *priv = dev_get_priv(bus); 679 struct aspeed_spi_flash *flash; 680 u8 *cmd_buf = priv->cmd_buf; 681 size_t data_bytes; 682 int err = 0; 683 684 flash = aspeed_spi_get_flash(dev); 685 if (!flash) 686 return -ENXIO; 687 688 if (flags & SPI_XFER_BEGIN) { 689 /* save command in progress */ 690 priv->cmd_len = bitlen / 8; 691 memcpy(cmd_buf, dout, priv->cmd_len); 692 } 693 694 if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) { 695 /* if start and end bit are set, the data bytes is 0. */ 696 data_bytes = 0; 697 } else { 698 data_bytes = bitlen / 8; 699 } 700 701 debug("CS%u: %s cmd %zu bytes data %zu bytes\n", flash->cs, 702 din ? "read" : "write", priv->cmd_len, data_bytes); 703 704 if ((flags & SPI_XFER_END) || flags == 0) { 705 if (priv->cmd_len == 0) { 706 pr_err("No command is progress !\n"); 707 return -1; 708 } 709 710 if (din && data_bytes) { 711 if (priv->cmd_len == 1) 712 err = aspeed_spi_read_reg(priv, flash, 713 cmd_buf[0], 714 din, data_bytes); 715 else 716 err = aspeed_spi_read(priv, flash, 717 priv->cmd_len, 718 cmd_buf, data_bytes, 719 din); 720 } else if (dout) { 721 if (priv->cmd_len == 1) 722 err = aspeed_spi_write_reg(priv, flash, 723 cmd_buf[0], 724 dout, data_bytes); 725 else 726 err = aspeed_spi_write_user(priv, flash, 727 priv->cmd_len, 728 cmd_buf, data_bytes, 729 dout); 730 } 731 732 if (flags & SPI_XFER_END) { 733 /* clear command */ 734 memset(cmd_buf, 0, sizeof(priv->cmd_buf)); 735 priv->cmd_len = 0; 736 } 737 } 738 739 return err; 740 } 741 742 static int aspeed_spi_child_pre_probe(struct udevice *dev) 743 { 744 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 745 746 debug("pre_probe slave device on CS%u, max_hz %u, mode 0x%x.\n", 747 slave_plat->cs, slave_plat->max_hz, slave_plat->mode); 748 749 if (!aspeed_spi_get_flash(dev)) 750 return -ENXIO; 751 752 return 0; 753 } 754 755 /* 756 * It is possible to automatically define a contiguous address space 757 * on top of all CEs in the AHB window of the controller but it would 758 * require much more work. Let's start with a simple mapping scheme 759 * which should work fine for a single flash device. 760 * 761 * More complex schemes should probably be defined with the device 762 * tree. 763 */ 764 static int aspeed_spi_flash_set_segment(struct aspeed_spi_priv *priv, 765 struct aspeed_spi_flash *flash) 766 { 767 u32 seg_addr; 768 769 /* could be configured through the device tree */ 770 flash->ahb_size = flash->spi->size; 771 772 if (priv->new_ver) { 773 seg_addr = G6_SEGMENT_ADDR_VALUE((u32)flash->ahb_base, 774 (u32)flash->ahb_base + flash->ahb_size); 775 } else { 776 seg_addr = SEGMENT_ADDR_VALUE((u32)flash->ahb_base, 777 (u32)flash->ahb_base + flash->ahb_size); 778 } 779 writel(seg_addr, &priv->regs->segment_addr[flash->cs]); 780 781 return 0; 782 } 783 784 static int aspeed_spi_flash_init(struct aspeed_spi_priv *priv, 785 struct aspeed_spi_flash *flash, 786 struct udevice *dev) 787 { 788 struct spi_flash *spi_flash = dev_get_uclass_priv(dev); 789 struct spi_slave *slave = dev_get_parent_priv(dev); 790 u32 read_hclk; 791 792 /* 793 * The SPI flash device slave should not change, so initialize 794 * it only once. 795 */ 796 if (flash->init) 797 return 0; 798 799 /* 800 * The flash device has not been probed yet. Initial transfers 801 * to read the JEDEC of the device will use the initial 802 * default settings of the registers. 803 */ 804 if (!spi_flash->name) 805 return 0; 806 807 debug("CS%u: init %s flags:%x size:%d page:%d sector:%d erase:%d " 808 "cmds [ erase:%x read=%x write:%x ] dummy:%d\n", 809 flash->cs, 810 spi_flash->name, spi_flash->flags, spi_flash->size, 811 spi_flash->page_size, spi_flash->sector_size, 812 spi_flash->erase_size, spi_flash->erase_opcode, 813 spi_flash->read_opcode, spi_flash->program_opcode, 814 spi_flash->read_dummy); 815 816 flash->spi = spi_flash; 817 818 flash->ce_ctrl_user = CE_CTRL_USERMODE; 819 820 if(priv->new_ver) 821 read_hclk = aspeed_g6_spi_hclk_divisor(priv, slave->speed); 822 else 823 read_hclk = aspeed_spi_hclk_divisor(priv, slave->speed); 824 825 if (slave->mode & (SPI_RX_DUAL | SPI_TX_DUAL)) { 826 debug("CS%u: setting dual data mode\n", flash->cs); 827 flash->iomode = CE_CTRL_IO_DUAL_DATA; 828 } 829 830 if(priv->new_ver) 831 flash->ce_ctrl_fread = CE_G6_CTRL_CLOCK_FREQ(read_hclk) | 832 flash->iomode | 833 CE_CTRL_CMD(flash->spi->read_opcode) | 834 CE_CTRL_DUMMY((flash->spi->read_dummy/8)) | 835 CE_CTRL_FREADMODE; 836 else 837 flash->ce_ctrl_fread = CE_CTRL_CLOCK_FREQ(read_hclk) | 838 flash->iomode | 839 CE_CTRL_CMD(flash->spi->read_opcode) | 840 CE_CTRL_DUMMY((flash->spi->read_dummy/8)) | 841 CE_CTRL_FREADMODE; 842 843 debug("CS%u: USER mode 0x%08x FREAD mode 0x%08x\n", flash->cs, 844 flash->ce_ctrl_user, flash->ce_ctrl_fread); 845 846 /* Set the CE Control Register default (FAST READ) */ 847 writel(flash->ce_ctrl_fread, &priv->regs->ce_ctrl[flash->cs]); 848 849 /* Set Address Segment Register for direct AHB accesses */ 850 aspeed_spi_flash_set_segment(priv, flash); 851 852 /* All done */ 853 flash->init = true; 854 855 return 0; 856 } 857 858 static int aspeed_spi_claim_bus(struct udevice *dev) 859 { 860 struct udevice *bus = dev->parent; 861 struct aspeed_spi_priv *priv = dev_get_priv(bus); 862 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 863 struct aspeed_spi_flash *flash; 864 865 debug("%s: claim bus CS%u\n", bus->name, slave_plat->cs); 866 867 flash = aspeed_spi_get_flash(dev); 868 if (!flash) 869 return -ENODEV; 870 871 return aspeed_spi_flash_init(priv, flash, dev); 872 } 873 874 static int aspeed_spi_release_bus(struct udevice *dev) 875 { 876 struct udevice *bus = dev->parent; 877 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 878 879 debug("%s: release bus CS%u\n", bus->name, slave_plat->cs); 880 881 if (!aspeed_spi_get_flash(dev)) 882 return -ENODEV; 883 884 return 0; 885 } 886 887 static int aspeed_spi_set_mode(struct udevice *bus, uint mode) 888 { 889 debug("%s: setting mode to %x\n", bus->name, mode); 890 891 if (mode & (SPI_RX_QUAD | SPI_TX_QUAD)) { 892 pr_err("%s invalid QUAD IO mode\n", bus->name); 893 return -EINVAL; 894 } 895 896 /* The CE Control Register is set in claim_bus() */ 897 return 0; 898 } 899 900 static int aspeed_spi_set_speed(struct udevice *bus, uint hz) 901 { 902 debug("%s: setting speed to %u\n", bus->name, hz); 903 904 /* The CE Control Register is set in claim_bus() */ 905 return 0; 906 } 907 908 static int aspeed_spi_count_flash_devices(struct udevice *bus) 909 { 910 ofnode node; 911 int count = 0; 912 913 dev_for_each_subnode(node, bus) { 914 if (ofnode_is_available(node) && 915 ofnode_device_is_compatible(node, "spi-flash")) 916 count++; 917 } 918 919 return count; 920 } 921 922 static int aspeed_spi_bind(struct udevice *bus) 923 { 924 debug("%s assigned req_seq=%d seq=%d\n", bus->name, bus->req_seq, 925 bus->seq); 926 927 return 0; 928 } 929 930 static int aspeed_spi_probe(struct udevice *bus) 931 { 932 struct resource res_regs, res_ahb; 933 struct aspeed_spi_priv *priv = dev_get_priv(bus); 934 struct clk hclk; 935 int ret; 936 937 ret = dev_read_resource(bus, 0, &res_regs); 938 if (ret < 0) 939 return ret; 940 941 priv->regs = (void __iomem *)res_regs.start; 942 943 ret = dev_read_resource(bus, 1, &res_ahb); 944 if (ret < 0) 945 return ret; 946 947 priv->ahb_base = (void __iomem *)res_ahb.start; 948 priv->ahb_size = res_ahb.end - res_ahb.start; 949 950 ret = clk_get_by_index(bus, 0, &hclk); 951 if (ret < 0) { 952 pr_err("%s could not get clock: %d\n", bus->name, ret); 953 return ret; 954 } 955 956 priv->hclk_rate = clk_get_rate(&hclk); 957 clk_free(&hclk); 958 959 priv->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 960 100000000); 961 962 priv->num_cs = dev_read_u32_default(bus, "num-cs", ASPEED_SPI_MAX_CS); 963 964 priv->flash_count = aspeed_spi_count_flash_devices(bus); 965 if (priv->flash_count > priv->num_cs) { 966 pr_err("%s has too many flash devices: %d\n", bus->name, 967 priv->flash_count); 968 return -EINVAL; 969 } 970 971 if (!priv->flash_count) { 972 pr_err("%s has no flash devices ?!\n", bus->name); 973 return -ENODEV; 974 } 975 976 if (device_is_compatible(bus, "aspeed,ast2600-fmc") || 977 device_is_compatible(bus, "aspeed,ast2600-fmc")) { 978 priv->new_ver = 1; 979 } 980 981 /* 982 * There are some slight differences between the FMC and the 983 * SPI controllers 984 */ 985 priv->is_fmc = dev_get_driver_data(bus); 986 987 ret = aspeed_spi_controller_init(priv); 988 if (ret) 989 return ret; 990 991 debug("%s probed regs=%p ahb_base=%p max-hz=%d cs=%d seq=%d\n", 992 bus->name, priv->regs, priv->ahb_base, priv->max_hz, 993 priv->flash_count, bus->seq); 994 995 return 0; 996 } 997 998 static const struct dm_spi_ops aspeed_spi_ops = { 999 .claim_bus = aspeed_spi_claim_bus, 1000 .release_bus = aspeed_spi_release_bus, 1001 .set_mode = aspeed_spi_set_mode, 1002 .set_speed = aspeed_spi_set_speed, 1003 .xfer = aspeed_spi_xfer, 1004 }; 1005 1006 static const struct udevice_id aspeed_spi_ids[] = { 1007 { .compatible = "aspeed,ast2600-fmc", .data = 1 }, 1008 { .compatible = "aspeed,ast2600-spi", .data = 0 }, 1009 { .compatible = "aspeed,ast2500-fmc", .data = 1 }, 1010 { .compatible = "aspeed,ast2500-spi", .data = 0 }, 1011 { } 1012 }; 1013 1014 U_BOOT_DRIVER(aspeed_spi) = { 1015 .name = "aspeed_spi", 1016 .id = UCLASS_SPI, 1017 .of_match = aspeed_spi_ids, 1018 .ops = &aspeed_spi_ops, 1019 .priv_auto_alloc_size = sizeof(struct aspeed_spi_priv), 1020 .child_pre_probe = aspeed_spi_child_pre_probe, 1021 .bind = aspeed_spi_bind, 1022 .probe = aspeed_spi_probe, 1023 }; 1024