1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * ASPEED AST2500 FMC/SPI Controller driver 4 * 5 * Copyright (c) 2015-2018, IBM Corporation. 6 */ 7 8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 10 #include <common.h> 11 #include <clk.h> 12 #include <dm.h> 13 #include <spi.h> 14 #include <spi_flash.h> 15 #include <asm/io.h> 16 #include <linux/ioport.h> 17 18 #define ASPEED_SPI_MAX_CS 3 19 20 struct aspeed_spi_regs { 21 u32 conf; /* 0x00 CE Type Setting */ 22 u32 ctrl; /* 0x04 Control */ 23 u32 intr_ctrl; /* 0x08 Interrupt Control and Status */ 24 u32 cmd_ctrl; /* 0x0c Command Control */ 25 u32 ce_ctrl[ASPEED_SPI_MAX_CS]; /* 0x10 .. 0x18 CEx Control */ 26 u32 _reserved0[5]; /* .. */ 27 u32 segment_addr[ASPEED_SPI_MAX_CS]; 28 /* 0x30 .. 0x38 Segment Address */ 29 u32 _reserved1[17]; /* .. */ 30 u32 dma_ctrl; /* 0x80 DMA Control/Status */ 31 u32 dma_flash_addr; /* 0x84 DMA Flash Side Address */ 32 u32 dma_dram_addr; /* 0x88 DMA DRAM Side Address */ 33 u32 dma_len; /* 0x8c DMA Length Register */ 34 u32 dma_checksum; /* 0x90 Checksum Calculation Result */ 35 u32 timings; /* 0x94 Read Timing Compensation */ 36 37 /* not used */ 38 u32 soft_strap_status; /* 0x9c Software Strap Status */ 39 u32 write_cmd_filter_ctrl; /* 0xa0 Write Command Filter Control */ 40 u32 write_addr_filter_ctrl; /* 0xa4 Write Address Filter Control */ 41 u32 lock_ctrl_reset; /* 0xa8 Lock Control (SRST#) */ 42 u32 lock_ctrl_wdt; /* 0xac Lock Control (Watchdog) */ 43 u32 write_addr_filter[5]; /* 0xb0 Write Address Filter */ 44 }; 45 46 /* CE Type Setting Register */ 47 #define CONF_ENABLE_W2 BIT(18) 48 #define CONF_ENABLE_W1 BIT(17) 49 #define CONF_ENABLE_W0 BIT(16) 50 #define CONF_FLASH_TYPE2 4 51 #define CONF_FLASH_TYPE1 2 /* Hardwired to SPI */ 52 #define CONF_FLASH_TYPE0 0 /* Hardwired to SPI */ 53 #define CONF_FLASH_TYPE_NOR 0x0 54 #define CONF_FLASH_TYPE_SPI 0x2 55 56 /* CE Control Register */ 57 #define CTRL_EXTENDED2 BIT(2) /* 32 bit addressing for SPI */ 58 #define CTRL_EXTENDED1 BIT(1) /* 32 bit addressing for SPI */ 59 #define CTRL_EXTENDED0 BIT(0) /* 32 bit addressing for SPI */ 60 61 /* Interrupt Control and Status Register */ 62 #define INTR_CTRL_DMA_STATUS BIT(11) 63 #define INTR_CTRL_CMD_ABORT_STATUS BIT(10) 64 #define INTR_CTRL_WRITE_PROTECT_STATUS BIT(9) 65 #define INTR_CTRL_DMA_EN BIT(3) 66 #define INTR_CTRL_CMD_ABORT_EN BIT(2) 67 #define INTR_CTRL_WRITE_PROTECT_EN BIT(1) 68 69 /* CEx Control Register */ 70 #define CE_CTRL_IO_MODE_MASK GENMASK(31, 28) 71 #define CE_CTRL_IO_QPI_DATA BIT(31) 72 #define CE_CTRL_IO_DUAL_DATA BIT(29) 73 #define CE_CTRL_IO_DUAL_ADDR_DATA (BIT(29) | BIT(28)) 74 #define CE_CTRL_IO_QUAD_DATA BIT(30) 75 #define CE_CTRL_IO_QUAD_ADDR_DATA (BIT(30) | BIT(28)) 76 #define CE_CTRL_CMD_SHIFT 16 77 #define CE_CTRL_CMD_MASK 0xff 78 #define CE_CTRL_CMD(cmd) \ 79 (((cmd) & CE_CTRL_CMD_MASK) << CE_CTRL_CMD_SHIFT) 80 #define CE_CTRL_DUMMY_HIGH_SHIFT 14 81 #define CE_CTRL_DUMMY_HIGH_MASK 0x1 82 #define CE_CTRL_CLOCK_FREQ_SHIFT 8 83 #define CE_CTRL_CLOCK_FREQ_MASK 0xf 84 #define CE_CTRL_CLOCK_FREQ(div) \ 85 (((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT) 86 #define CE_G6_CTRL_CLOCK_FREQ(div) \ 87 ((((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT) | (((div) & 0xf0) << 20)) 88 #define CE_CTRL_DUMMY_LOW_SHIFT 6 /* 2 bits [7:6] */ 89 #define CE_CTRL_DUMMY_LOW_MASK 0x3 90 #define CE_CTRL_DUMMY(dummy) \ 91 (((((dummy) >> 2) & CE_CTRL_DUMMY_HIGH_MASK) \ 92 << CE_CTRL_DUMMY_HIGH_SHIFT) | \ 93 (((dummy) & CE_CTRL_DUMMY_LOW_MASK) << CE_CTRL_DUMMY_LOW_SHIFT)) 94 #define CE_CTRL_STOP_ACTIVE BIT(2) 95 #define CE_CTRL_MODE_MASK 0x3 96 #define CE_CTRL_READMODE 0x0 97 #define CE_CTRL_FREADMODE 0x1 98 #define CE_CTRL_WRITEMODE 0x2 99 #define CE_CTRL_USERMODE 0x3 100 101 /* 102 * The Segment Register uses a 8MB unit to encode the start address 103 * and the end address of the AHB window of a SPI flash device. 104 * Default segment addresses are : 105 * 106 * CE0 0x20000000 - 0x2fffffff 128MB 107 * CE1 0x28000000 - 0x29ffffff 32MB 108 * CE2 0x2a000000 - 0x2bffffff 32MB 109 * 110 * The full address space of the AHB window of the controller is 111 * covered and CE0 start address and CE2 end addresses are read-only. 112 */ 113 #define SEGMENT_ADDR_START(reg) ((((reg) >> 16) & 0xff) << 23) 114 #define SEGMENT_ADDR_END(reg) ((((reg) >> 24) & 0xff) << 23) 115 #define SEGMENT_ADDR_VALUE(start, end) \ 116 (((((start) >> 23) & 0xff) << 16) | ((((end) >> 23) & 0xff) << 24)) 117 118 #define G6_SEGMENT_ADDR_START(reg) (reg & 0xffff) 119 #define G6_SEGMENT_ADDR_END(reg) ((reg >> 16) & 0xffff) 120 #define G6_SEGMENT_ADDR_VALUE(start, end) \ 121 ((((start) >> 16) & 0xffff) | (((end) - 0x100000) & 0xffff0000)) 122 123 /* DMA Control/Status Register */ 124 #define DMA_CTRL_DELAY_SHIFT 8 125 #define DMA_CTRL_DELAY_MASK 0xf 126 #define DMA_CTRL_FREQ_SHIFT 4 127 #define G6_DMA_CTRL_FREQ_SHIFT 16 128 129 #define DMA_CTRL_FREQ_MASK 0xf 130 #define TIMING_MASK(div, delay) \ 131 (((delay & DMA_CTRL_DELAY_MASK) << DMA_CTRL_DELAY_SHIFT) | \ 132 ((div & DMA_CTRL_FREQ_MASK) << DMA_CTRL_FREQ_SHIFT)) 133 #define G6_TIMING_MASK(div, delay) \ 134 (((delay & DMA_CTRL_DELAY_MASK) << DMA_CTRL_DELAY_SHIFT) | \ 135 ((div & DMA_CTRL_FREQ_MASK) << G6_DMA_CTRL_FREQ_SHIFT)) 136 #define DMA_CTRL_CALIB BIT(3) 137 #define DMA_CTRL_CKSUM BIT(2) 138 #define DMA_CTRL_WRITE BIT(1) 139 #define DMA_CTRL_ENABLE BIT(0) 140 141 /* 142 * 143 */ 144 struct aspeed_spi_flash { 145 u8 cs; 146 bool init; /* Initialized when the SPI bus is 147 * first claimed 148 */ 149 void __iomem *ahb_base; /* AHB Window for this device */ 150 u32 ahb_size; /* AHB Window segment size */ 151 u32 ce_ctrl_user; /* CE Control Register for USER mode */ 152 u32 ce_ctrl_fread; /* CE Control Register for FREAD mode */ 153 u32 iomode; 154 155 struct spi_flash *spi; /* Associated SPI Flash device */ 156 }; 157 158 struct aspeed_spi_priv { 159 struct aspeed_spi_regs *regs; 160 void __iomem *ahb_base; /* AHB Window for all flash devices */ 161 int new_ver; 162 u32 ahb_size; /* AHB Window segments size */ 163 164 ulong hclk_rate; /* AHB clock rate */ 165 u32 max_hz; 166 u8 num_cs; 167 bool is_fmc; 168 169 struct aspeed_spi_flash flashes[ASPEED_SPI_MAX_CS]; 170 u32 flash_count; 171 172 u8 cmd_buf[16]; /* SPI command in progress */ 173 size_t cmd_len; 174 }; 175 176 static struct aspeed_spi_flash *aspeed_spi_get_flash(struct udevice *dev) 177 { 178 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 179 struct aspeed_spi_priv *priv = dev_get_priv(dev->parent); 180 u8 cs = slave_plat->cs; 181 182 if (cs >= priv->flash_count) { 183 pr_err("invalid CS %u\n", cs); 184 return NULL; 185 } 186 187 return &priv->flashes[cs]; 188 } 189 190 static u32 aspeed_g6_spi_hclk_divisor(struct aspeed_spi_priv *priv, u32 max_hz) 191 { 192 u32 hclk_rate = priv->hclk_rate; 193 /* HCLK/1 .. HCLK/16 */ 194 const u8 hclk_masks[] = { 195 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0 196 }; 197 u8 base_div = 0; 198 int done = 0; 199 u32 i, j = 0; 200 u32 hclk_div_setting = 0; 201 202 for (j = 0; j < 0xf; i++) { 203 for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) { 204 base_div = j * 16; 205 if (max_hz >= (hclk_rate / ((i + 1) + base_div))) { 206 207 done = 1; 208 break; 209 } 210 } 211 if (done) 212 break; 213 } 214 215 debug("hclk=%d required=%d h_div %d, divisor is %d (mask %x) speed=%d\n", 216 hclk_rate, max_hz, j, i + 1, hclk_masks[i], hclk_rate / (i + 1 + base_div)); 217 218 hclk_div_setting = ((j << 4) | hclk_masks[i]); 219 220 return hclk_div_setting; 221 222 } 223 224 static u32 aspeed_spi_hclk_divisor(struct aspeed_spi_priv *priv, u32 max_hz) 225 { 226 u32 hclk_rate = priv->hclk_rate; 227 /* HCLK/1 .. HCLK/16 */ 228 const u8 hclk_masks[] = { 229 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0 230 }; 231 u32 i; 232 u32 hclk_div_setting = 0; 233 234 for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) { 235 if (max_hz >= (hclk_rate / (i + 1))) 236 break; 237 } 238 debug("hclk=%d required=%d divisor is %d (mask %x) speed=%d\n", 239 hclk_rate, max_hz, i + 1, hclk_masks[i], hclk_rate / (i + 1)); 240 241 hclk_div_setting = hclk_masks[i]; 242 243 return hclk_div_setting; 244 } 245 246 /* 247 * Use some address/size under the first flash device CE0 248 */ 249 static u32 aspeed_spi_fmc_checksum(struct aspeed_spi_priv *priv, u8 div, 250 u8 delay) 251 { 252 u32 flash_addr = (u32)priv->ahb_base + 0x10000; 253 u32 flash_len = 0x200; 254 u32 dma_ctrl; 255 u32 checksum; 256 257 writel(flash_addr, &priv->regs->dma_flash_addr); 258 writel(flash_len, &priv->regs->dma_len); 259 260 /* 261 * When doing calibration, the SPI clock rate in the CE0 262 * Control Register and the data input delay cycles in the 263 * Read Timing Compensation Register are replaced by bit[11:4]. 264 */ 265 if(priv->new_ver) 266 dma_ctrl = DMA_CTRL_ENABLE | DMA_CTRL_CKSUM | DMA_CTRL_CALIB | 267 G6_TIMING_MASK(div, delay); 268 else 269 dma_ctrl = DMA_CTRL_ENABLE | DMA_CTRL_CKSUM | DMA_CTRL_CALIB | 270 TIMING_MASK(div, delay); 271 writel(dma_ctrl, &priv->regs->dma_ctrl); 272 273 while (!(readl(&priv->regs->intr_ctrl) & INTR_CTRL_DMA_STATUS)) 274 ; 275 276 writel(0x0, &priv->regs->intr_ctrl); 277 278 checksum = readl(&priv->regs->dma_checksum); 279 280 writel(0x0, &priv->regs->dma_ctrl); 281 282 return checksum; 283 } 284 285 static u32 aspeed_spi_read_checksum(struct aspeed_spi_priv *priv, u8 div, 286 u8 delay) 287 { 288 /* TODO(clg@kaod.org): the SPI controllers do not have the DMA 289 * registers. The algorithm is the same. 290 */ 291 if (!priv->is_fmc) { 292 pr_warn("No timing calibration support for SPI controllers"); 293 return 0xbadc0de; 294 } 295 296 return aspeed_spi_fmc_checksum(priv, div, delay); 297 } 298 299 #define TIMING_DELAY_DI_4NS BIT(3) 300 #define TIMING_DELAY_HCYCLE_MAX 5 301 302 static int aspeed_spi_timing_calibration(struct aspeed_spi_priv *priv) 303 { 304 /* HCLK/5 .. HCLK/1 */ 305 const u8 hclk_masks[] = { 13, 6, 14, 7, 15 }; 306 u32 timing_reg = 0; 307 u32 checksum, gold_checksum; 308 int i, hcycle, delay_ns; 309 310 debug("Read timing calibration :\n"); 311 312 /* Compute reference checksum at lowest freq HCLK/16 */ 313 gold_checksum = aspeed_spi_read_checksum(priv, 0, 0); 314 315 /* 316 * Set CE0 Control Register to FAST READ command mode. The 317 * HCLK divisor will be set through the DMA Control Register. 318 */ 319 writel(CE_CTRL_CMD(0xb) | CE_CTRL_DUMMY(1) | CE_CTRL_FREADMODE, 320 &priv->regs->ce_ctrl[0]); 321 322 /* Increase HCLK freq */ 323 if (priv->new_ver) { 324 for (i = 0; i < ARRAY_SIZE(hclk_masks) - 1; i++) { 325 u32 hdiv = 5 - i; 326 u32 hshift = (hdiv - 2) * 8; 327 bool pass = false; 328 u8 delay; 329 u16 first_delay = 0; 330 u16 end_delay = 0; 331 u32 cal_tmp; 332 debug(" hdiv %d, hshift %d \n", hdiv, hshift); 333 if (priv->hclk_rate / hdiv > priv->max_hz) { 334 debug("skipping freq %ld\n", priv->hclk_rate / hdiv); 335 continue; 336 } 337 338 /* Try without the 4ns DI delay */ 339 hcycle = delay = 0; 340 debug("** Dealy Disable ** \n"); 341 checksum = aspeed_spi_read_checksum(priv, hclk_masks[i], delay); 342 pass = (checksum == gold_checksum); 343 debug(" HCLK/%d, no DI delay, %d HCLK cycle : %s\n", 344 hdiv, hcycle, pass ? "PASS" : "FAIL"); 345 346 /* All good for this freq */ 347 if (pass) 348 goto next_div; 349 350 /* Increase HCLK cycles until read succeeds */ 351 for (hcycle = 0; hcycle <= TIMING_DELAY_HCYCLE_MAX; hcycle++) { 352 /* Try first with a 4ns DI delay */ 353 delay = TIMING_DELAY_DI_4NS | hcycle; 354 debug("** Delay Enable : hcycle %x ** \n", hcycle); 355 for (delay_ns = 0; delay_ns < 0xf; delay_ns++) { 356 delay |= (delay_ns << 4); 357 checksum = aspeed_spi_read_checksum(priv, hclk_masks[i], 358 delay); 359 pass = (checksum == gold_checksum); 360 debug(" HCLK/%d, 4ns DI delay, %d HCLK cycle, %d delay_ns : %s\n", 361 hdiv, hcycle, delay_ns, pass ? "PASS" : "FAIL"); 362 363 /* Try again with more HCLK cycles */ 364 if (!pass) { 365 if (!first_delay) 366 continue; 367 else { 368 end_delay = (hcycle << 4) | (delay_ns); 369 end_delay = end_delay - 1; 370 pass = 1; 371 debug("find end_delay %x %d %d\n", end_delay, hcycle, delay_ns); 372 break; 373 } 374 } else { 375 if (!first_delay) { 376 first_delay = (hcycle << 4) | delay_ns; 377 debug("find first_delay %x %d %d\n", first_delay, hcycle, delay_ns); 378 } 379 if (!end_delay) 380 pass = 0; 381 } 382 } 383 384 if (pass) { 385 cal_tmp = (first_delay + end_delay) / 2; 386 delay = TIMING_DELAY_DI_4NS | ((cal_tmp & 0xf) << 4) | (cal_tmp >> 4); 387 break; 388 } 389 } 390 next_div: 391 if (pass) { 392 timing_reg &= ~(0xfu << hshift); 393 timing_reg |= delay << hshift; 394 debug("timing_reg %x, delay %x, hshift bit %d\n",timing_reg, delay, hshift); 395 } 396 } 397 } else { 398 for (i = 0; i < ARRAY_SIZE(hclk_masks); i++) { 399 u32 hdiv = 5 - i; 400 u32 hshift = (hdiv - 1) << 2; 401 bool pass = false; 402 u8 delay; 403 404 if (priv->hclk_rate / hdiv > priv->max_hz) { 405 debug("skipping freq %ld\n", priv->hclk_rate / hdiv); 406 continue; 407 } 408 409 /* Increase HCLK cycles until read succeeds */ 410 for (hcycle = 0; hcycle <= TIMING_DELAY_HCYCLE_MAX; hcycle++) { 411 /* Try first with a 4ns DI delay */ 412 delay = TIMING_DELAY_DI_4NS | hcycle; 413 checksum = aspeed_spi_read_checksum(priv, hclk_masks[i], 414 delay); 415 pass = (checksum == gold_checksum); 416 debug(" HCLK/%d, 4ns DI delay, %d HCLK cycle : %s\n", 417 hdiv, hcycle, pass ? "PASS" : "FAIL"); 418 419 /* Try again with more HCLK cycles */ 420 if (!pass) 421 continue; 422 423 /* Try without the 4ns DI delay */ 424 delay = hcycle; 425 checksum = aspeed_spi_read_checksum(priv, hclk_masks[i], 426 delay); 427 pass = (checksum == gold_checksum); 428 debug(" HCLK/%d, no DI delay, %d HCLK cycle : %s\n", 429 hdiv, hcycle, pass ? "PASS" : "FAIL"); 430 431 /* All good for this freq */ 432 if (pass) 433 break; 434 } 435 436 if (pass) { 437 timing_reg &= ~(0xfu << hshift); 438 timing_reg |= delay << hshift; 439 } 440 } 441 } 442 debug("Read Timing Compensation set to 0x%08x\n", timing_reg); 443 writel(timing_reg, &priv->regs->timings); 444 445 /* Reset CE0 Control Register */ 446 writel(0x0, &priv->regs->ce_ctrl[0]); 447 448 return 0; 449 } 450 451 static int aspeed_spi_controller_init(struct aspeed_spi_priv *priv) 452 { 453 int cs, ret; 454 455 /* 456 * Enable write on all flash devices as USER command mode 457 * requires it. 458 */ 459 setbits_le32(&priv->regs->conf, 460 CONF_ENABLE_W2 | CONF_ENABLE_W1 | CONF_ENABLE_W0); 461 462 /* 463 * Set the Read Timing Compensation Register. This setting 464 * applies to all devices. 465 */ 466 ret = aspeed_spi_timing_calibration(priv); 467 if (ret) 468 return ret; 469 470 /* 471 * Set safe default settings for each device. These will be 472 * tuned after the SPI flash devices are probed. 473 */ 474 if (priv->new_ver) { 475 for (cs = 0; cs < priv->flash_count; cs++) { 476 struct aspeed_spi_flash *flash = &priv->flashes[cs]; 477 u32 seg_addr = readl(&priv->regs->segment_addr[cs]); 478 u32 addr_config = 0; 479 switch(cs) { 480 case 0: 481 flash->ahb_base = cs ? (void *)G6_SEGMENT_ADDR_START(seg_addr) : 482 priv->ahb_base; 483 debug("cs0 mem-map : %x \n", (u32)flash->ahb_base); 484 break; 485 case 1: 486 flash->ahb_base = priv->flashes[0].ahb_base + 0x8000000; //cs0 + 128Mb : use 64MB 487 debug("cs1 mem-map : %x end %x \n", (u32)flash->ahb_base, (u32)flash->ahb_base + 0x4000000); 488 addr_config = G6_SEGMENT_ADDR_VALUE((u32)flash->ahb_base, (u32)flash->ahb_base + 0x4000000); //add 128Mb 489 writel(addr_config, &priv->regs->segment_addr[cs]); 490 break; 491 case 2: 492 flash->ahb_base = priv->flashes[0].ahb_base + 0xc000000; //cs0 + 192Mb : use 64MB 493 debug("cs2 mem-map : %x end %x \n", (u32)flash->ahb_base, (u32)flash->ahb_base + 0x4000000); 494 addr_config = G6_SEGMENT_ADDR_VALUE((u32)flash->ahb_base, (u32)flash->ahb_base + 0x4000000); //add 128Mb 495 writel(addr_config, &priv->regs->segment_addr[cs]); 496 break; 497 } 498 flash->cs = cs; 499 flash->ce_ctrl_user = CE_CTRL_USERMODE; 500 flash->ce_ctrl_fread = CE_CTRL_READMODE; 501 } 502 } else { 503 for (cs = 0; cs < priv->flash_count; cs++) { 504 struct aspeed_spi_flash *flash = &priv->flashes[cs]; 505 u32 seg_addr = readl(&priv->regs->segment_addr[cs]); 506 /* 507 * The start address of the AHB window of CE0 is 508 * read-only and is the same as the address of the 509 * overall AHB window of the controller for all flash 510 * devices. 511 */ 512 flash->ahb_base = cs ? (void *)SEGMENT_ADDR_START(seg_addr) : 513 priv->ahb_base; 514 515 flash->cs = cs; 516 flash->ce_ctrl_user = CE_CTRL_USERMODE; 517 flash->ce_ctrl_fread = CE_CTRL_READMODE; 518 } 519 } 520 return 0; 521 } 522 523 static int aspeed_spi_read_from_ahb(void __iomem *ahb_base, void *buf, 524 size_t len) 525 { 526 size_t offset = 0; 527 528 if (!((uintptr_t)buf % 4)) { 529 readsl(ahb_base, buf, len >> 2); 530 offset = len & ~0x3; 531 len -= offset; 532 } 533 readsb(ahb_base, (u8 *)buf + offset, len); 534 535 return 0; 536 } 537 538 static int aspeed_spi_write_to_ahb(void __iomem *ahb_base, const void *buf, 539 size_t len) 540 { 541 size_t offset = 0; 542 543 if (!((uintptr_t)buf % 4)) { 544 writesl(ahb_base, buf, len >> 2); 545 offset = len & ~0x3; 546 len -= offset; 547 } 548 writesb(ahb_base, (u8 *)buf + offset, len); 549 550 return 0; 551 } 552 553 static void aspeed_spi_start_user(struct aspeed_spi_priv *priv, 554 struct aspeed_spi_flash *flash) 555 { 556 u32 ctrl_reg = flash->ce_ctrl_user | CE_CTRL_STOP_ACTIVE; 557 558 /* Deselect CS and set USER command mode */ 559 writel(ctrl_reg, &priv->regs->ce_ctrl[flash->cs]); 560 561 /* Select CS */ 562 clrbits_le32(&priv->regs->ce_ctrl[flash->cs], CE_CTRL_STOP_ACTIVE); 563 } 564 565 static void aspeed_spi_stop_user(struct aspeed_spi_priv *priv, 566 struct aspeed_spi_flash *flash) 567 { 568 /* Deselect CS first */ 569 setbits_le32(&priv->regs->ce_ctrl[flash->cs], CE_CTRL_STOP_ACTIVE); 570 571 /* Restore default command mode */ 572 writel(flash->ce_ctrl_fread, &priv->regs->ce_ctrl[flash->cs]); 573 } 574 575 static int aspeed_spi_read_reg(struct aspeed_spi_priv *priv, 576 struct aspeed_spi_flash *flash, 577 u8 opcode, u8 *read_buf, int len) 578 { 579 aspeed_spi_start_user(priv, flash); 580 aspeed_spi_write_to_ahb(flash->ahb_base, &opcode, 1); 581 aspeed_spi_read_from_ahb(flash->ahb_base, read_buf, len); 582 aspeed_spi_stop_user(priv, flash); 583 584 return 0; 585 } 586 587 static int aspeed_spi_write_reg(struct aspeed_spi_priv *priv, 588 struct aspeed_spi_flash *flash, 589 u8 opcode, const u8 *write_buf, int len) 590 { 591 aspeed_spi_start_user(priv, flash); 592 aspeed_spi_write_to_ahb(flash->ahb_base, &opcode, 1); 593 aspeed_spi_write_to_ahb(flash->ahb_base, write_buf, len); 594 aspeed_spi_stop_user(priv, flash); 595 596 switch(opcode) { 597 case SPINOR_OP_EN4B: 598 writel(readl(&priv->regs->ctrl) | BIT(flash->cs), &priv->regs->ctrl); 599 break; 600 case SPINOR_OP_EX4B: 601 writel(readl(&priv->regs->ctrl) & ~BIT(flash->cs), &priv->regs->ctrl); 602 break; 603 } 604 return 0; 605 } 606 607 static void aspeed_spi_send_cmd_addr(struct aspeed_spi_priv *priv, 608 struct aspeed_spi_flash *flash, 609 const u8 *cmdbuf, unsigned int cmdlen) 610 { 611 int i; 612 u8 byte0 = 0x0; 613 u8 addrlen = cmdlen - 1; 614 615 /* First, send the opcode */ 616 aspeed_spi_write_to_ahb(flash->ahb_base, &cmdbuf[0], 1); 617 618 /* 619 * The controller is configured for 4BYTE address mode. Fix 620 * the address width and send an extra byte if the SPI Flash 621 * layer uses 3 bytes addresses. 622 */ 623 if (addrlen == 3 && readl(&priv->regs->ctrl) & BIT(flash->cs)) 624 aspeed_spi_write_to_ahb(flash->ahb_base, &byte0, 1); 625 626 /* Then the address */ 627 for (i = 1 ; i < cmdlen; i++) 628 aspeed_spi_write_to_ahb(flash->ahb_base, &cmdbuf[i], 1); 629 } 630 631 static ssize_t aspeed_spi_read_user(struct aspeed_spi_priv *priv, 632 struct aspeed_spi_flash *flash, 633 unsigned int cmdlen, const u8 *cmdbuf, 634 unsigned int len, u8 *read_buf) 635 { 636 u8 dummy = 0xff; 637 int i; 638 639 aspeed_spi_start_user(priv, flash); 640 641 /* cmd buffer = cmd + addr + dummies */ 642 aspeed_spi_send_cmd_addr(priv, flash, cmdbuf, 643 cmdlen - (flash->spi->read_dummy/8)); 644 645 for (i = 0 ; i < (flash->spi->read_dummy/8); i++) 646 aspeed_spi_write_to_ahb(flash->ahb_base, &dummy, 1); 647 648 if (flash->iomode) { 649 clrbits_le32(&priv->regs->ce_ctrl[flash->cs], 650 CE_CTRL_IO_MODE_MASK); 651 setbits_le32(&priv->regs->ce_ctrl[flash->cs], flash->iomode); 652 } 653 654 aspeed_spi_read_from_ahb(flash->ahb_base, read_buf, len); 655 aspeed_spi_stop_user(priv, flash); 656 657 return 0; 658 } 659 660 static ssize_t aspeed_spi_write_user(struct aspeed_spi_priv *priv, 661 struct aspeed_spi_flash *flash, 662 unsigned int cmdlen, const u8 *cmdbuf, 663 unsigned int len, const u8 *write_buf) 664 { 665 aspeed_spi_start_user(priv, flash); 666 667 if(flash->iomode == CE_CTRL_IO_QPI_DATA) 668 writel(flash->ce_ctrl_user | flash->iomode, &priv->regs->ce_ctrl[flash->cs]); 669 670 /* cmd buffer = cmd + addr : normally cmd is use signle mode*/ 671 aspeed_spi_send_cmd_addr(priv, flash, cmdbuf, cmdlen); 672 673 /* data will use io mode */ 674 if(flash->iomode == CE_CTRL_IO_QUAD_DATA) 675 writel(flash->ce_ctrl_user | flash->iomode, &priv->regs->ce_ctrl[flash->cs]); 676 677 aspeed_spi_write_to_ahb(flash->ahb_base, write_buf, len); 678 679 aspeed_spi_stop_user(priv, flash); 680 681 return 0; 682 } 683 684 static u32 aspeed_spi_flash_to_addr(struct aspeed_spi_flash *flash, 685 const u8 *cmdbuf, unsigned int cmdlen) 686 { 687 u8 addrlen = cmdlen - 1; 688 u32 addr = (cmdbuf[1] << 16) | (cmdbuf[2] << 8) | cmdbuf[3]; 689 690 /* 691 * U-Boot SPI Flash layer uses 3 bytes addresses, but it might 692 * change one day 693 */ 694 if (addrlen == 4) 695 addr = (addr << 8) | cmdbuf[4]; 696 697 return addr; 698 } 699 700 /* TODO(clg@kaod.org): add support for XFER_MMAP instead ? */ 701 static ssize_t aspeed_spi_read(struct aspeed_spi_priv *priv, 702 struct aspeed_spi_flash *flash, 703 unsigned int cmdlen, const u8 *cmdbuf, 704 unsigned int len, u8 *read_buf) 705 { 706 /* cmd buffer = cmd + addr + dummies */ 707 u32 offset = aspeed_spi_flash_to_addr(flash, cmdbuf, 708 cmdlen - (flash->spi->read_dummy/8)); 709 710 /* 711 * Switch to USER command mode if the AHB window configured 712 * for the device is too small for the read operation 713 */ 714 if (offset + len >= flash->ahb_size) { 715 return aspeed_spi_read_user(priv, flash, cmdlen, cmdbuf, 716 len, read_buf); 717 } 718 719 memcpy_fromio(read_buf, flash->ahb_base + offset, len); 720 721 return 0; 722 } 723 724 static int aspeed_spi_xfer(struct udevice *dev, unsigned int bitlen, 725 const void *dout, void *din, unsigned long flags) 726 { 727 struct udevice *bus = dev->parent; 728 struct aspeed_spi_priv *priv = dev_get_priv(bus); 729 struct aspeed_spi_flash *flash; 730 u8 *cmd_buf = priv->cmd_buf; 731 size_t data_bytes; 732 int err = 0; 733 734 flash = aspeed_spi_get_flash(dev); 735 if (!flash) 736 return -ENXIO; 737 738 if (flags & SPI_XFER_BEGIN) { 739 /* save command in progress */ 740 priv->cmd_len = bitlen / 8; 741 memcpy(cmd_buf, dout, priv->cmd_len); 742 } 743 744 if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) { 745 /* if start and end bit are set, the data bytes is 0. */ 746 data_bytes = 0; 747 } else { 748 data_bytes = bitlen / 8; 749 } 750 751 debug("CS%u: %s cmd %zu bytes data %zu bytes\n", flash->cs, 752 din ? "read" : "write", priv->cmd_len, data_bytes); 753 754 if ((flags & SPI_XFER_END) || flags == 0) { 755 if (priv->cmd_len == 0) { 756 pr_err("No command is progress !\n"); 757 return -1; 758 } 759 760 if (din && data_bytes) { 761 if (priv->cmd_len == 1) 762 err = aspeed_spi_read_reg(priv, flash, 763 cmd_buf[0], 764 din, data_bytes); 765 else 766 err = aspeed_spi_read(priv, flash, 767 priv->cmd_len, 768 cmd_buf, data_bytes, 769 din); 770 } else if (dout) { 771 if (priv->cmd_len == 1) 772 err = aspeed_spi_write_reg(priv, flash, 773 cmd_buf[0], 774 dout, data_bytes); 775 else 776 err = aspeed_spi_write_user(priv, flash, 777 priv->cmd_len, 778 cmd_buf, data_bytes, 779 dout); 780 } 781 782 if (flags & SPI_XFER_END) { 783 /* clear command */ 784 memset(cmd_buf, 0, sizeof(priv->cmd_buf)); 785 priv->cmd_len = 0; 786 } 787 } 788 789 return err; 790 } 791 792 static int aspeed_spi_child_pre_probe(struct udevice *dev) 793 { 794 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 795 796 debug("pre_probe slave device on CS%u, max_hz %u, mode 0x%x.\n", 797 slave_plat->cs, slave_plat->max_hz, slave_plat->mode); 798 799 if (!aspeed_spi_get_flash(dev)) 800 return -ENXIO; 801 802 return 0; 803 } 804 805 /* 806 * It is possible to automatically define a contiguous address space 807 * on top of all CEs in the AHB window of the controller but it would 808 * require much more work. Let's start with a simple mapping scheme 809 * which should work fine for a single flash device. 810 * 811 * More complex schemes should probably be defined with the device 812 * tree. 813 */ 814 static int aspeed_spi_flash_set_segment(struct aspeed_spi_priv *priv, 815 struct aspeed_spi_flash *flash) 816 { 817 u32 seg_addr; 818 819 /* could be configured through the device tree */ 820 flash->ahb_size = flash->spi->size; 821 822 if (priv->new_ver) { 823 seg_addr = G6_SEGMENT_ADDR_VALUE((u32)flash->ahb_base, 824 (u32)flash->ahb_base + flash->ahb_size); 825 } else { 826 seg_addr = SEGMENT_ADDR_VALUE((u32)flash->ahb_base, 827 (u32)flash->ahb_base + flash->ahb_size); 828 } 829 writel(seg_addr, &priv->regs->segment_addr[flash->cs]); 830 831 return 0; 832 } 833 834 static int aspeed_spi_flash_init(struct aspeed_spi_priv *priv, 835 struct aspeed_spi_flash *flash, 836 struct udevice *dev) 837 { 838 struct spi_flash *spi_flash = dev_get_uclass_priv(dev); 839 struct spi_slave *slave = dev_get_parent_priv(dev); 840 u32 read_hclk; 841 842 /* 843 * The SPI flash device slave should not change, so initialize 844 * it only once. 845 */ 846 if (flash->init) 847 return 0; 848 849 /* 850 * The flash device has not been probed yet. Initial transfers 851 * to read the JEDEC of the device will use the initial 852 * default settings of the registers. 853 */ 854 if (!spi_flash->name) 855 return 0; 856 857 debug("CS%u: init %s flags:%x size:%d page:%d sector:%d erase:%d " 858 "cmds [ erase:%x read=%x write:%x ] dummy:%d\n", 859 flash->cs, 860 spi_flash->name, spi_flash->flags, spi_flash->size, 861 spi_flash->page_size, spi_flash->sector_size, 862 spi_flash->erase_size, spi_flash->erase_opcode, 863 spi_flash->read_opcode, spi_flash->program_opcode, 864 spi_flash->read_dummy); 865 866 flash->spi = spi_flash; 867 868 flash->ce_ctrl_user = CE_CTRL_USERMODE; 869 870 if(priv->new_ver) 871 read_hclk = aspeed_g6_spi_hclk_divisor(priv, slave->speed); 872 else 873 read_hclk = aspeed_spi_hclk_divisor(priv, slave->speed); 874 875 if (slave->mode & (SPI_RX_DUAL | SPI_TX_DUAL)) { 876 debug("CS%u: setting dual data mode\n", flash->cs); 877 flash->iomode = CE_CTRL_IO_DUAL_DATA; 878 flash->spi->read_opcode = SPINOR_OP_READ_1_1_2; 879 } else if (slave->mode & (SPI_RX_QUAD | SPI_TX_QUAD)) { 880 flash->iomode = CE_CTRL_IO_QUAD_DATA; 881 flash->spi->read_opcode = SPINOR_OP_READ_1_4_4; 882 } else { 883 debug("normal read \n"); 884 } 885 886 if(priv->new_ver) { 887 flash->ce_ctrl_fread = CE_G6_CTRL_CLOCK_FREQ(read_hclk) | 888 flash->iomode | 889 CE_CTRL_CMD(flash->spi->read_opcode) | 890 CE_CTRL_DUMMY((flash->spi->read_dummy/8)) | 891 CE_CTRL_FREADMODE; 892 } else { 893 flash->ce_ctrl_fread = CE_CTRL_CLOCK_FREQ(read_hclk) | 894 flash->iomode | 895 CE_CTRL_CMD(flash->spi->read_opcode) | 896 CE_CTRL_DUMMY((flash->spi->read_dummy/8)) | 897 CE_CTRL_FREADMODE; 898 } 899 900 debug("CS%u: USER mode 0x%08x FREAD mode 0x%08x\n", flash->cs, 901 flash->ce_ctrl_user, flash->ce_ctrl_fread); 902 903 /* Set the CE Control Register default (FAST READ) */ 904 writel(flash->ce_ctrl_fread, &priv->regs->ce_ctrl[flash->cs]); 905 906 /* Set Address Segment Register for direct AHB accesses */ 907 aspeed_spi_flash_set_segment(priv, flash); 908 909 /* All done */ 910 flash->init = true; 911 912 return 0; 913 } 914 915 static int aspeed_spi_claim_bus(struct udevice *dev) 916 { 917 struct udevice *bus = dev->parent; 918 struct aspeed_spi_priv *priv = dev_get_priv(bus); 919 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 920 struct aspeed_spi_flash *flash; 921 922 debug("%s: claim bus CS%u\n", bus->name, slave_plat->cs); 923 924 flash = aspeed_spi_get_flash(dev); 925 if (!flash) 926 return -ENODEV; 927 928 return aspeed_spi_flash_init(priv, flash, dev); 929 } 930 931 static int aspeed_spi_release_bus(struct udevice *dev) 932 { 933 struct udevice *bus = dev->parent; 934 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); 935 936 debug("%s: release bus CS%u\n", bus->name, slave_plat->cs); 937 938 if (!aspeed_spi_get_flash(dev)) 939 return -ENODEV; 940 941 return 0; 942 } 943 944 static int aspeed_spi_set_mode(struct udevice *bus, uint mode) 945 { 946 debug("%s: setting mode to %x\n", bus->name, mode); 947 948 if (mode & (SPI_RX_QUAD | SPI_TX_QUAD)) { 949 #ifndef CONFIG_ASPEED_AST2600 950 pr_err("%s invalid QUAD IO mode\n", bus->name); 951 return -EINVAL; 952 #endif 953 } 954 955 /* The CE Control Register is set in claim_bus() */ 956 return 0; 957 } 958 959 static int aspeed_spi_set_speed(struct udevice *bus, uint hz) 960 { 961 debug("%s: setting speed to %u\n", bus->name, hz); 962 963 /* The CE Control Register is set in claim_bus() */ 964 return 0; 965 } 966 967 static int aspeed_spi_count_flash_devices(struct udevice *bus) 968 { 969 ofnode node; 970 int count = 0; 971 972 dev_for_each_subnode(node, bus) { 973 if (ofnode_is_available(node) && 974 ofnode_device_is_compatible(node, "spi-flash")) 975 count++; 976 } 977 978 return count; 979 } 980 981 static int aspeed_spi_bind(struct udevice *bus) 982 { 983 debug("%s assigned req_seq=%d seq=%d\n", bus->name, bus->req_seq, 984 bus->seq); 985 986 return 0; 987 } 988 989 static int aspeed_spi_probe(struct udevice *bus) 990 { 991 struct resource res_regs, res_ahb; 992 struct aspeed_spi_priv *priv = dev_get_priv(bus); 993 struct clk hclk; 994 int ret; 995 996 ret = dev_read_resource(bus, 0, &res_regs); 997 if (ret < 0) 998 return ret; 999 1000 priv->regs = (void __iomem *)res_regs.start; 1001 1002 ret = dev_read_resource(bus, 1, &res_ahb); 1003 if (ret < 0) 1004 return ret; 1005 1006 priv->ahb_base = (void __iomem *)res_ahb.start; 1007 priv->ahb_size = res_ahb.end - res_ahb.start; 1008 1009 ret = clk_get_by_index(bus, 0, &hclk); 1010 if (ret < 0) { 1011 pr_err("%s could not get clock: %d\n", bus->name, ret); 1012 return ret; 1013 } 1014 1015 priv->hclk_rate = clk_get_rate(&hclk); 1016 clk_free(&hclk); 1017 1018 priv->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 1019 100000000); 1020 1021 priv->num_cs = dev_read_u32_default(bus, "num-cs", ASPEED_SPI_MAX_CS); 1022 1023 priv->flash_count = aspeed_spi_count_flash_devices(bus); 1024 if (priv->flash_count > priv->num_cs) { 1025 pr_err("%s has too many flash devices: %d\n", bus->name, 1026 priv->flash_count); 1027 return -EINVAL; 1028 } 1029 1030 if (!priv->flash_count) { 1031 pr_err("%s has no flash devices ?!\n", bus->name); 1032 return -ENODEV; 1033 } 1034 1035 if (device_is_compatible(bus, "aspeed,ast2600-fmc") || 1036 device_is_compatible(bus, "aspeed,ast2600-spi")) { 1037 priv->new_ver = 1; 1038 } 1039 1040 /* 1041 * There are some slight differences between the FMC and the 1042 * SPI controllers 1043 */ 1044 priv->is_fmc = dev_get_driver_data(bus); 1045 1046 ret = aspeed_spi_controller_init(priv); 1047 if (ret) 1048 return ret; 1049 1050 debug("%s probed regs=%p ahb_base=%p max-hz=%d cs=%d seq=%d\n", 1051 bus->name, priv->regs, priv->ahb_base, priv->max_hz, 1052 priv->flash_count, bus->seq); 1053 1054 return 0; 1055 } 1056 1057 static const struct dm_spi_ops aspeed_spi_ops = { 1058 .claim_bus = aspeed_spi_claim_bus, 1059 .release_bus = aspeed_spi_release_bus, 1060 .set_mode = aspeed_spi_set_mode, 1061 .set_speed = aspeed_spi_set_speed, 1062 .xfer = aspeed_spi_xfer, 1063 }; 1064 1065 static const struct udevice_id aspeed_spi_ids[] = { 1066 { .compatible = "aspeed,ast2600-fmc", .data = 1 }, 1067 { .compatible = "aspeed,ast2600-spi", .data = 0 }, 1068 { .compatible = "aspeed,ast2500-fmc", .data = 1 }, 1069 { .compatible = "aspeed,ast2500-spi", .data = 0 }, 1070 { } 1071 }; 1072 1073 U_BOOT_DRIVER(aspeed_spi) = { 1074 .name = "aspeed_spi", 1075 .id = UCLASS_SPI, 1076 .of_match = aspeed_spi_ids, 1077 .ops = &aspeed_spi_ops, 1078 .priv_auto_alloc_size = sizeof(struct aspeed_spi_priv), 1079 .child_pre_probe = aspeed_spi_child_pre_probe, 1080 .bind = aspeed_spi_bind, 1081 .probe = aspeed_spi_probe, 1082 }; 1083