1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * (C) Copyright 2016 Google, Inc 4 * 5 * Copyright (C) ASPEED Technology Inc. 6 * 7 */ 8 9 #include <common.h> 10 #include <clk-uclass.h> 11 #include <dm.h> 12 #include <asm/io.h> 13 #include <asm/arch/scu_ast2500.h> 14 #include <dm/lists.h> 15 #include <dt-bindings/clock/ast2500-clock.h> 16 17 /* 18 * MAC Clock Delay settings, taken from Aspeed SDK 19 */ 20 #define RGMII_TXCLK_ODLY 8 21 #define RMII_RXCLK_IDLY 2 22 23 /* 24 * TGMII Clock Duty constants, taken from Aspeed SDK 25 */ 26 #define RGMII2_TXCK_DUTY 0x66 27 #define RGMII1_TXCK_DUTY 0x64 28 29 #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000) 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 /* 34 * Clock divider/multiplier configuration struct. 35 * For H-PLL and M-PLL the formula is 36 * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) 37 * M - Numerator 38 * N - Denumerator 39 * P - Post Divider 40 * They have the same layout in their control register. 41 * 42 * D-PLL and D2-PLL have extra divider (OD + 1), which is not 43 * yet needed and ignored by clock configurations. 44 */ 45 struct ast2500_div_config { 46 unsigned int num; 47 unsigned int denum; 48 unsigned int post_div; 49 }; 50 51 /* 52 * Get the rate of the M-PLL clock from input clock frequency and 53 * the value of the M-PLL Parameter Register. 54 */ 55 static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg) 56 { 57 const ulong num = (mpll_reg & SCU_MPLL_NUM_MASK) >> SCU_MPLL_NUM_SHIFT; 58 const ulong denum = (mpll_reg & SCU_MPLL_DENUM_MASK) 59 >> SCU_MPLL_DENUM_SHIFT; 60 const ulong post_div = (mpll_reg & SCU_MPLL_POST_MASK) 61 >> SCU_MPLL_POST_SHIFT; 62 63 return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1); 64 } 65 66 /* 67 * Get the rate of the H-PLL clock from input clock frequency and 68 * the value of the H-PLL Parameter Register. 69 */ 70 static ulong ast2500_get_hpll_rate(ulong clkin, u32 hpll_reg) 71 { 72 /* F = clkin * [(M+1) / (N+1)] / (P + 1) */ 73 const ulong num = (hpll_reg & SCU_HPLL_NUM_MASK) >> SCU_HPLL_NUM_SHIFT; 74 const ulong denum = (hpll_reg & SCU_HPLL_DENUM_MASK) 75 >> SCU_HPLL_DENUM_SHIFT; 76 const ulong post_div = (hpll_reg & SCU_HPLL_POST_MASK) 77 >> SCU_HPLL_POST_SHIFT; 78 79 return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1); 80 } 81 82 static ulong ast2500_get_clkin(struct ast2500_scu *scu) 83 { 84 return readl(&scu->hwstrap) & SCU_HWSTRAP_CLKIN_25MHZ 85 ? 25 * 1000 * 1000 : 24 * 1000 * 1000; 86 } 87 88 /** 89 * Get current rate or uart clock 90 * 91 * @scu SCU registers 92 * @uart_index UART index, 1-5 93 * 94 * @return current setting for uart clock rate 95 */ 96 static ulong ast2500_get_uart_clk_rate(struct ast2500_scu *scu, int uart_index) 97 { 98 /* 99 * ast2500 datasheet is very confusing when it comes to UART clocks, 100 * especially when CLKIN = 25 MHz. The settings are in 101 * different registers and it is unclear how they interact. 102 * 103 * This has only been tested with default settings and CLKIN = 24 MHz. 104 */ 105 ulong uart_clkin; 106 107 if (readl(&scu->misc_ctrl2) & 108 (1 << (uart_index - 1 + SCU_MISC2_UARTCLK_SHIFT))) 109 uart_clkin = 192 * 1000 * 1000; 110 else 111 uart_clkin = 24 * 1000 * 1000; 112 113 if (readl(&scu->misc_ctrl1) & SCU_MISC_UARTCLK_DIV13) 114 uart_clkin /= 13; 115 116 return uart_clkin; 117 } 118 119 static ulong ast2500_clk_get_rate(struct clk *clk) 120 { 121 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev); 122 ulong clkin = ast2500_get_clkin(priv->scu); 123 ulong rate; 124 125 switch (clk->id) { 126 //HPLL 127 case ASPEED_CLK_HPLL: 128 rate = ast2500_get_hpll_rate(clkin, readl(&priv->scu->h_pll_param)); 129 break; 130 //HCLK 131 case ASPEED_CLK_AHB: 132 { 133 ulong ahb_div = 1 + ((readl(&priv->scu->hwstrap) 134 & SCU_HWSTRAP_AXIAHB_DIV_MASK) 135 >> SCU_HWSTRAP_AXIAHB_DIV_SHIFT); 136 ulong axi_div = 2; 137 138 rate = ast2500_get_hpll_rate( 139 clkin, readl(&priv->scu->h_pll_param)); 140 rate = rate / axi_div / ahb_div; 141 } 142 break; 143 case MCLK_DDR: 144 rate = ast2500_get_mpll_rate(clkin, 145 readl(&priv->scu->m_pll_param)); 146 break; 147 case BCLK_PCLK: 148 { 149 ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1) 150 & SCU_PCLK_DIV_MASK) 151 >> SCU_PCLK_DIV_SHIFT); 152 rate = ast2500_get_hpll_rate(clkin, 153 readl(&priv-> 154 scu->h_pll_param)); 155 rate = rate / apb_div; 156 } 157 break; 158 case PCLK_UART1: 159 rate = ast2500_get_uart_clk_rate(priv->scu, 1); 160 break; 161 case PCLK_UART2: 162 rate = ast2500_get_uart_clk_rate(priv->scu, 2); 163 break; 164 case PCLK_UART3: 165 rate = ast2500_get_uart_clk_rate(priv->scu, 3); 166 break; 167 case PCLK_UART4: 168 rate = ast2500_get_uart_clk_rate(priv->scu, 4); 169 break; 170 case PCLK_UART5: 171 rate = ast2500_get_uart_clk_rate(priv->scu, 5); 172 break; 173 default: 174 return -ENOENT; 175 } 176 177 return rate; 178 } 179 180 struct ast2500_clock_config { 181 ulong input_rate; 182 ulong rate; 183 struct ast2500_div_config cfg; 184 }; 185 186 static const struct ast2500_clock_config ast2500_clock_config_defaults[] = { 187 { 24000000, 250000000, { .num = 124, .denum = 1, .post_div = 5 } }, 188 }; 189 190 static bool ast2500_get_clock_config_default(ulong input_rate, 191 ulong requested_rate, 192 struct ast2500_div_config *cfg) 193 { 194 int i; 195 196 for (i = 0; i < ARRAY_SIZE(ast2500_clock_config_defaults); i++) { 197 const struct ast2500_clock_config *default_cfg = 198 &ast2500_clock_config_defaults[i]; 199 if (default_cfg->input_rate == input_rate && 200 default_cfg->rate == requested_rate) { 201 *cfg = default_cfg->cfg; 202 return true; 203 } 204 } 205 206 return false; 207 } 208 209 /* 210 * @input_rate - the rate of input clock in Hz 211 * @requested_rate - desired output rate in Hz 212 * @div - this is an IN/OUT parameter, at input all fields of the config 213 * need to be set to their maximum allowed values. 214 * The result (the best config we could find), would also be returned 215 * in this structure. 216 * 217 * @return The clock rate, when the resulting div_config is used. 218 */ 219 static ulong ast2500_calc_clock_config(ulong input_rate, ulong requested_rate, 220 struct ast2500_div_config *cfg) 221 { 222 /* 223 * The assumption is that kHz precision is good enough and 224 * also enough to avoid overflow when multiplying. 225 */ 226 const ulong input_rate_khz = input_rate / 1000; 227 const ulong rate_khz = requested_rate / 1000; 228 const struct ast2500_div_config max_vals = *cfg; 229 struct ast2500_div_config it = { 0, 0, 0 }; 230 ulong delta = rate_khz; 231 ulong new_rate_khz = 0; 232 233 /* 234 * Look for a well known frequency first. 235 */ 236 if (ast2500_get_clock_config_default(input_rate, requested_rate, cfg)) 237 return requested_rate; 238 239 for (; it.denum <= max_vals.denum; ++it.denum) { 240 for (it.post_div = 0; it.post_div <= max_vals.post_div; 241 ++it.post_div) { 242 it.num = (rate_khz * (it.post_div + 1) / input_rate_khz) 243 * (it.denum + 1); 244 if (it.num > max_vals.num) 245 continue; 246 247 new_rate_khz = (input_rate_khz 248 * ((it.num + 1) / (it.denum + 1))) 249 / (it.post_div + 1); 250 251 /* Keep the rate below requested one. */ 252 if (new_rate_khz > rate_khz) 253 continue; 254 255 if (new_rate_khz - rate_khz < delta) { 256 delta = new_rate_khz - rate_khz; 257 *cfg = it; 258 if (delta == 0) 259 return new_rate_khz * 1000; 260 } 261 } 262 } 263 264 return new_rate_khz * 1000; 265 } 266 267 static ulong ast2500_configure_ddr(struct ast2500_scu *scu, ulong rate) 268 { 269 ulong clkin = ast2500_get_clkin(scu); 270 u32 mpll_reg; 271 struct ast2500_div_config div_cfg = { 272 .num = (SCU_MPLL_NUM_MASK >> SCU_MPLL_NUM_SHIFT), 273 .denum = (SCU_MPLL_DENUM_MASK >> SCU_MPLL_DENUM_SHIFT), 274 .post_div = (SCU_MPLL_POST_MASK >> SCU_MPLL_POST_SHIFT), 275 }; 276 277 ast2500_calc_clock_config(clkin, rate, &div_cfg); 278 279 mpll_reg = readl(&scu->m_pll_param); 280 mpll_reg &= ~(SCU_MPLL_POST_MASK | SCU_MPLL_NUM_MASK 281 | SCU_MPLL_DENUM_MASK); 282 mpll_reg |= (div_cfg.post_div << SCU_MPLL_POST_SHIFT) 283 | (div_cfg.num << SCU_MPLL_NUM_SHIFT) 284 | (div_cfg.denum << SCU_MPLL_DENUM_SHIFT); 285 286 writel(mpll_reg, &scu->m_pll_param); 287 288 return ast2500_get_mpll_rate(clkin, mpll_reg); 289 } 290 291 static ulong ast2500_configure_mac(struct ast2500_scu *scu, int index) 292 { 293 ulong clkin = ast2500_get_clkin(scu); 294 ulong hpll_rate = ast2500_get_hpll_rate(clkin, 295 readl(&scu->h_pll_param)); 296 ulong required_rate; 297 u32 hwstrap; 298 u32 divisor; 299 u32 reset_bit; 300 u32 clkstop_bit; 301 302 /* 303 * According to data sheet, for 10/100 mode the MAC clock frequency 304 * should be at least 25MHz and for 1000 mode at least 100MHz 305 */ 306 hwstrap = readl(&scu->hwstrap); 307 if (hwstrap & (SCU_HWSTRAP_MAC1_RGMII | SCU_HWSTRAP_MAC2_RGMII)) 308 required_rate = 100 * 1000 * 1000; 309 else 310 required_rate = 25 * 1000 * 1000; 311 312 divisor = hpll_rate / required_rate; 313 314 if (divisor < 4) { 315 /* Clock can't run fast enough, but let's try anyway */ 316 debug("MAC clock too slow\n"); 317 divisor = 4; 318 } else if (divisor > 16) { 319 /* Can't slow down the clock enough, but let's try anyway */ 320 debug("MAC clock too fast\n"); 321 divisor = 16; 322 } 323 324 switch (index) { 325 case 1: 326 reset_bit = SCU_SYSRESET_MAC1; 327 clkstop_bit = SCU_CLKSTOP_MAC1; 328 break; 329 case 2: 330 reset_bit = SCU_SYSRESET_MAC2; 331 clkstop_bit = SCU_CLKSTOP_MAC2; 332 break; 333 default: 334 return -EINVAL; 335 } 336 337 clrsetbits_le32(&scu->clk_sel1, SCU_MACCLK_MASK, 338 ((divisor - 2) / 2) << SCU_MACCLK_SHIFT); 339 340 /* 341 * Disable MAC, start its clock and re-enable it. 342 * The procedure and the delays (100us & 10ms) are 343 * specified in the datasheet. 344 */ 345 setbits_le32(&scu->sysreset_ctrl1, reset_bit); 346 udelay(100); 347 clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit); 348 mdelay(10); 349 clrbits_le32(&scu->sysreset_ctrl1, reset_bit); 350 351 writel((RGMII2_TXCK_DUTY << SCU_CLKDUTY_RGMII2TXCK_SHIFT) 352 | (RGMII1_TXCK_DUTY << SCU_CLKDUTY_RGMII1TXCK_SHIFT), 353 &scu->clk_duty_sel); 354 355 return required_rate; 356 } 357 358 static ulong ast2500_configure_d2pll(struct ast2500_scu *scu, ulong rate) 359 { 360 /* 361 * The values and the meaning of the next three 362 * parameters are undocumented. Taken from Aspeed SDK. 363 * 364 * TODO(clg@kaod.org): the SIP and SIC values depend on the 365 * Numerator value 366 */ 367 const u32 d2_pll_ext_param = 0x2c; 368 const u32 d2_pll_sip = 0x11; 369 const u32 d2_pll_sic = 0x18; 370 u32 clk_delay_settings = 371 (RMII_RXCLK_IDLY << SCU_MICDS_MAC1RMII_RDLY_SHIFT) 372 | (RMII_RXCLK_IDLY << SCU_MICDS_MAC2RMII_RDLY_SHIFT) 373 | (RGMII_TXCLK_ODLY << SCU_MICDS_MAC1RGMII_TXDLY_SHIFT) 374 | (RGMII_TXCLK_ODLY << SCU_MICDS_MAC2RGMII_TXDLY_SHIFT); 375 struct ast2500_div_config div_cfg = { 376 .num = SCU_D2PLL_NUM_MASK >> SCU_D2PLL_NUM_SHIFT, 377 .denum = SCU_D2PLL_DENUM_MASK >> SCU_D2PLL_DENUM_SHIFT, 378 .post_div = SCU_D2PLL_POST_MASK >> SCU_D2PLL_POST_SHIFT, 379 }; 380 ulong clkin = ast2500_get_clkin(scu); 381 ulong new_rate; 382 383 writel((d2_pll_ext_param << SCU_D2PLL_EXT1_PARAM_SHIFT) 384 | SCU_D2PLL_EXT1_OFF 385 | SCU_D2PLL_EXT1_RESET, &scu->d2_pll_ext_param[0]); 386 387 /* 388 * Select USB2.0 port1 PHY clock as a clock source for GCRT. 389 * This would disconnect it from D2-PLL. 390 */ 391 clrsetbits_le32(&scu->misc_ctrl1, SCU_MISC_D2PLL_OFF, 392 SCU_MISC_GCRT_USB20CLK); 393 394 new_rate = ast2500_calc_clock_config(clkin, rate, &div_cfg); 395 writel((d2_pll_sip << SCU_D2PLL_SIP_SHIFT) 396 | (d2_pll_sic << SCU_D2PLL_SIC_SHIFT) 397 | (div_cfg.num << SCU_D2PLL_NUM_SHIFT) 398 | (div_cfg.denum << SCU_D2PLL_DENUM_SHIFT) 399 | (div_cfg.post_div << SCU_D2PLL_POST_SHIFT), 400 &scu->d2_pll_param); 401 402 clrbits_le32(&scu->d2_pll_ext_param[0], 403 SCU_D2PLL_EXT1_OFF | SCU_D2PLL_EXT1_RESET); 404 405 clrsetbits_le32(&scu->misc_ctrl2, 406 SCU_MISC2_RGMII_HPLL | SCU_MISC2_RMII_MPLL 407 | SCU_MISC2_RGMII_CLKDIV_MASK | 408 SCU_MISC2_RMII_CLKDIV_MASK, 409 (4 << SCU_MISC2_RMII_CLKDIV_SHIFT)); 410 411 writel(clk_delay_settings | SCU_MICDS_RGMIIPLL, &scu->mac_clk_delay); 412 writel(clk_delay_settings, &scu->mac_clk_delay_100M); 413 writel(clk_delay_settings, &scu->mac_clk_delay_10M); 414 415 return new_rate; 416 } 417 418 static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate) 419 { 420 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev); 421 422 ulong new_rate; 423 switch (clk->id) { 424 case PLL_MPLL: 425 case MCLK_DDR: 426 new_rate = ast2500_configure_ddr(priv->scu, rate); 427 break; 428 case PLL_D2PLL: 429 new_rate = ast2500_configure_d2pll(priv->scu, rate); 430 break; 431 default: 432 return -ENOENT; 433 } 434 435 return new_rate; 436 } 437 438 static int ast2500_clk_enable(struct clk *clk) 439 { 440 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev); 441 442 switch (clk->id) { 443 /* 444 * For MAC clocks the clock rate is 445 * configured based on whether RGMII or RMII mode has been selected 446 * through hardware strapping. 447 */ 448 case PCLK_MAC1: 449 ast2500_configure_mac(priv->scu, 1); 450 break; 451 case PCLK_MAC2: 452 ast2500_configure_mac(priv->scu, 2); 453 break; 454 case PLL_D2PLL: 455 ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE); 456 break; 457 default: 458 return -ENOENT; 459 } 460 461 return 0; 462 } 463 464 struct clk_ops ast2500_clk_ops = { 465 .get_rate = ast2500_clk_get_rate, 466 .set_rate = ast2500_clk_set_rate, 467 .enable = ast2500_clk_enable, 468 }; 469 470 static int ast2500_clk_probe(struct udevice *dev) 471 { 472 struct ast2500_clk_priv *priv = dev_get_priv(dev); 473 474 priv->scu = devfdt_get_addr_ptr(dev); 475 if (IS_ERR(priv->scu)) 476 return PTR_ERR(priv->scu); 477 478 return 0; 479 } 480 481 static int ast2500_clk_bind(struct udevice *dev) 482 { 483 int ret; 484 485 /* The reset driver does not have a device node, so bind it here */ 486 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); 487 if (ret) 488 debug("Warning: No reset driver: ret=%d\n", ret); 489 490 return 0; 491 } 492 493 static const struct udevice_id ast2500_clk_ids[] = { 494 { .compatible = "aspeed,ast2500-scu" }, 495 { } 496 }; 497 498 U_BOOT_DRIVER(aspeed_scu) = { 499 .name = "aspeed_scu", 500 .id = UCLASS_CLK, 501 .of_match = ast2500_clk_ids, 502 .priv_auto_alloc_size = sizeof(struct ast2500_clk_priv), 503 .ops = &ast2500_clk_ops, 504 .bind = ast2500_clk_bind, 505 .probe = ast2500_clk_probe, 506 }; 507