1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * (C) Copyright 2016 Google, Inc 4 * 5 * Copyright (C) ASPEED Technology Inc. 6 * 7 */ 8 9 #include <common.h> 10 #include <clk-uclass.h> 11 #include <dm.h> 12 #include <asm/io.h> 13 #include <asm/arch/scu_ast2500.h> 14 #include <dm/lists.h> 15 #include <dt-bindings/clock/ast2500-clock.h> 16 17 /* 18 * MAC Clock Delay settings, taken from Aspeed SDK 19 */ 20 #define RGMII_TXCLK_ODLY 8 21 #define RMII_RXCLK_IDLY 2 22 23 /* 24 * TGMII Clock Duty constants, taken from Aspeed SDK 25 */ 26 #define RGMII2_TXCK_DUTY 0x66 27 #define RGMII1_TXCK_DUTY 0x64 28 29 #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000) 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 /* 34 * Clock divider/multiplier configuration struct. 35 * For H-PLL and M-PLL the formula is 36 * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) 37 * M - Numerator 38 * N - Denumerator 39 * P - Post Divider 40 * They have the same layout in their control register. 41 * 42 * D-PLL and D2-PLL have extra divider (OD + 1), which is not 43 * yet needed and ignored by clock configurations. 44 */ 45 struct ast2500_div_config { 46 unsigned int num; 47 unsigned int denum; 48 unsigned int post_div; 49 }; 50 51 /* 52 * Get the rate of the M-PLL clock from input clock frequency and 53 * the value of the M-PLL Parameter Register. 54 */ 55 static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg) 56 { 57 const ulong num = (mpll_reg & SCU_MPLL_NUM_MASK) >> SCU_MPLL_NUM_SHIFT; 58 const ulong denum = (mpll_reg & SCU_MPLL_DENUM_MASK) 59 >> SCU_MPLL_DENUM_SHIFT; 60 const ulong post_div = (mpll_reg & SCU_MPLL_POST_MASK) 61 >> SCU_MPLL_POST_SHIFT; 62 63 return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1); 64 } 65 66 /* 67 * Get the rate of the H-PLL clock from input clock frequency and 68 * the value of the H-PLL Parameter Register. 69 */ 70 static ulong ast2500_get_hpll_rate(ulong clkin, u32 hpll_reg) 71 { 72 /* F = clkin * [(M+1) / (N+1)] / (P + 1) */ 73 const ulong num = (hpll_reg & SCU_HPLL_NUM_MASK) >> SCU_HPLL_NUM_SHIFT; 74 const ulong denum = (hpll_reg & SCU_HPLL_DENUM_MASK) 75 >> SCU_HPLL_DENUM_SHIFT; 76 const ulong post_div = (hpll_reg & SCU_HPLL_POST_MASK) 77 >> SCU_HPLL_POST_SHIFT; 78 79 return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1); 80 } 81 82 static ulong ast2500_get_clkin(struct ast2500_scu *scu) 83 { 84 return readl(&scu->hwstrap) & SCU_HWSTRAP_CLKIN_25MHZ 85 ? 25 * 1000 * 1000 : 24 * 1000 * 1000; 86 } 87 88 /** 89 * Get current rate or uart clock 90 * 91 * @scu SCU registers 92 * @uart_index UART index, 1-5 93 * 94 * @return current setting for uart clock rate 95 */ 96 static ulong ast2500_get_uart_clk_rate(struct ast2500_scu *scu, int uart_index) 97 { 98 /* 99 * ast2500 datasheet is very confusing when it comes to UART clocks, 100 * especially when CLKIN = 25 MHz. The settings are in 101 * different registers and it is unclear how they interact. 102 * 103 * This has only been tested with default settings and CLKIN = 24 MHz. 104 */ 105 ulong uart_clkin; 106 107 if (readl(&scu->misc_ctrl2) & 108 (1 << (uart_index - 1 + SCU_MISC2_UARTCLK_SHIFT))) 109 uart_clkin = 192 * 1000 * 1000; 110 else 111 uart_clkin = 24 * 1000 * 1000; 112 113 if (readl(&scu->misc_ctrl1) & SCU_MISC_UARTCLK_DIV13) 114 uart_clkin /= 13; 115 116 return uart_clkin; 117 } 118 119 static ulong ast2500_clk_get_rate(struct clk *clk) 120 { 121 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev); 122 ulong clkin = ast2500_get_clkin(priv->scu); 123 ulong rate; 124 125 switch (clk->id) { 126 //HPLL 127 case ASPEED_CLK_HPLL: 128 rate = ast2500_get_hpll_rate(clkin, readl(&priv->scu->h_pll_param)); 129 break; 130 //HCLK 131 case ASPEED_CLK_AHB: 132 { 133 ulong ahb_div = 1 + ((readl(&priv->scu->hwstrap) 134 & SCU_HWSTRAP_AXIAHB_DIV_MASK) 135 >> SCU_HWSTRAP_AXIAHB_DIV_SHIFT); 136 ulong axi_div = 2; 137 138 rate = ast2500_get_hpll_rate( 139 clkin, readl(&priv->scu->h_pll_param)); 140 rate = rate / axi_div / ahb_div; 141 } 142 break; 143 //mpll 144 case ASPEED_CLK_MPLL: 145 rate = ast2500_get_mpll_rate(clkin, 146 readl(&priv->scu->m_pll_param)); 147 break; 148 case BCLK_PCLK: 149 { 150 ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1) 151 & SCU_PCLK_DIV_MASK) 152 >> SCU_PCLK_DIV_SHIFT); 153 rate = ast2500_get_hpll_rate(clkin, 154 readl(&priv-> 155 scu->h_pll_param)); 156 rate = rate / apb_div; 157 } 158 break; 159 case PCLK_UART1: 160 rate = ast2500_get_uart_clk_rate(priv->scu, 1); 161 break; 162 case PCLK_UART2: 163 rate = ast2500_get_uart_clk_rate(priv->scu, 2); 164 break; 165 case PCLK_UART3: 166 rate = ast2500_get_uart_clk_rate(priv->scu, 3); 167 break; 168 case PCLK_UART4: 169 rate = ast2500_get_uart_clk_rate(priv->scu, 4); 170 break; 171 case PCLK_UART5: 172 rate = ast2500_get_uart_clk_rate(priv->scu, 5); 173 break; 174 default: 175 return -ENOENT; 176 } 177 178 return rate; 179 } 180 181 struct ast2500_clock_config { 182 ulong input_rate; 183 ulong rate; 184 struct ast2500_div_config cfg; 185 }; 186 187 static const struct ast2500_clock_config ast2500_clock_config_defaults[] = { 188 { 24000000, 250000000, { .num = 124, .denum = 1, .post_div = 5 } }, 189 }; 190 191 static bool ast2500_get_clock_config_default(ulong input_rate, 192 ulong requested_rate, 193 struct ast2500_div_config *cfg) 194 { 195 int i; 196 197 for (i = 0; i < ARRAY_SIZE(ast2500_clock_config_defaults); i++) { 198 const struct ast2500_clock_config *default_cfg = 199 &ast2500_clock_config_defaults[i]; 200 if (default_cfg->input_rate == input_rate && 201 default_cfg->rate == requested_rate) { 202 *cfg = default_cfg->cfg; 203 return true; 204 } 205 } 206 207 return false; 208 } 209 210 /* 211 * @input_rate - the rate of input clock in Hz 212 * @requested_rate - desired output rate in Hz 213 * @div - this is an IN/OUT parameter, at input all fields of the config 214 * need to be set to their maximum allowed values. 215 * The result (the best config we could find), would also be returned 216 * in this structure. 217 * 218 * @return The clock rate, when the resulting div_config is used. 219 */ 220 static ulong ast2500_calc_clock_config(ulong input_rate, ulong requested_rate, 221 struct ast2500_div_config *cfg) 222 { 223 /* 224 * The assumption is that kHz precision is good enough and 225 * also enough to avoid overflow when multiplying. 226 */ 227 const ulong input_rate_khz = input_rate / 1000; 228 const ulong rate_khz = requested_rate / 1000; 229 const struct ast2500_div_config max_vals = *cfg; 230 struct ast2500_div_config it = { 0, 0, 0 }; 231 ulong delta = rate_khz; 232 ulong new_rate_khz = 0; 233 234 /* 235 * Look for a well known frequency first. 236 */ 237 if (ast2500_get_clock_config_default(input_rate, requested_rate, cfg)) 238 return requested_rate; 239 240 for (; it.denum <= max_vals.denum; ++it.denum) { 241 for (it.post_div = 0; it.post_div <= max_vals.post_div; 242 ++it.post_div) { 243 it.num = (rate_khz * (it.post_div + 1) / input_rate_khz) 244 * (it.denum + 1); 245 if (it.num > max_vals.num) 246 continue; 247 248 new_rate_khz = (input_rate_khz 249 * ((it.num + 1) / (it.denum + 1))) 250 / (it.post_div + 1); 251 252 /* Keep the rate below requested one. */ 253 if (new_rate_khz > rate_khz) 254 continue; 255 256 if (new_rate_khz - rate_khz < delta) { 257 delta = new_rate_khz - rate_khz; 258 *cfg = it; 259 if (delta == 0) 260 return new_rate_khz * 1000; 261 } 262 } 263 } 264 265 return new_rate_khz * 1000; 266 } 267 268 static ulong ast2500_configure_ddr(struct ast2500_scu *scu, ulong rate) 269 { 270 ulong clkin = ast2500_get_clkin(scu); 271 u32 mpll_reg; 272 struct ast2500_div_config div_cfg = { 273 .num = (SCU_MPLL_NUM_MASK >> SCU_MPLL_NUM_SHIFT), 274 .denum = (SCU_MPLL_DENUM_MASK >> SCU_MPLL_DENUM_SHIFT), 275 .post_div = (SCU_MPLL_POST_MASK >> SCU_MPLL_POST_SHIFT), 276 }; 277 278 ast2500_calc_clock_config(clkin, rate, &div_cfg); 279 280 mpll_reg = readl(&scu->m_pll_param); 281 mpll_reg &= ~(SCU_MPLL_POST_MASK | SCU_MPLL_NUM_MASK 282 | SCU_MPLL_DENUM_MASK); 283 mpll_reg |= (div_cfg.post_div << SCU_MPLL_POST_SHIFT) 284 | (div_cfg.num << SCU_MPLL_NUM_SHIFT) 285 | (div_cfg.denum << SCU_MPLL_DENUM_SHIFT); 286 287 writel(mpll_reg, &scu->m_pll_param); 288 289 return ast2500_get_mpll_rate(clkin, mpll_reg); 290 } 291 292 static ulong ast2500_configure_mac(struct ast2500_scu *scu, int index) 293 { 294 ulong clkin = ast2500_get_clkin(scu); 295 ulong hpll_rate = ast2500_get_hpll_rate(clkin, 296 readl(&scu->h_pll_param)); 297 ulong required_rate; 298 u32 hwstrap; 299 u32 divisor; 300 u32 reset_bit; 301 u32 clkstop_bit; 302 303 /* 304 * According to data sheet, for 10/100 mode the MAC clock frequency 305 * should be at least 25MHz and for 1000 mode at least 100MHz 306 */ 307 hwstrap = readl(&scu->hwstrap); 308 if (hwstrap & (SCU_HWSTRAP_MAC1_RGMII | SCU_HWSTRAP_MAC2_RGMII)) 309 required_rate = 100 * 1000 * 1000; 310 else 311 required_rate = 25 * 1000 * 1000; 312 313 divisor = hpll_rate / required_rate; 314 315 if (divisor < 4) { 316 /* Clock can't run fast enough, but let's try anyway */ 317 debug("MAC clock too slow\n"); 318 divisor = 4; 319 } else if (divisor > 16) { 320 /* Can't slow down the clock enough, but let's try anyway */ 321 debug("MAC clock too fast\n"); 322 divisor = 16; 323 } 324 325 switch (index) { 326 case 1: 327 reset_bit = SCU_SYSRESET_MAC1; 328 clkstop_bit = SCU_CLKSTOP_MAC1; 329 break; 330 case 2: 331 reset_bit = SCU_SYSRESET_MAC2; 332 clkstop_bit = SCU_CLKSTOP_MAC2; 333 break; 334 default: 335 return -EINVAL; 336 } 337 338 clrsetbits_le32(&scu->clk_sel1, SCU_MACCLK_MASK, 339 ((divisor - 2) / 2) << SCU_MACCLK_SHIFT); 340 341 /* 342 * Disable MAC, start its clock and re-enable it. 343 * The procedure and the delays (100us & 10ms) are 344 * specified in the datasheet. 345 */ 346 setbits_le32(&scu->sysreset_ctrl1, reset_bit); 347 udelay(100); 348 clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit); 349 mdelay(10); 350 clrbits_le32(&scu->sysreset_ctrl1, reset_bit); 351 352 writel((RGMII2_TXCK_DUTY << SCU_CLKDUTY_RGMII2TXCK_SHIFT) 353 | (RGMII1_TXCK_DUTY << SCU_CLKDUTY_RGMII1TXCK_SHIFT), 354 &scu->clk_duty_sel); 355 356 return required_rate; 357 } 358 359 static ulong ast2500_configure_d2pll(struct ast2500_scu *scu, ulong rate) 360 { 361 /* 362 * The values and the meaning of the next three 363 * parameters are undocumented. Taken from Aspeed SDK. 364 * 365 * TODO(clg@kaod.org): the SIP and SIC values depend on the 366 * Numerator value 367 */ 368 const u32 d2_pll_ext_param = 0x2c; 369 const u32 d2_pll_sip = 0x11; 370 const u32 d2_pll_sic = 0x18; 371 u32 clk_delay_settings = 372 (RMII_RXCLK_IDLY << SCU_MICDS_MAC1RMII_RDLY_SHIFT) 373 | (RMII_RXCLK_IDLY << SCU_MICDS_MAC2RMII_RDLY_SHIFT) 374 | (RGMII_TXCLK_ODLY << SCU_MICDS_MAC1RGMII_TXDLY_SHIFT) 375 | (RGMII_TXCLK_ODLY << SCU_MICDS_MAC2RGMII_TXDLY_SHIFT); 376 struct ast2500_div_config div_cfg = { 377 .num = SCU_D2PLL_NUM_MASK >> SCU_D2PLL_NUM_SHIFT, 378 .denum = SCU_D2PLL_DENUM_MASK >> SCU_D2PLL_DENUM_SHIFT, 379 .post_div = SCU_D2PLL_POST_MASK >> SCU_D2PLL_POST_SHIFT, 380 }; 381 ulong clkin = ast2500_get_clkin(scu); 382 ulong new_rate; 383 384 writel((d2_pll_ext_param << SCU_D2PLL_EXT1_PARAM_SHIFT) 385 | SCU_D2PLL_EXT1_OFF 386 | SCU_D2PLL_EXT1_RESET, &scu->d2_pll_ext_param[0]); 387 388 /* 389 * Select USB2.0 port1 PHY clock as a clock source for GCRT. 390 * This would disconnect it from D2-PLL. 391 */ 392 clrsetbits_le32(&scu->misc_ctrl1, SCU_MISC_D2PLL_OFF, 393 SCU_MISC_GCRT_USB20CLK); 394 395 new_rate = ast2500_calc_clock_config(clkin, rate, &div_cfg); 396 writel((d2_pll_sip << SCU_D2PLL_SIP_SHIFT) 397 | (d2_pll_sic << SCU_D2PLL_SIC_SHIFT) 398 | (div_cfg.num << SCU_D2PLL_NUM_SHIFT) 399 | (div_cfg.denum << SCU_D2PLL_DENUM_SHIFT) 400 | (div_cfg.post_div << SCU_D2PLL_POST_SHIFT), 401 &scu->d2_pll_param); 402 403 clrbits_le32(&scu->d2_pll_ext_param[0], 404 SCU_D2PLL_EXT1_OFF | SCU_D2PLL_EXT1_RESET); 405 406 clrsetbits_le32(&scu->misc_ctrl2, 407 SCU_MISC2_RGMII_HPLL | SCU_MISC2_RMII_MPLL 408 | SCU_MISC2_RGMII_CLKDIV_MASK | 409 SCU_MISC2_RMII_CLKDIV_MASK, 410 (4 << SCU_MISC2_RMII_CLKDIV_SHIFT)); 411 412 writel(clk_delay_settings | SCU_MICDS_RGMIIPLL, &scu->mac_clk_delay); 413 writel(clk_delay_settings, &scu->mac_clk_delay_100M); 414 writel(clk_delay_settings, &scu->mac_clk_delay_10M); 415 416 return new_rate; 417 } 418 419 static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate) 420 { 421 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev); 422 423 ulong new_rate; 424 switch (clk->id) { 425 //mpll 426 case ASPEED_CLK_MPLL: 427 new_rate = ast2500_configure_ddr(priv->scu, rate); 428 break; 429 case PLL_D2PLL: 430 new_rate = ast2500_configure_d2pll(priv->scu, rate); 431 break; 432 default: 433 return -ENOENT; 434 } 435 436 return new_rate; 437 } 438 439 static int ast2500_clk_enable(struct clk *clk) 440 { 441 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev); 442 443 switch (clk->id) { 444 /* 445 * For MAC clocks the clock rate is 446 * configured based on whether RGMII or RMII mode has been selected 447 * through hardware strapping. 448 */ 449 case PCLK_MAC1: 450 ast2500_configure_mac(priv->scu, 1); 451 break; 452 case PCLK_MAC2: 453 ast2500_configure_mac(priv->scu, 2); 454 break; 455 case PLL_D2PLL: 456 ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE); 457 break; 458 default: 459 return -ENOENT; 460 } 461 462 return 0; 463 } 464 465 struct clk_ops ast2500_clk_ops = { 466 .get_rate = ast2500_clk_get_rate, 467 .set_rate = ast2500_clk_set_rate, 468 .enable = ast2500_clk_enable, 469 }; 470 471 static int ast2500_clk_probe(struct udevice *dev) 472 { 473 struct ast2500_clk_priv *priv = dev_get_priv(dev); 474 475 priv->scu = devfdt_get_addr_ptr(dev); 476 if (IS_ERR(priv->scu)) 477 return PTR_ERR(priv->scu); 478 479 return 0; 480 } 481 482 static int ast2500_clk_bind(struct udevice *dev) 483 { 484 int ret; 485 486 /* The reset driver does not have a device node, so bind it here */ 487 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); 488 if (ret) 489 debug("Warning: No reset driver: ret=%d\n", ret); 490 491 return 0; 492 } 493 494 static const struct udevice_id ast2500_clk_ids[] = { 495 { .compatible = "aspeed,ast2500-scu" }, 496 { } 497 }; 498 499 U_BOOT_DRIVER(aspeed_scu) = { 500 .name = "aspeed_scu", 501 .id = UCLASS_CLK, 502 .of_match = ast2500_clk_ids, 503 .priv_auto_alloc_size = sizeof(struct ast2500_clk_priv), 504 .ops = &ast2500_clk_ops, 505 .bind = ast2500_clk_bind, 506 .probe = ast2500_clk_probe, 507 }; 508