1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2012-2020 ASPEED Technology Inc. 4 * 5 * Copyright 2016 Google, Inc 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <errno.h> 12 #include <ram.h> 13 #include <regmap.h> 14 #include <reset.h> 15 #include <asm/io.h> 16 #include <asm/arch/scu_ast2600.h> 17 #include <asm/arch/sdram_ast2600.h> 18 #include <asm/arch/wdt.h> 19 #include <linux/err.h> 20 #include <linux/kernel.h> 21 #include <dt-bindings/clock/ast2600-clock.h> 22 #include "sdram_phy_ast2600.h" 23 24 #define AST2600_SDRAMMC_FPGA 25 26 #ifdef AST2600_SDRAMMC_FPGA 27 /* mode register settings for FPGA are fixed */ 28 #define DDR4_MR01_MODE 0x03010100 29 #define DDR4_MR23_MODE 0x00000000 30 #define DDR4_MR45_MODE 0x04C00000 31 #define DDR4_MR6_MODE 0x00000050 32 #define DDR4_TRFC 0x17263434 33 34 /* FPGA need for an additional initialization procedure: search read window */ 35 #define SEARCH_RDWIN_ANCHOR_0 (CONFIG_SYS_SDRAM_BASE + 0x0000) 36 #define SEARCH_RDWIN_ANCHOR_1 (CONFIG_SYS_SDRAM_BASE + 0x0004) 37 #define SEARCH_RDWIN_PTRN_0 0x12345678 38 #define SEARCH_RDWIN_PTRN_1 0xaabbccdd 39 #define SEARCH_RDWIN_PTRN_SUM 0xbcf02355 40 #else 41 /* mode register setting for real chip are derived from the model GDDR4-1600 */ 42 #define DDR4_MR01_MODE 0x03010510 43 #define DDR4_MR23_MODE 0x00000000 44 #define DDR4_MR45_MODE 0x04000000 45 #define DDR4_MR6_MODE 0x00000400 46 #define DDR4_TRFC 0x467299f1 47 #endif /* end of "#ifdef AST2600_SDRAMMC_FPGA" */ 48 49 #define SDRAM_SIZE_1KB (1024U) 50 #define SDRAM_SIZE_1MB (SDRAM_SIZE_1KB * SDRAM_SIZE_1KB) 51 #define SDRAM_MIN_SIZE (256 * SDRAM_SIZE_1MB) 52 #define SDRAM_MAX_SIZE (2048 * SDRAM_SIZE_1MB) 53 54 /* register offset */ 55 #define AST_SCU_CONFIG 0x004 56 #define AST_SCU_HANDSHAKE 0x100 57 #define AST_SCU_FPGA_PLL 0x400 58 #define AST_SCU_HW_STRAP 0x500 59 60 /* bit-field of AST_SCU_HW_STRAP */ 61 #define SCU_HWSTRAP_VGAMEM_SHIFT 2 62 #define SCU_HWSTRAP_VGAMEM_MASK (3 << SCU_HWSTRAP_VGAMEM_SHIFT) 63 #define SCU_HWSTRAP_DDR3 (1 << 25) 64 65 66 /* bit-field of AST_SCU_HANDSHAKE */ 67 #define SCU_SDRAM_INIT_READY_SHIFT 6 68 #define SCU_SDRAM_INIT_READY_MASK (0x1 << SCU_SDRAM_INIT_READY_SHIFT) 69 #define SCU_SDRAM_INIT_BY_SOC_SHIFT 7 70 #define SCU_SDRAM_INIT_BY_SOC_MASK (0x1 << SCU_SDRAM_INIT_BY_SOC_SHIFT) 71 72 DECLARE_GLOBAL_DATA_PTR; 73 74 /* 75 * Bandwidth configuration parameters for different SDRAM requests. 76 * These are hardcoded settings taken from Aspeed SDK. 77 */ 78 #ifdef AST2600_SDRAMMC_FPGA 79 static const u32 ddr4_ac_timing[4] = {0x030C0207, 0x04451133, 0x0E010200, 80 0x00000140}; 81 82 static const u32 ddr_max_grant_params[4] = {0x88888888, 0x88888888, 0x88888888, 83 0x88888888}; 84 #else 85 static const u32 ddr4_ac_timing[4] = {0x040e0307, 0x0f4711f1, 0x0e060304, 86 0x00001240}; 87 88 static const u32 ddr_max_grant_params[4] = {0x44444444, 0x44444444, 0x44444444, 89 0x44444444}; 90 #endif 91 92 struct dram_info { 93 struct ram_info info; 94 struct clk ddr_clk; 95 struct ast2600_sdrammc_regs *regs; 96 void __iomem *scu; 97 struct ast2600_ddr_phy *phy; 98 void __iomem *phy_setting; 99 void __iomem *phy_status; 100 ulong clock_rate; 101 }; 102 103 static void ast2600_sdramphy_kick_training(struct dram_info *info) 104 { 105 #ifndef AST2600_SDRAMMC_FPGA 106 struct ast2600_sdrammc_regs *regs = info->regs; 107 u32 mask = SDRAM_PHYCTRL0_INIT | SDRAM_PHYCTRL0_PLL_LOCKED; 108 u32 data; 109 110 writel(0, ®s->phy_ctrl[0]); 111 udelay(2); 112 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]); 113 114 /* wait for (PLL_LOCKED == 1) and (INIT == 0) */ 115 do { 116 data = readl(®s->phy_ctrl[0]) & mask; 117 } while (SDRAM_PHYCTRL0_PLL_LOCKED != data); 118 #endif 119 } 120 121 /** 122 * @brief load DDR-PHY configurations table to the PHY registers 123 * @param[in] p_tbl - pointer to the configuration table 124 * @param[in] info - pointer to the DRAM info struct 125 */ 126 static void ast2600_sdramphy_init(u32 *p_tbl, struct dram_info *info) 127 { 128 #ifndef AST2600_SDRAMMC_FPGA 129 u32 reg_base = (u32)info->phy_setting; 130 u32 addr = p_tbl[0]; 131 u32 data; 132 int i = 1; 133 134 debug("%s:reg base = 0x%08x, 1st addr = 0x%08x\n", __func__, reg_base, 135 addr); 136 137 /* load PHY configuration table into PHY-setting registers */ 138 while (1) { 139 if (addr < reg_base) { 140 debug("invalid DDR-PHY addr: 0x%08x\n", addr); 141 break; 142 } 143 data = p_tbl[i++]; 144 145 if (DDR_PHY_TBL_END == data) { 146 break; 147 } else if (DDR_PHY_TBL_CHG_ADDR == data) { 148 addr = p_tbl[i++]; 149 } else { 150 writel(data, addr); 151 addr += 4; 152 } 153 } 154 #endif 155 } 156 157 static void ast2600_sdramphy_show_status(struct dram_info *info) 158 { 159 #ifndef AST2600_SDRAMMC_FPGA 160 u32 value; 161 u32 reg_base = (u32)info->phy_status; 162 163 debug("%s:reg base = 0x%08x\n", __func__, reg_base); 164 165 value = readl(reg_base + 0x00); 166 if (value & BIT(3)) { 167 debug("initial PVT calibration fail\n"); 168 } 169 if (value & BIT(5)) { 170 debug("runtime calibration fail\n"); 171 } 172 173 value = readl(reg_base + 0x30); 174 debug("IO PU = 0x%02x\n", value & 0xff); 175 debug("IO PD = 0x%02x\n", (value >> 16) & 0xff); 176 177 value = readl(reg_base + 0x88); 178 debug("PHY vref: 0x%02x_%02x\n", value & 0xff, (value >> 8) & 0xff); 179 value = readl(reg_base + 0x90); 180 debug("DDR vref: 0x%02x\n", value & 0x3f); 181 182 value = readl(reg_base + 0x40); 183 debug("MLB Gate training result: 0x%04x_%04x\n", value & 0xffff, 184 (value >> 16) & 0xffff); 185 value = readl(reg_base + 0x50); 186 debug("MLB Gate pass window: 0x%04x_%04x\n", value & 0xffff, 187 (value >> 16) & 0xffff); 188 value = readl(reg_base + 0x60); 189 debug("Rising edge Read Data Eye Training Result = 0x%x_%x\n", 190 value & 0xff, (value >> 8) & 0xff); 191 192 value = readl(reg_base + 0x68); 193 debug("Rising edge Read Data Eye Training Pass Window = 0x%x_%x\n", 194 value & 0xff, (value >> 8) & 0xff); 195 196 value = readl(reg_base + 0xC0); 197 debug("Falling edge Read Data Eye Training Result = 0x%x_%x\n", 198 value & 0xff, (value >> 8) & 0xff); 199 200 value = readl(reg_base + 0xC8); 201 debug("Falling edge Read Data Eye Training Pass Window = 0x%x_%x\n", 202 value & 0xff, (value >> 8) & 0xff); 203 204 value = readl(reg_base + 0x74); 205 debug("Write Data Eye fine Training Result = %X_%X\n", 206 value & 0xff, (value >> 8) & 0xff); 207 208 value = readl(reg_base + 0x7C); 209 debug("Write Data Eye Training Pass Window = 0x%x_%x\n", 210 value & 0xff, (value >> 8) & 0xff); 211 #endif 212 } 213 214 /** 215 * @brief SDRAM memory controller test mode with data-generation 216 * @param[in] - info - pointer to the current dram_info 217 * @param[in] - data_gen - data_gen index 218 * @param[in] - mode - 0:single, 1:burst 219 * @return - 0:success, others:fail 220 */ 221 static int ast2600_sdrammc_dg_test(struct dram_info *info, u32 data_gen, 222 u32 mode) 223 { 224 u32 data; 225 u32 mask; 226 struct ast2600_sdrammc_regs *regs = info->regs; 227 228 writel(0, ®s->ecc_test_ctrl); 229 data = (data_gen << SDRAM_TEST_GEN_MODE_SHIFT) | SDRAM_TEST_ERRSTOP | 230 SDRAM_TEST_EN; 231 if (mode) { 232 data |= 233 (SDRAM_TEST_ERRSTOP | SDRAM_TEST_EN | SDRAM_TEST_MODE_RW); 234 } else { 235 data |= (SDRAM_TEST_ERRSTOP | SDRAM_TEST_EN | 236 SDRAM_TEST_MODE_WO | SDRAM_TEST_TWO_MODES); 237 } 238 writel(data, ®s->ecc_test_ctrl); 239 240 mask = SDRAM_TEST_DONE | SDRAM_TEST_FAIL; 241 do { 242 data = readl(®s->ecc_test_ctrl) & mask; 243 if (data & SDRAM_TEST_FAIL) { 244 debug("%s %d fail\n", __func__, data_gen); 245 return 1; 246 } 247 } while (!data); 248 249 writel(0x00000000, ®s->ecc_test_ctrl); 250 return 0; 251 } 252 253 static int ast2600_sdrammc_cbr_test(struct dram_info *info, u32 pattern) 254 { 255 struct ast2600_sdrammc_regs *regs = info->regs; 256 int i; 257 int ret = 0; 258 259 writel((0xff << SDRAM_TEST_LEN_SHIFT), ®s->test_addr); 260 writel(pattern, ®s->test_init_val); 261 262 /* scan all data-generation mode */ 263 for (i = 0; i < 8; i++) { 264 if (0 == ast2600_sdrammc_dg_test(info, i, 0)) { 265 debug("sdrammc calibration test fail: single data " 266 "mode\n"); 267 ret = 1; 268 break; 269 } 270 } 271 272 for (i = 0; i < 8; i++) { 273 if (0 == ast2600_sdrammc_dg_test(info, i, 1)) { 274 debug( 275 "sdrammc calibration test fail: burst data mode\n"); 276 ret = 1; 277 break; 278 } 279 } 280 281 writel(0, ®s->ecc_test_ctrl); 282 return ret; 283 } 284 285 #define MC_TEST_PATTERN_N 8 286 static u32 as2600_sdrammc_test_pattern[MC_TEST_PATTERN_N] = { 287 0xcc33cc33, 0xff00ff00, 0xaa55aa55, 0x88778877, 288 0x92cc4d6e, 0x543d3cde, 0xf1e843c7, 0x7c61d253}; 289 290 static int ast2600_sdrammc_test(struct dram_info *info) 291 { 292 int i; 293 int ret; 294 295 for (i = 0; i < MC_TEST_PATTERN_N; i++) { 296 ret = ast2600_sdrammc_cbr_test(info, 297 as2600_sdrammc_test_pattern[i]); 298 if (ret) { 299 return ret; 300 } 301 debug("%s: pass %d\n", __func__, i); 302 } 303 304 return ret; 305 } 306 307 static size_t ast2600_sdrammc_get_vga_mem_size(struct dram_info *info) 308 { 309 u32 vga_hwconf; 310 size_t vga_mem_size_base = 8 * 1024 * 1024; 311 312 vga_hwconf = readl(info->scu + AST_SCU_HW_STRAP) & 313 SCU_HWSTRAP_VGAMEM_MASK >> SCU_HWSTRAP_VGAMEM_SHIFT; 314 315 return vga_mem_size_base << vga_hwconf; 316 } 317 #ifdef AST2600_SDRAMMC_FPGA 318 static void ast2600_sdrammc_fpga_set_pll(struct dram_info *info) 319 { 320 u32 data; 321 u32 scu_base = (u32)info->scu; 322 323 writel(0x00000303, scu_base + AST_SCU_FPGA_PLL); 324 325 do { 326 data = readl(scu_base + AST_SCU_CONFIG); 327 } while (!(data & 0x100)); 328 329 writel(0x00000103, scu_base + AST_SCU_FPGA_PLL); 330 } 331 332 static int ast2600_sdrammc_search_read_window(struct dram_info *info) 333 { 334 u32 pll, pll_min, pll_max, dat1, offset; 335 u32 win = 0x03, gwin = 0, gwinsize = 0; 336 u32 phy_setting = (u32)info->phy_setting; 337 338 writel(SEARCH_RDWIN_PTRN_0, SEARCH_RDWIN_ANCHOR_0); 339 writel(SEARCH_RDWIN_PTRN_1, SEARCH_RDWIN_ANCHOR_1); 340 341 while (gwin == 0) { 342 while (!(win & 0x80)) { 343 debug("Window = 0x%X\n", win); 344 writel(win, phy_setting + 0x0000); 345 346 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 347 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 348 while (dat1 == SEARCH_RDWIN_PTRN_SUM) { 349 ast2600_sdrammc_fpga_set_pll(info); 350 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 351 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 352 } 353 354 pll_min = 0xfff; 355 pll_max = 0x0; 356 pll = 0; 357 while (pll_max > 0 || pll < 256) { 358 ast2600_sdrammc_fpga_set_pll(info); 359 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 360 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 361 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 362 if (pll_min > pll) { 363 pll_min = pll; 364 } 365 if (pll_max < pll) { 366 pll_max = pll; 367 } 368 debug("%3d_(%3d:%3d)\n", pll, pll_min, 369 pll_max); 370 } else if (pll_max > 0) { 371 pll_min = pll_max - pll_min; 372 if (gwinsize < pll_min) { 373 gwin = win; 374 gwinsize = pll_min; 375 } 376 break; 377 } 378 pll += 1; 379 } 380 381 if (gwin != 0 && pll_max == 0) { 382 break; 383 } 384 win = win << 1; 385 } 386 if (gwin == 0) { 387 win = 0x7; 388 } 389 } 390 debug("Set PLL Read Gating Window = %x\n", gwin); 391 writel(gwin, phy_setting + 0x0000); 392 393 debug("PLL Read Window training\n"); 394 pll_min = 0xfff; 395 pll_max = 0x0; 396 397 debug("Search Window Start\n"); 398 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 399 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 400 while (dat1 == SEARCH_RDWIN_PTRN_SUM) { 401 ast2600_sdrammc_fpga_set_pll(info); 402 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 403 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 404 } 405 406 debug("Search Window Margin\n"); 407 pll = 0; 408 while (pll_max > 0 || pll < 256) { 409 ast2600_sdrammc_fpga_set_pll(info); 410 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 411 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 412 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 413 if (pll_min > pll) { 414 pll_min = pll; 415 } 416 if (pll_max < pll) { 417 pll_max = pll; 418 } 419 debug("%3d_(%3d:%3d)\n", pll, pll_min, pll_max); 420 } else if (pll_max > 0 && (pll_max - pll_min) > 20) { 421 break; 422 } else if (pll_max > 0) { 423 pll_min = 0xfff; 424 pll_max = 0x0; 425 } 426 pll += 1; 427 } 428 if (pll_min < pll_max) { 429 debug("PLL Read window = %d\n", (pll_max - pll_min)); 430 offset = (pll_max - pll_min) >> 1; 431 pll_min = 0xfff; 432 pll = 0; 433 while (pll < (pll_min + offset)) { 434 ast2600_sdrammc_fpga_set_pll(info); 435 dat1 = readl(SEARCH_RDWIN_ANCHOR_0); 436 dat1 += readl(SEARCH_RDWIN_ANCHOR_1); 437 if (dat1 == SEARCH_RDWIN_PTRN_SUM) { 438 if (pll_min > pll) { 439 pll_min = pll; 440 } 441 debug("%d\n", pll); 442 } else { 443 pll_min = 0xfff; 444 pll_max = 0x0; 445 } 446 pll += 1; 447 } 448 return (1); 449 } else { 450 debug("PLL Read window training fail\n"); 451 return (0); 452 } 453 } 454 #endif /* end of "#ifdef AST2600_SDRAMMC_FPGA" */ 455 456 /* 457 * Find out RAM size and save it in dram_info 458 * 459 * The procedure is taken from Aspeed SDK 460 */ 461 static void ast2600_sdrammc_calc_size(struct dram_info *info) 462 { 463 /* The controller supports 256/512/1024/2048 MB ram */ 464 size_t ram_size = SDRAM_MIN_SIZE; 465 const int write_test_offset = 0x100000; 466 u32 test_pattern = 0xdeadbeef; 467 u32 cap_param = SDRAM_CONF_CAP_2048M; 468 u32 refresh_timing_param = DDR4_TRFC; 469 const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset; 470 471 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 472 ram_size >>= 1) { 473 writel(test_pattern, write_addr_base + (ram_size >> 1)); 474 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 475 } 476 477 /* One last write to overwrite all wrapped values */ 478 writel(test_pattern, write_addr_base); 479 480 /* Reset the pattern and see which value was really written */ 481 test_pattern = 0xdeadbeef; 482 for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; 483 ram_size >>= 1) { 484 if (readl(write_addr_base + (ram_size >> 1)) == test_pattern) 485 break; 486 487 --cap_param; 488 refresh_timing_param >>= 8; 489 test_pattern = (test_pattern >> 4) | (test_pattern << 28); 490 } 491 492 clrsetbits_le32(&info->regs->ac_timing[1], 493 (SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT), 494 ((refresh_timing_param & SDRAM_AC_TRFC_MASK) 495 << SDRAM_AC_TRFC_SHIFT)); 496 497 info->info.base = CONFIG_SYS_SDRAM_BASE; 498 info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info); 499 clrsetbits_le32(&info->regs->config, 500 (SDRAM_CONF_CAP_MASK << SDRAM_CONF_CAP_SHIFT), 501 ((cap_param & SDRAM_CONF_CAP_MASK) 502 << SDRAM_CONF_CAP_SHIFT)); 503 } 504 505 static int ast2600_sdrammc_init_ddr4(struct dram_info *info) 506 { 507 const u32 power_ctrl = MCR34_CKE_EN | MCR34_AUTOPWRDN_EN | 508 MCR34_MREQ_BYPASS_DIS | MCR34_RESETN_DIS | 509 MCR34_ODT_EN | MCR34_ODT_AUTO_ON | 510 (0x1 << MCR34_ODT_EXT_SHIFT); 511 512 #ifdef CONFIG_DUALX8_RAM 513 setbits_le32(&info->regs->config, SDRAM_CONF_DDR4 | SDRAM_CONF_DUALX8); 514 #else 515 setbits_le32(&info->regs->config, SDRAM_CONF_DDR4); 516 #endif 517 518 /* init SDRAM-PHY only on real chip */ 519 ast2600_sdramphy_init(ast2600_sdramphy_config, info); 520 ast2600_sdramphy_kick_training(info); 521 522 writel((MCR34_CKE_EN | MCR34_MREQI_DIS | MCR34_RESETN_DIS), 523 &info->regs->power_ctrl); 524 writel(SDRAM_RESET_DLL_ZQCL_EN, &info->regs->refresh_timing); 525 526 writel(MCR30_SET_MR(3), &info->regs->mode_setting_control); 527 writel(MCR30_SET_MR(6), &info->regs->mode_setting_control); 528 writel(MCR30_SET_MR(5), &info->regs->mode_setting_control); 529 writel(MCR30_SET_MR(4), &info->regs->mode_setting_control); 530 writel(MCR30_SET_MR(2), &info->regs->mode_setting_control); 531 writel(MCR30_SET_MR(1), &info->regs->mode_setting_control); 532 writel(MCR30_SET_MR(0) | MCR30_RESET_DLL_DELAY_EN, 533 &info->regs->mode_setting_control); 534 535 #ifdef AST2600_SDRAMMC_FPGA 536 writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN | 537 (0x5d << SDRAM_REFRESH_PERIOD_SHIFT), 538 &info->regs->refresh_timing); 539 #else 540 writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN | 541 (0x5f << SDRAM_REFRESH_PERIOD_SHIFT), 542 &info->regs->refresh_timing); 543 #endif 544 545 /* wait self-refresh idle */ 546 while (readl(&info->regs->power_ctrl) & MCR34_SELF_REFRESH_STATUS_MASK) 547 ; 548 549 #ifdef AST2600_SDRAMMC_FPGA 550 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | 551 SDRAM_REFRESH_ZQCS_EN | 552 (0x5d << SDRAM_REFRESH_PERIOD_SHIFT) | 553 (0x4000 << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), 554 &info->regs->refresh_timing); 555 #else 556 writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | 557 SDRAM_REFRESH_ZQCS_EN | 558 (0x5f << SDRAM_REFRESH_PERIOD_SHIFT) | 559 (0x42aa << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), 560 &info->regs->refresh_timing); 561 #endif 562 563 writel(power_ctrl, &info->regs->power_ctrl); 564 565 #ifdef AST2600_SDRAMMC_FPGA 566 /* toggle Vref training */ 567 setbits_le32(&info->regs->mr6_mode_setting, 0x80); 568 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), 569 &info->regs->mode_setting_control); 570 clrbits_le32(&info->regs->mr6_mode_setting, 0x80); 571 writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6), 572 &info->regs->mode_setting_control); 573 #endif 574 return 0; 575 } 576 577 static void ast2600_sdrammc_unlock(struct dram_info *info) 578 { 579 writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key); 580 while (!readl(&info->regs->protection_key)) 581 ; 582 } 583 584 static void ast2600_sdrammc_lock(struct dram_info *info) 585 { 586 writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key); 587 while (readl(&info->regs->protection_key)) 588 ; 589 } 590 591 static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs) 592 { 593 int i; 594 595 writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key); 596 writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, ®s->power_ctrl); 597 writel(0x10 << MCR38_RW_MAX_GRANT_CNT_RQ_SHIFT, 598 ®s->arbitration_ctrl); 599 writel(0xFFFFFFFF, ®s->req_limit_mask); 600 601 for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i) 602 writel(ddr_max_grant_params[i], ®s->max_grant_len[i]); 603 604 writel(MCR50_RESET_ALL_INTR, ®s->intr_ctrl); 605 606 /* FIXME: the sample code does NOT match the datasheet */ 607 writel(0x7FFFFFF, ®s->ecc_range_ctrl); 608 609 writel(0, ®s->ecc_test_ctrl); 610 writel(0, ®s->test_addr); 611 writel(0, ®s->test_fail_dq_bit); 612 writel(0, ®s->test_init_val); 613 614 writel(0xFFFFFFFF, ®s->req_input_ctrl); 615 writel(0, ®s->req_high_pri_ctrl); 616 617 #ifdef AST2600_SDRAMMC_FPGA 618 //writel(0xFF, 0x1e6e0100); 619 #endif 620 udelay(500); 621 622 /* set capacity to the max size */ 623 clrsetbits_le32(®s->config, SDRAM_CONF_CAP_MASK, 624 SDRAM_CONF_CAP_2048M); 625 626 /* load controller setting */ 627 for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i) 628 writel(ddr4_ac_timing[i], ®s->ac_timing[i]); 629 630 writel(DDR4_MR01_MODE, ®s->mr01_mode_setting); 631 writel(DDR4_MR23_MODE, ®s->mr23_mode_setting); 632 writel(DDR4_MR45_MODE, ®s->mr45_mode_setting); 633 writel(DDR4_MR6_MODE, ®s->mr6_mode_setting); 634 } 635 636 static int ast2600_sdrammc_probe(struct udevice *dev) 637 { 638 struct reset_ctl reset_ctl; 639 struct dram_info *priv = (struct dram_info *)dev_get_priv(dev); 640 struct ast2600_sdrammc_regs *regs = priv->regs; 641 struct udevice *clk_dev; 642 int ret = clk_get_by_index(dev, 0, &priv->ddr_clk); 643 644 if (ret) { 645 debug("DDR:No CLK\n"); 646 return ret; 647 } 648 649 /* find SCU base address from clock device */ 650 ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), 651 &clk_dev); 652 if (ret) { 653 debug("clock device not defined\n"); 654 return ret; 655 } 656 657 priv->scu = devfdt_get_addr_ptr(clk_dev); 658 if (IS_ERR(priv->scu)) { 659 debug("%s(): can't get SCU\n", __func__); 660 return PTR_ERR(priv->scu); 661 } 662 663 if (readl(priv->scu + AST_SCU_HANDSHAKE) & SCU_SDRAM_INIT_READY_MASK) { 664 debug("%s(): DDR SDRAM had been initialized\n", __func__); 665 ast2600_sdrammc_calc_size(priv); 666 return 0; 667 } 668 669 clk_set_rate(&priv->ddr_clk, priv->clock_rate); 670 671 /* FIXME: enable the following code if reset-driver is ready */ 672 ret = reset_get_by_index(dev, 0, &reset_ctl); 673 if (ret) { 674 debug("%s(): Failed to get reset signal\n", __func__); 675 return ret; 676 } 677 #if 0 678 679 ret = reset_assert(&reset_ctl); 680 if (ret) { 681 debug("%s(): SDRAM reset failed: %u\n", __func__, ret); 682 return ret; 683 } 684 #endif 685 686 ast2600_sdrammc_unlock(priv); 687 ast2600_sdrammc_common_init(regs); 688 689 if (readl(priv->scu + AST_SCU_HW_STRAP) & SCU_HWSTRAP_DDR3) { 690 debug("Unsupported SDRAM type: DDR3\n"); 691 return -EINVAL; 692 } else { 693 ast2600_sdrammc_init_ddr4(priv); 694 } 695 696 #ifdef AST2600_SDRAMMC_FPGA 697 ast2600_sdrammc_search_read_window(priv); 698 #endif 699 700 ast2600_sdramphy_show_status(priv); 701 ast2600_sdrammc_calc_size(priv); 702 703 ast2600_sdrammc_test(priv); 704 705 clrbits_le32(®s->intr_ctrl, MCR50_RESET_ALL_INTR); 706 ast2600_sdrammc_lock(priv); 707 return 0; 708 } 709 710 static int ast2600_sdrammc_ofdata_to_platdata(struct udevice *dev) 711 { 712 struct dram_info *priv = dev_get_priv(dev); 713 struct regmap *map; 714 int ret; 715 716 ret = regmap_init_mem(dev_ofnode(dev), &map); 717 if (ret) 718 return ret; 719 720 priv->regs = regmap_get_range(map, 0); 721 priv->phy_setting = regmap_get_range(map, 1); 722 priv->phy_status = regmap_get_range(map, 2); 723 724 priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 725 "clock-frequency", 0); 726 727 if (!priv->clock_rate) { 728 debug("DDR Clock Rate not defined\n"); 729 return -EINVAL; 730 } 731 732 return 0; 733 } 734 735 static int ast2600_sdrammc_get_info(struct udevice *dev, struct ram_info *info) 736 { 737 struct dram_info *priv = dev_get_priv(dev); 738 739 *info = priv->info; 740 741 return 0; 742 } 743 744 static struct ram_ops ast2600_sdrammc_ops = { 745 .get_info = ast2600_sdrammc_get_info, 746 }; 747 748 static const struct udevice_id ast2600_sdrammc_ids[] = { 749 { .compatible = "aspeed,ast2600-sdrammc" }, 750 { } 751 }; 752 753 U_BOOT_DRIVER(sdrammc_ast2600) = { 754 .name = "aspeed_ast2600_sdrammc", 755 .id = UCLASS_RAM, 756 .of_match = ast2600_sdrammc_ids, 757 .ops = &ast2600_sdrammc_ops, 758 .ofdata_to_platdata = ast2600_sdrammc_ofdata_to_platdata, 759 .probe = ast2600_sdrammc_probe, 760 .priv_auto_alloc_size = sizeof(struct dram_info), 761 }; 762