1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3#include "skeleton.dtsi" 4 5/ { 6 model = "Aspeed BMC"; 7 compatible = "aspeed,ast2600"; 8 #address-cells = <1>; 9 #size-cells = <1>; 10 11 aliases { 12 i2c0 = &i2c0; 13 i2c1 = &i2c1; 14 i2c2 = &i2c2; 15 i2c3 = &i2c3; 16 i2c4 = &i2c4; 17 i2c5 = &i2c5; 18 i2c6 = &i2c6; 19 i2c7 = &i2c7; 20 i2c8 = &i2c8; 21 i2c9 = &i2c9; 22 i2c10 = &i2c10; 23 i2c11 = &i2c11; 24 i2c12 = &i2c12; 25 i2c13 = &i2c13; 26 i2c14 = &i2c14; 27 i2c15 = &i2c15; 28 serial0 = &uart1; 29 serial1 = &uart2; 30 serial2 = &uart3; 31 serial3 = &uart4; 32 serial4 = &uart5; 33 serial5 = &uart6; 34 serial6 = &uart7; 35 serial7 = &uart8; 36 serial8 = &uart9; 37 serial9 = &uart10; 38 serial10 = &uart11; 39 serial11 = &uart12; 40 serial12 = &uart13; 41 }; 42 43 cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 enable-method = "aspeed,ast2600-smp"; 47 48 cpu@0 { 49 compatible = "arm,cortex-a7"; 50 device_type = "cpu"; 51 reg = <0>; 52 clock-frequency = <48000000>; 53 }; 54 55 cpu@1 { 56 compatible = "arm,cortex-a7"; 57 device_type = "cpu"; 58 reg = <1>; 59 clock-frequency = <48000000>; 60 }; 61 62 }; 63 64 timer { 65 compatible = "arm,armv7-timer"; 66 interrupt-parent = <&gic>; 67 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 68 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 69 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 70 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 71 clock-frequency = <25000000>; 72 }; 73 74 memory@80000000 { 75 device_type = "memory"; 76 reg = <0x80000000 0>; 77 }; 78 79 reserved-memory { 80 #address-cells = <1>; 81 #size-cells = <1>; 82 ranges; 83 84 gfx_memory: framebuffer { 85 size = <0x01000000>; 86 alignment = <0x01000000>; 87 compatible = "shared-dma-pool"; 88 reusable; 89 }; 90 91 video_memory: video { 92 size = <0x04000000>; 93 alignment = <0x01000000>; 94 compatible = "shared-dma-pool"; 95 no-map; 96 }; 97 }; 98 99 ahb { 100 compatible = "simple-bus"; 101 #address-cells = <1>; 102 #size-cells = <1>; 103 device_type = "soc"; 104 ranges; 105 106 gic: interrupt-controller@40461000 { 107 compatible = "arm,cortex-a7-gic"; 108 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 109 #interrupt-cells = <3>; 110 interrupt-controller; 111 interrupt-parent = <&gic>; 112 reg = <0x40461000 0x1000>, 113 <0x40462000 0x1000>, 114 <0x40464000 0x2000>, 115 <0x40466000 0x2000>; 116 }; 117 118 fmc: flash-controller@1e620000 { 119 reg = < 0x1e620000 0xc4 120 0x20000000 0x10000000 >; 121 #address-cells = <1>; 122 #size-cells = <0>; 123 compatible = "aspeed,ast2500-fmc"; 124 status = "disabled"; 125 interrupts = <19>; 126 flash@0 { 127 reg = < 0 >; 128 compatible = "jedec,spi-nor"; 129 status = "disabled"; 130 }; 131 flash@1 { 132 reg = < 1 >; 133 compatible = "jedec,spi-nor"; 134 status = "disabled"; 135 }; 136 flash@2 { 137 reg = < 2 >; 138 compatible = "jedec,spi-nor"; 139 status = "disabled"; 140 }; 141 }; 142 143 spi1: flash-controller@1e630000 { 144 reg = < 0x1e630000 0xc4 145 0x30000000 0x08000000 >; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 compatible = "aspeed,ast2500-spi"; 149 status = "disabled"; 150 flash@0 { 151 reg = < 0 >; 152 compatible = "jedec,spi-nor"; 153 status = "disabled"; 154 }; 155 flash@1 { 156 reg = < 1 >; 157 compatible = "jedec,spi-nor"; 158 status = "disabled"; 159 }; 160 }; 161 162 spi2: flash-controller@1e631000 { 163 reg = < 0x1e631000 0xc4 164 0x38000000 0x08000000 >; 165 #address-cells = <1>; 166 #size-cells = <0>; 167 compatible = "aspeed,ast2500-spi"; 168 status = "disabled"; 169 flash@0 { 170 reg = < 0 >; 171 compatible = "jedec,spi-nor"; 172 status = "disabled"; 173 }; 174 flash@1 { 175 reg = < 1 >; 176 compatible = "jedec,spi-nor"; 177 status = "disabled"; 178 }; 179 }; 180 181 edac: sdram@1e6e0000 { 182 compatible = "aspeed,ast2600-sdram-edac"; 183 reg = <0x1e6e0000 0x174>; 184 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 185 }; 186 187 mac0: ethernet@1e660000 { 188 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; 189 reg = <0x1e660000 0x180>; 190 interrupts = <2>; 191 status = "disabled"; 192 }; 193 194 mac2: ftgmac@1e670000 { 195 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 196 reg = <0x1e670000 0x180>, <0x1e650010 0x4>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 200#if 0 201 phy-handle = <&phy0>; 202#endif 203 status = "disabled"; 204 }; 205 206 mac1: ftgmac@1e680000 { 207 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 208 reg = <0x1e680000 0x180>, <0x1e650008 0x4>; 209 #address-cells = <1>; 210 #size-cells = <0>; 211 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 212#if 0 213 phy-handle = <&phy0>; 214#endif 215 status = "disabled"; 216 }; 217 218 mac3: ftgmac@1e690000 { 219 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 220 reg = <0x1e690000 0x180>, <0x1e650018 0x4>; 221 #address-cells = <1>; 222 #size-cells = <0>; 223 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 224#if 0 225 phy-handle = <&phy0>; 226#endif 227 status = "disabled"; 228 }; 229 230 231 apb { 232 compatible = "simple-bus"; 233 #address-cells = <1>; 234 #size-cells = <1>; 235 ranges; 236 237 syscon: syscon@1e6e2000 { 238 compatible = "aspeed,aspeed-scu", "aspeed,ast2600-scu", "syscon", "simple-mfd"; 239 reg = <0x1e6e2000 0x1000>; 240 #address-cells = <1>; 241 #size-cells = <1>; 242 #clock-cells = <1>; 243 #reset-cells = <1>; 244 ranges = <0 0x1e6e2000 0x1000>; 245 246 pinctrl: pinctrl { 247 compatible = "aspeed,g6-pinctrl"; 248 aspeed,external-nodes = <&gfx &lhc>; 249 250 }; 251 252 vga_scratch: scratch { 253 compatible = "aspeed,bmc-misc"; 254 }; 255 256 scu_ic0: interrupt-controller@0 { 257 #interrupt-cells = <1>; 258 compatible = "aspeed,ast2600-scu-ic"; 259 reg = <0x560 0x10>; 260 interrupt-parent = <&gic>; 261 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 262 interrupt-controller; 263 }; 264 265 scu_ic1: interrupt-controller@1 { 266 #interrupt-cells = <1>; 267 compatible = "aspeed,ast2600-scu-ic"; 268 reg = <0x570 0x10>; 269 interrupt-parent = <&gic>; 270 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 271 interrupt-controller; 272 }; 273 274 }; 275 276 smp-memram@0 { 277 compatible = "aspeed,ast2600-smpmem", "syscon"; 278 reg = <0x1e6e2180 0x40>; 279 }; 280 281 gfx: display@1e6e6000 { 282 compatible = "aspeed,ast2500-gfx", "syscon"; 283 reg = <0x1e6e6000 0x1000>; 284 reg-io-width = <4>; 285 }; 286 287 uart1: serial@1e783000 { 288 compatible = "ns16550a"; 289 reg = <0x1e783000 0x20>; 290 reg-shift = <2>; 291 no-loopback-test; 292 status = "disabled"; 293 }; 294 295 uart5: serial@1e784000 { 296 compatible = "ns16550a"; 297 reg = <0x1e784000 0x1000>; 298 reg-shift = <2>; 299 clock-frequency = <1846154>; 300 no-loopback-test; 301 }; 302 303 wdt1: watchdog@1e785000 { 304 compatible = "aspeed,ast2600-wdt"; 305 reg = <0x1e785000 0x40>; 306 }; 307 308 wdt2: watchdog@1e785040 { 309 compatible = "aspeed,ast2600-wdt"; 310 reg = <0x1e785040 0x40>; 311 }; 312 313 wdt3: watchdog@1e785080 { 314 compatible = "aspeed,ast2600-wdt"; 315 reg = <0x1e785080 0x40>; 316 }; 317 318 wdt4: watchdog@1e7850C0 { 319 compatible = "aspeed,ast2600-wdt"; 320 reg = <0x1e7850C0 0x40>; 321 }; 322 323 lpc: lpc@1e789000 { 324 compatible = "aspeed,ast-lpc", "simple-mfd", "syscon"; 325 reg = <0x1e789000 0x200>; 326 327 #address-cells = <1>; 328 #size-cells = <1>; 329 ranges = <0x0 0x1e789000 0x1000>; 330 331 lpc_bmc: lpc-bmc@0 { 332 compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon"; 333 reg = <0x0 0x80>; 334 reg-io-width = <4>; 335 #address-cells = <1>; 336 #size-cells = <1>; 337 ranges = <0x0 0x0 0x80>; 338 339 kcs1: kcs1@0 { 340 compatible = "aspeed,ast2600-kcs-bmc"; 341 reg = <0x0 0x80>; 342 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 343 kcs_chan = <1>; 344 kcs_addr = <0xCA0>; 345 status = "disabled"; 346 }; 347 348 kcs2: kcs2@0 { 349 compatible = "aspeed,ast2600-kcs-bmc"; 350 reg = <0x0 0x80>; 351 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 352 kcs_chan = <2>; 353 kcs_addr = <0xCA8>; 354 status = "disabled"; 355 }; 356 357 kcs3: kcs3@0 { 358 compatible = "aspeed,ast2600-kcs-bmc"; 359 reg = <0x0 0x80>; 360 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 361 kcs_chan = <3>; 362 kcs_addr = <0xCA2>; 363 }; 364 365 kcs4: kcs4@0 { 366 compatible = "aspeed,ast2600-kcs-bmc"; 367 reg = <0x0 0x120>; 368 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 369 kcs_chan = <4>; 370 kcs_addr = <0xCA4>; 371 status = "disabled"; 372 }; 373 374 }; 375 376 lpc_host: lpc-host@80 { 377 compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon"; 378 reg = <0x80 0x1e0>; 379 reg-io-width = <4>; 380 381 #address-cells = <1>; 382 #size-cells = <1>; 383 ranges = <0x0 0x80 0x1e0>; 384 385 lpc_ctrl: lpc-ctrl@0 { 386 compatible = "aspeed,ast2600-lpc-ctrl"; 387 reg = <0x0 0x80>; 388 status = "disabled"; 389 }; 390 391 lpc_snoop: lpc-snoop@0 { 392 compatible = "aspeed,ast2600-lpc-snoop"; 393 reg = <0x0 0x80>; 394 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 395 snoop-ports = <0x80>; 396 status = "disabled"; 397 }; 398 399 lhc: lhc@20 { 400 compatible = "aspeed,ast2600-lhc"; 401 reg = <0x20 0x24 0x48 0x8>; 402 }; 403 404 lpc_reset: reset-controller@18 { 405 compatible = "aspeed,ast2600-lpc-reset"; 406 reg = <0x18 0x4>; 407 #reset-cells = <1>; 408 status = "disabled"; 409 }; 410 411 ibt: ibt@c0 { 412 compatible = "aspeed,ast2600-ibt-bmc"; 413 reg = <0xc0 0x18>; 414 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 415 status = "disabled"; 416 }; 417 418 sio_regs: regs { 419 compatible = "aspeed,bmc-misc"; 420 }; 421 422 mbox: mbox@180 { 423 compatible = "aspeed,ast2600-mbox"; 424 reg = <0x180 0x5c>; 425 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 426 #mbox-cells = <1>; 427 status = "disabled"; 428 }; 429 }; 430 }; 431 432 uart2: serial@1e78d000 { 433 compatible = "ns16550a"; 434 reg = <0x1e78d000 0x20>; 435 reg-shift = <2>; 436 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 437 no-loopback-test; 438 status = "disabled"; 439 }; 440 441 uart3: serial@1e78e000 { 442 compatible = "ns16550a"; 443 reg = <0x1e78e000 0x20>; 444 reg-shift = <2>; 445 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 446 no-loopback-test; 447 status = "disabled"; 448 }; 449 450 uart4: serial@1e78f000 { 451 compatible = "ns16550a"; 452 reg = <0x1e78f000 0x20>; 453 reg-shift = <2>; 454 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 455 no-loopback-test; 456 status = "disabled"; 457 }; 458 459 i2c: bus@1e78a000 { 460 compatible = "simple-bus"; 461 #address-cells = <1>; 462 #size-cells = <1>; 463 ranges = <0 0x1e78a000 0x1000>; 464 }; 465 466 uart6: serial@1e790000 { 467 compatible = "ns16550a"; 468 reg = <0x1e790000 0x20>; 469 reg-shift = <2>; 470 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 471 no-loopback-test; 472 status = "disabled"; 473 }; 474 475 uart7: serial@1e790100 { 476 compatible = "ns16550a"; 477 reg = <0x1e790100 0x20>; 478 reg-shift = <2>; 479 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 480 no-loopback-test; 481 status = "disabled"; 482 }; 483 484 uart8: serial@1e790200 { 485 compatible = "ns16550a"; 486 reg = <0x1e790200 0x20>; 487 reg-shift = <2>; 488 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 489 no-loopback-test; 490 status = "disabled"; 491 }; 492 493 uart9: serial@1e790300 { 494 compatible = "ns16550a"; 495 reg = <0x1e790300 0x20>; 496 reg-shift = <2>; 497 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 498 no-loopback-test; 499 status = "disabled"; 500 }; 501 502 uart10: serial@1e790400 { 503 compatible = "ns16550a"; 504 reg = <0x1e790400 0x20>; 505 reg-shift = <2>; 506 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 507 no-loopback-test; 508 status = "disabled"; 509 }; 510 511 uart11: serial@1e790500 { 512 compatible = "ns16550a"; 513 reg = <0x1e790400 0x20>; 514 reg-shift = <2>; 515 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 516 no-loopback-test; 517 status = "disabled"; 518 }; 519 520 uart12: serial@1e790600 { 521 compatible = "ns16550a"; 522 reg = <0x1e790600 0x20>; 523 reg-shift = <2>; 524 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 525 no-loopback-test; 526 status = "disabled"; 527 }; 528 529 uart13: serial@1e790700 { 530 compatible = "ns16550a"; 531 reg = <0x1e790700 0x20>; 532 reg-shift = <2>; 533 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 534 no-loopback-test; 535 status = "disabled"; 536 }; 537 538 539 540 }; 541 542 }; 543 544}; 545 546&i2c { 547 i2cglobal: i2cg@00 { 548 compatible = "aspeed,ast2600-i2c-global", "syscon", "simple-mfd"; 549 reg = <0x0 0x40>; 550 551#if 0 552 new-mode; 553#endif 554 }; 555 556 i2c0: i2c@80 { 557 #address-cells = <1>; 558 #size-cells = <0>; 559 #interrupt-cells = <1>; 560 561 reg = <0x80 0x80 0xC00 0x20>; 562 compatible = "aspeed,ast2600-i2c-bus"; 563#if 0 564 compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 565 #compatible = "aspeed,ast2500-i2c-bus"; 566 #compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 567#endif 568 bus-frequency = <100000>; 569 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 570 }; 571 572 i2c1: i2c@100 { 573 #address-cells = <1>; 574 #size-cells = <0>; 575 #interrupt-cells = <1>; 576 577 reg = <0x100 0x80 0xC20 0x20>; 578 compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 579#if 0 580 #compatible = "aspeed,ast2500-i2c-bus"; 581 #compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 582#endif 583 bus-frequency = <100000>; 584 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 585 }; 586 587 i2c2: i2c@180 { 588 #address-cells = <1>; 589 #size-cells = <0>; 590 #interrupt-cells = <1>; 591 592 reg = <0x180 0x80 0xC40 0x20>; 593 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 594 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 595 bus-frequency = <100000>; 596 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 597 }; 598 599 i2c3: i2c@200 { 600 #address-cells = <1>; 601 #size-cells = <0>; 602 #interrupt-cells = <1>; 603 604 reg = <0x200 0x40 0xC60 0x20>; 605 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 606 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 607 bus-frequency = <100000>; 608 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 609 }; 610 611 i2c4: i2c@280 { 612 #address-cells = <1>; 613 #size-cells = <0>; 614 #interrupt-cells = <1>; 615 616 reg = <0x280 0x80 0xC80 0x20>; 617 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 618 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 619 bus-frequency = <100000>; 620 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 621 }; 622 623 i2c5: i2c@300 { 624 #address-cells = <1>; 625 #size-cells = <0>; 626 #interrupt-cells = <1>; 627 628 reg = <0x300 0x40 0xCA0 0x20>; 629 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 630 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 631 bus-frequency = <100000>; 632 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 633 }; 634 635 i2c6: i2c@380 { 636 #address-cells = <1>; 637 #size-cells = <0>; 638 #interrupt-cells = <1>; 639 640 reg = <0x380 0x80 0xCC0 0x20>; 641 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 642 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 643 bus-frequency = <100000>; 644 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 645 }; 646 647 i2c7: i2c@400 { 648 #address-cells = <1>; 649 #size-cells = <0>; 650 #interrupt-cells = <1>; 651 652 reg = <0x400 0x80 0xCE0 0x20>; 653 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 654 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 655 bus-frequency = <100000>; 656 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 657 }; 658 659 i2c8: i2c@480 { 660 #address-cells = <1>; 661 #size-cells = <0>; 662 #interrupt-cells = <1>; 663 664 reg = <0x480 0x80 0xD00 0x20>; 665 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 666 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 667 bus-frequency = <100000>; 668 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 669 }; 670 671 i2c9: i2c@500 { 672 #address-cells = <1>; 673 #size-cells = <0>; 674 #interrupt-cells = <1>; 675 676 reg = <0x500 0x80 0xD20 0x20>; 677 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 678 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 679 bus-frequency = <100000>; 680 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 681 status = "disabled"; 682 }; 683 684 i2c10: i2c@580 { 685 #address-cells = <1>; 686 #size-cells = <0>; 687 #interrupt-cells = <1>; 688 689 reg = <0x580 0x80 0xD40 0x20>; 690 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 691 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 692 bus-frequency = <100000>; 693 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 694 status = "disabled"; 695 }; 696 697 i2c11: i2c@600 { 698 #address-cells = <1>; 699 #size-cells = <0>; 700 #interrupt-cells = <1>; 701 702 reg = <0x600 0x80 0xD60 0x20>; 703 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 704 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 705 bus-frequency = <100000>; 706 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 707 status = "disabled"; 708 }; 709 710 i2c12: i2c@680 { 711 #address-cells = <1>; 712 #size-cells = <0>; 713 #interrupt-cells = <1>; 714 715 reg = <0x680 0x80 0xD80 0x20>; 716 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 717 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 718 bus-frequency = <100000>; 719 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 720 status = "disabled"; 721 }; 722 723 i2c13: i2c@700 { 724 #address-cells = <1>; 725 #size-cells = <0>; 726 #interrupt-cells = <1>; 727 728 reg = <0x700 0x80 0xDA0 0x20>; 729 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 730 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 731 bus-frequency = <100000>; 732 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 733 status = "disabled"; 734 }; 735 736 i2c14: i2c@780 { 737 #address-cells = <1>; 738 #size-cells = <0>; 739 #interrupt-cells = <1>; 740 741 reg = <0x780 0x80 0xDC0 0x20>; 742 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 743 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 744 bus-frequency = <100000>; 745 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 746 status = "disabled"; 747 }; 748 749 i2c15: i2c@800 { 750 #address-cells = <1>; 751 #size-cells = <0>; 752 #interrupt-cells = <1>; 753 754 reg = <0x800 0x80 0xDE0 0x20>; 755 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 756 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 757 bus-frequency = <100000>; 758 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 759 status = "disabled"; 760 }; 761 762}; 763 764&pinctrl { 765 pinctrl_acpi_default: acpi_default { 766 function = "ACPI"; 767 groups = "ACPI"; 768 }; 769 770 pinctrl_adc0_default: adc0_default { 771 function = "ADC0"; 772 groups = "ADC0"; 773 }; 774 775 pinctrl_adc1_default: adc1_default { 776 function = "ADC1"; 777 groups = "ADC1"; 778 }; 779 780 pinctrl_adc10_default: adc10_default { 781 function = "ADC10"; 782 groups = "ADC10"; 783 }; 784 785 pinctrl_adc11_default: adc11_default { 786 function = "ADC11"; 787 groups = "ADC11"; 788 }; 789 790 pinctrl_adc12_default: adc12_default { 791 function = "ADC12"; 792 groups = "ADC12"; 793 }; 794 795 pinctrl_adc13_default: adc13_default { 796 function = "ADC13"; 797 groups = "ADC13"; 798 }; 799 800 pinctrl_adc14_default: adc14_default { 801 function = "ADC14"; 802 groups = "ADC14"; 803 }; 804 805 pinctrl_adc15_default: adc15_default { 806 function = "ADC15"; 807 groups = "ADC15"; 808 }; 809 810 pinctrl_adc2_default: adc2_default { 811 function = "ADC2"; 812 groups = "ADC2"; 813 }; 814 815 pinctrl_adc3_default: adc3_default { 816 function = "ADC3"; 817 groups = "ADC3"; 818 }; 819 820 pinctrl_adc4_default: adc4_default { 821 function = "ADC4"; 822 groups = "ADC4"; 823 }; 824 825 pinctrl_adc5_default: adc5_default { 826 function = "ADC5"; 827 groups = "ADC5"; 828 }; 829 830 pinctrl_adc6_default: adc6_default { 831 function = "ADC6"; 832 groups = "ADC6"; 833 }; 834 835 pinctrl_adc7_default: adc7_default { 836 function = "ADC7"; 837 groups = "ADC7"; 838 }; 839 840 pinctrl_adc8_default: adc8_default { 841 function = "ADC8"; 842 groups = "ADC8"; 843 }; 844 845 pinctrl_adc9_default: adc9_default { 846 function = "ADC9"; 847 groups = "ADC9"; 848 }; 849 850 pinctrl_bmcint_default: bmcint_default { 851 function = "BMCINT"; 852 groups = "BMCINT"; 853 }; 854 855 pinctrl_ddcclk_default: ddcclk_default { 856 function = "DDCCLK"; 857 groups = "DDCCLK"; 858 }; 859 860 pinctrl_ddcdat_default: ddcdat_default { 861 function = "DDCDAT"; 862 groups = "DDCDAT"; 863 }; 864 865 pinctrl_espi_default: espi_default { 866 function = "ESPI"; 867 groups = "ESPI"; 868 }; 869 870 pinctrl_fwspics1_default: fwspics1_default { 871 function = "FWSPICS1"; 872 groups = "FWSPICS1"; 873 }; 874 875 pinctrl_fwspics2_default: fwspics2_default { 876 function = "FWSPICS2"; 877 groups = "FWSPICS2"; 878 }; 879 880 pinctrl_gpid0_default: gpid0_default { 881 function = "GPID0"; 882 groups = "GPID0"; 883 }; 884 885 pinctrl_gpid2_default: gpid2_default { 886 function = "GPID2"; 887 groups = "GPID2"; 888 }; 889 890 pinctrl_gpid4_default: gpid4_default { 891 function = "GPID4"; 892 groups = "GPID4"; 893 }; 894 895 pinctrl_gpid6_default: gpid6_default { 896 function = "GPID6"; 897 groups = "GPID6"; 898 }; 899 900 pinctrl_gpie0_default: gpie0_default { 901 function = "GPIE0"; 902 groups = "GPIE0"; 903 }; 904 905 pinctrl_gpie2_default: gpie2_default { 906 function = "GPIE2"; 907 groups = "GPIE2"; 908 }; 909 910 pinctrl_gpie4_default: gpie4_default { 911 function = "GPIE4"; 912 groups = "GPIE4"; 913 }; 914 915 pinctrl_gpie6_default: gpie6_default { 916 function = "GPIE6"; 917 groups = "GPIE6"; 918 }; 919 920 pinctrl_i2c10_default: i2c10_default { 921 function = "I2C10"; 922 groups = "I2C10"; 923 }; 924 925 pinctrl_i2c11_default: i2c11_default { 926 function = "I2C11"; 927 groups = "I2C11"; 928 }; 929 930 pinctrl_i2c12_default: i2c12_default { 931 function = "I2C12"; 932 groups = "I2C12"; 933 }; 934 935 pinctrl_i2c13_default: i2c13_default { 936 function = "I2C13"; 937 groups = "I2C13"; 938 }; 939 940 pinctrl_i2c14_default: i2c14_default { 941 function = "I2C14"; 942 groups = "I2C14"; 943 }; 944 945 pinctrl_i2c3_default: i2c3_default { 946 function = "I2C3"; 947 groups = "I2C3"; 948 }; 949 950 pinctrl_i2c4_default: i2c4_default { 951 function = "I2C4"; 952 groups = "I2C4"; 953 }; 954 955 pinctrl_i2c5_default: i2c5_default { 956 function = "I2C5"; 957 groups = "I2C5"; 958 }; 959 960 pinctrl_i2c6_default: i2c6_default { 961 function = "I2C6"; 962 groups = "I2C6"; 963 }; 964 965 pinctrl_i2c7_default: i2c7_default { 966 function = "I2C7"; 967 groups = "I2C7"; 968 }; 969 970 pinctrl_i2c8_default: i2c8_default { 971 function = "I2C8"; 972 groups = "I2C8"; 973 }; 974 975 pinctrl_i2c9_default: i2c9_default { 976 function = "I2C9"; 977 groups = "I2C9"; 978 }; 979 980 pinctrl_lad0_default: lad0_default { 981 function = "LAD0"; 982 groups = "LAD0"; 983 }; 984 985 pinctrl_lad1_default: lad1_default { 986 function = "LAD1"; 987 groups = "LAD1"; 988 }; 989 990 pinctrl_lad2_default: lad2_default { 991 function = "LAD2"; 992 groups = "LAD2"; 993 }; 994 995 pinctrl_lad3_default: lad3_default { 996 function = "LAD3"; 997 groups = "LAD3"; 998 }; 999 1000 pinctrl_lclk_default: lclk_default { 1001 function = "LCLK"; 1002 groups = "LCLK"; 1003 }; 1004 1005 pinctrl_lframe_default: lframe_default { 1006 function = "LFRAME"; 1007 groups = "LFRAME"; 1008 }; 1009 1010 pinctrl_lpchc_default: lpchc_default { 1011 function = "LPCHC"; 1012 groups = "LPCHC"; 1013 }; 1014 1015 pinctrl_lpcpd_default: lpcpd_default { 1016 function = "LPCPD"; 1017 groups = "LPCPD"; 1018 }; 1019 1020 pinctrl_lpcplus_default: lpcplus_default { 1021 function = "LPCPLUS"; 1022 groups = "LPCPLUS"; 1023 }; 1024 1025 pinctrl_lpcpme_default: lpcpme_default { 1026 function = "LPCPME"; 1027 groups = "LPCPME"; 1028 }; 1029 1030 pinctrl_lpcrst_default: lpcrst_default { 1031 function = "LPCRST"; 1032 groups = "LPCRST"; 1033 }; 1034 1035 pinctrl_lpcsmi_default: lpcsmi_default { 1036 function = "LPCSMI"; 1037 groups = "LPCSMI"; 1038 }; 1039 1040 pinctrl_lsirq_default: lsirq_default { 1041 function = "LSIRQ"; 1042 groups = "LSIRQ"; 1043 }; 1044 1045 pinctrl_mac1link_default: mac1link_default { 1046 function = "MAC1LINK"; 1047 groups = "MAC1LINK"; 1048 }; 1049 1050 pinctrl_mac2link_default: mac2link_default { 1051 function = "MAC2LINK"; 1052 groups = "MAC2LINK"; 1053 }; 1054 1055 pinctrl_mac3link_default: mac3link_default { 1056 function = "MAC3LINK"; 1057 groups = "MAC3LINK"; 1058 }; 1059 1060 pinctrl_mac4link_default: mac4link_default { 1061 function = "MAC4LINK"; 1062 groups = "MAC4LINK"; 1063 }; 1064 1065 pinctrl_mdio1_default: mdio1_default { 1066 function = "MDIO1"; 1067 groups = "MDIO1"; 1068 }; 1069 1070 pinctrl_mdio2_default: mdio2_default { 1071 function = "MDIO2"; 1072 groups = "MDIO2"; 1073 }; 1074 1075 pinctrl_mdio3_default: mdio3_default { 1076 function = "MDIO3"; 1077 groups = "MDIO3"; 1078 }; 1079 1080 pinctrl_mdio4_default: mdio4_default { 1081 function = "MDIO4"; 1082 groups = "MDIO4"; 1083 }; 1084 1085 pinctrl_ncts1_default: ncts1_default { 1086 function = "NCTS1"; 1087 groups = "NCTS1"; 1088 }; 1089 1090 pinctrl_ncts2_default: ncts2_default { 1091 function = "NCTS2"; 1092 groups = "NCTS2"; 1093 }; 1094 1095 pinctrl_ncts3_default: ncts3_default { 1096 function = "NCTS3"; 1097 groups = "NCTS3"; 1098 }; 1099 1100 pinctrl_ncts4_default: ncts4_default { 1101 function = "NCTS4"; 1102 groups = "NCTS4"; 1103 }; 1104 1105 pinctrl_ndcd1_default: ndcd1_default { 1106 function = "NDCD1"; 1107 groups = "NDCD1"; 1108 }; 1109 1110 pinctrl_ndcd2_default: ndcd2_default { 1111 function = "NDCD2"; 1112 groups = "NDCD2"; 1113 }; 1114 1115 pinctrl_ndcd3_default: ndcd3_default { 1116 function = "NDCD3"; 1117 groups = "NDCD3"; 1118 }; 1119 1120 pinctrl_ndcd4_default: ndcd4_default { 1121 function = "NDCD4"; 1122 groups = "NDCD4"; 1123 }; 1124 1125 pinctrl_ndsr1_default: ndsr1_default { 1126 function = "NDSR1"; 1127 groups = "NDSR1"; 1128 }; 1129 1130 pinctrl_ndsr2_default: ndsr2_default { 1131 function = "NDSR2"; 1132 groups = "NDSR2"; 1133 }; 1134 1135 pinctrl_ndsr3_default: ndsr3_default { 1136 function = "NDSR3"; 1137 groups = "NDSR3"; 1138 }; 1139 1140 pinctrl_ndsr4_default: ndsr4_default { 1141 function = "NDSR4"; 1142 groups = "NDSR4"; 1143 }; 1144 1145 pinctrl_ndtr1_default: ndtr1_default { 1146 function = "NDTR1"; 1147 groups = "NDTR1"; 1148 }; 1149 1150 pinctrl_ndtr2_default: ndtr2_default { 1151 function = "NDTR2"; 1152 groups = "NDTR2"; 1153 }; 1154 1155 pinctrl_ndtr3_default: ndtr3_default { 1156 function = "NDTR3"; 1157 groups = "NDTR3"; 1158 }; 1159 1160 pinctrl_ndtr4_default: ndtr4_default { 1161 function = "NDTR4"; 1162 groups = "NDTR4"; 1163 }; 1164 1165 pinctrl_nri1_default: nri1_default { 1166 function = "NRI1"; 1167 groups = "NRI1"; 1168 }; 1169 1170 pinctrl_nri2_default: nri2_default { 1171 function = "NRI2"; 1172 groups = "NRI2"; 1173 }; 1174 1175 pinctrl_nri3_default: nri3_default { 1176 function = "NRI3"; 1177 groups = "NRI3"; 1178 }; 1179 1180 pinctrl_nri4_default: nri4_default { 1181 function = "NRI4"; 1182 groups = "NRI4"; 1183 }; 1184 1185 pinctrl_nrts1_default: nrts1_default { 1186 function = "NRTS1"; 1187 groups = "NRTS1"; 1188 }; 1189 1190 pinctrl_nrts2_default: nrts2_default { 1191 function = "NRTS2"; 1192 groups = "NRTS2"; 1193 }; 1194 1195 pinctrl_nrts3_default: nrts3_default { 1196 function = "NRTS3"; 1197 groups = "NRTS3"; 1198 }; 1199 1200 pinctrl_nrts4_default: nrts4_default { 1201 function = "NRTS4"; 1202 groups = "NRTS4"; 1203 }; 1204 1205 pinctrl_oscclk_default: oscclk_default { 1206 function = "OSCCLK"; 1207 groups = "OSCCLK"; 1208 }; 1209 1210 pinctrl_pewake_default: pewake_default { 1211 function = "PEWAKE"; 1212 groups = "PEWAKE"; 1213 }; 1214 1215 pinctrl_pnor_default: pnor_default { 1216 function = "PNOR"; 1217 groups = "PNOR"; 1218 }; 1219 1220 pinctrl_pwm0_default: pwm0_default { 1221 function = "PWM0"; 1222 groups = "PWM0"; 1223 }; 1224 1225 pinctrl_pwm1_default: pwm1_default { 1226 function = "PWM1"; 1227 groups = "PWM1"; 1228 }; 1229 1230 pinctrl_pwm2_default: pwm2_default { 1231 function = "PWM2"; 1232 groups = "PWM2"; 1233 }; 1234 1235 pinctrl_pwm3_default: pwm3_default { 1236 function = "PWM3"; 1237 groups = "PWM3"; 1238 }; 1239 1240 pinctrl_pwm4_default: pwm4_default { 1241 function = "PWM4"; 1242 groups = "PWM4"; 1243 }; 1244 1245 pinctrl_pwm5_default: pwm5_default { 1246 function = "PWM5"; 1247 groups = "PWM5"; 1248 }; 1249 1250 pinctrl_pwm6_default: pwm6_default { 1251 function = "PWM6"; 1252 groups = "PWM6"; 1253 }; 1254 1255 pinctrl_pwm7_default: pwm7_default { 1256 function = "PWM7"; 1257 groups = "PWM7"; 1258 }; 1259 1260 pinctrl_rgmii1_default: rgmii1_default { 1261 function = "RGMII1"; 1262 groups = "RGMII1"; 1263 }; 1264 1265 pinctrl_rgmii2_default: rgmii2_default { 1266 function = "RGMII2"; 1267 groups = "RGMII2"; 1268 }; 1269 1270 pinctrl_rmii1_default: rmii1_default { 1271 function = "RMII1"; 1272 groups = "RMII1"; 1273 }; 1274 1275 pinctrl_rmii2_default: rmii2_default { 1276 function = "RMII2"; 1277 groups = "RMII2"; 1278 }; 1279 1280 pinctrl_rxd1_default: rxd1_default { 1281 function = "RXD1"; 1282 groups = "RXD1"; 1283 }; 1284 1285 pinctrl_rxd2_default: rxd2_default { 1286 function = "RXD2"; 1287 groups = "RXD2"; 1288 }; 1289 1290 pinctrl_rxd3_default: rxd3_default { 1291 function = "RXD3"; 1292 groups = "RXD3"; 1293 }; 1294 1295 pinctrl_rxd4_default: rxd4_default { 1296 function = "RXD4"; 1297 groups = "RXD4"; 1298 }; 1299 1300 pinctrl_salt1_default: salt1_default { 1301 function = "SALT1"; 1302 groups = "SALT1"; 1303 }; 1304 1305 pinctrl_salt10_default: salt10_default { 1306 function = "SALT10"; 1307 groups = "SALT10"; 1308 }; 1309 1310 pinctrl_salt11_default: salt11_default { 1311 function = "SALT11"; 1312 groups = "SALT11"; 1313 }; 1314 1315 pinctrl_salt12_default: salt12_default { 1316 function = "SALT12"; 1317 groups = "SALT12"; 1318 }; 1319 1320 pinctrl_salt13_default: salt13_default { 1321 function = "SALT13"; 1322 groups = "SALT13"; 1323 }; 1324 1325 pinctrl_salt14_default: salt14_default { 1326 function = "SALT14"; 1327 groups = "SALT14"; 1328 }; 1329 1330 pinctrl_salt2_default: salt2_default { 1331 function = "SALT2"; 1332 groups = "SALT2"; 1333 }; 1334 1335 pinctrl_salt3_default: salt3_default { 1336 function = "SALT3"; 1337 groups = "SALT3"; 1338 }; 1339 1340 pinctrl_salt4_default: salt4_default { 1341 function = "SALT4"; 1342 groups = "SALT4"; 1343 }; 1344 1345 pinctrl_salt5_default: salt5_default { 1346 function = "SALT5"; 1347 groups = "SALT5"; 1348 }; 1349 1350 pinctrl_salt6_default: salt6_default { 1351 function = "SALT6"; 1352 groups = "SALT6"; 1353 }; 1354 1355 pinctrl_salt7_default: salt7_default { 1356 function = "SALT7"; 1357 groups = "SALT7"; 1358 }; 1359 1360 pinctrl_salt8_default: salt8_default { 1361 function = "SALT8"; 1362 groups = "SALT8"; 1363 }; 1364 1365 pinctrl_salt9_default: salt9_default { 1366 function = "SALT9"; 1367 groups = "SALT9"; 1368 }; 1369 1370 pinctrl_scl1_default: scl1_default { 1371 function = "SCL1"; 1372 groups = "SCL1"; 1373 }; 1374 1375 pinctrl_scl2_default: scl2_default { 1376 function = "SCL2"; 1377 groups = "SCL2"; 1378 }; 1379 1380 pinctrl_sd1_default: sd1_default { 1381 function = "SD1"; 1382 groups = "SD1"; 1383 }; 1384 1385 pinctrl_sd2_default: sd2_default { 1386 function = "SD2"; 1387 groups = "SD2"; 1388 }; 1389 1390 pinctrl_sda1_default: sda1_default { 1391 function = "SDA1"; 1392 groups = "SDA1"; 1393 }; 1394 1395 pinctrl_sda2_default: sda2_default { 1396 function = "SDA2"; 1397 groups = "SDA2"; 1398 }; 1399 1400 pinctrl_sgps1_default: sgps1_default { 1401 function = "SGPS1"; 1402 groups = "SGPS1"; 1403 }; 1404 1405 pinctrl_sgps2_default: sgps2_default { 1406 function = "SGPS2"; 1407 groups = "SGPS2"; 1408 }; 1409 1410 pinctrl_sioonctrl_default: sioonctrl_default { 1411 function = "SIOONCTRL"; 1412 groups = "SIOONCTRL"; 1413 }; 1414 1415 pinctrl_siopbi_default: siopbi_default { 1416 function = "SIOPBI"; 1417 groups = "SIOPBI"; 1418 }; 1419 1420 pinctrl_siopbo_default: siopbo_default { 1421 function = "SIOPBO"; 1422 groups = "SIOPBO"; 1423 }; 1424 1425 pinctrl_siopwreq_default: siopwreq_default { 1426 function = "SIOPWREQ"; 1427 groups = "SIOPWREQ"; 1428 }; 1429 1430 pinctrl_siopwrgd_default: siopwrgd_default { 1431 function = "SIOPWRGD"; 1432 groups = "SIOPWRGD"; 1433 }; 1434 1435 pinctrl_sios3_default: sios3_default { 1436 function = "SIOS3"; 1437 groups = "SIOS3"; 1438 }; 1439 1440 pinctrl_sios5_default: sios5_default { 1441 function = "SIOS5"; 1442 groups = "SIOS5"; 1443 }; 1444 1445 pinctrl_siosci_default: siosci_default { 1446 function = "SIOSCI"; 1447 groups = "SIOSCI"; 1448 }; 1449 1450 pinctrl_spi1_default: spi1_default { 1451 function = "SPI1"; 1452 groups = "SPI1"; 1453 }; 1454 1455 pinctrl_spi1cs1_default: spi1cs1_default { 1456 function = "SPI1CS1"; 1457 groups = "SPI1CS1"; 1458 }; 1459 1460 pinctrl_spi1debug_default: spi1debug_default { 1461 function = "SPI1DEBUG"; 1462 groups = "SPI1DEBUG"; 1463 }; 1464 1465 pinctrl_spi1passthru_default: spi1passthru_default { 1466 function = "SPI1PASSTHRU"; 1467 groups = "SPI1PASSTHRU"; 1468 }; 1469 1470 pinctrl_spi2ck_default: spi2ck_default { 1471 function = "SPI2CK"; 1472 groups = "SPI2CK"; 1473 }; 1474 1475 pinctrl_spi2cs0_default: spi2cs0_default { 1476 function = "SPI2CS0"; 1477 groups = "SPI2CS0"; 1478 }; 1479 1480 pinctrl_spi2cs1_default: spi2cs1_default { 1481 function = "SPI2CS1"; 1482 groups = "SPI2CS1"; 1483 }; 1484 1485 pinctrl_spi2miso_default: spi2miso_default { 1486 function = "SPI2MISO"; 1487 groups = "SPI2MISO"; 1488 }; 1489 1490 pinctrl_spi2mosi_default: spi2mosi_default { 1491 function = "SPI2MOSI"; 1492 groups = "SPI2MOSI"; 1493 }; 1494 1495 pinctrl_timer3_default: timer3_default { 1496 function = "TIMER3"; 1497 groups = "TIMER3"; 1498 }; 1499 1500 pinctrl_timer4_default: timer4_default { 1501 function = "TIMER4"; 1502 groups = "TIMER4"; 1503 }; 1504 1505 pinctrl_timer5_default: timer5_default { 1506 function = "TIMER5"; 1507 groups = "TIMER5"; 1508 }; 1509 1510 pinctrl_timer6_default: timer6_default { 1511 function = "TIMER6"; 1512 groups = "TIMER6"; 1513 }; 1514 1515 pinctrl_timer7_default: timer7_default { 1516 function = "TIMER7"; 1517 groups = "TIMER7"; 1518 }; 1519 1520 pinctrl_timer8_default: timer8_default { 1521 function = "TIMER8"; 1522 groups = "TIMER8"; 1523 }; 1524 1525 pinctrl_txd1_default: txd1_default { 1526 function = "TXD1"; 1527 groups = "TXD1"; 1528 }; 1529 1530 pinctrl_txd2_default: txd2_default { 1531 function = "TXD2"; 1532 groups = "TXD2"; 1533 }; 1534 1535 pinctrl_txd3_default: txd3_default { 1536 function = "TXD3"; 1537 groups = "TXD3"; 1538 }; 1539 1540 pinctrl_txd4_default: txd4_default { 1541 function = "TXD4"; 1542 groups = "TXD4"; 1543 }; 1544 1545 pinctrl_uart6_default: uart6_default { 1546 function = "UART6"; 1547 groups = "UART6"; 1548 }; 1549 1550 pinctrl_usbcki_default: usbcki_default { 1551 function = "USBCKI"; 1552 groups = "USBCKI"; 1553 }; 1554 1555 pinctrl_usb2ah_default: usb2ah_default { 1556 function = "USB2AH"; 1557 groups = "USB2AH"; 1558 }; 1559 1560 pinctrl_usb11bhid_default: usb11bhid_default { 1561 function = "USB11BHID"; 1562 groups = "USB11BHID"; 1563 }; 1564 1565 pinctrl_usb2bh_default: usb2bh_default { 1566 function = "USB2BH"; 1567 groups = "USB2BH"; 1568 }; 1569 1570 pinctrl_vgabiosrom_default: vgabiosrom_default { 1571 function = "VGABIOSROM"; 1572 groups = "VGABIOSROM"; 1573 }; 1574 1575 pinctrl_vgahs_default: vgahs_default { 1576 function = "VGAHS"; 1577 groups = "VGAHS"; 1578 }; 1579 1580 pinctrl_vgavs_default: vgavs_default { 1581 function = "VGAVS"; 1582 groups = "VGAVS"; 1583 }; 1584 1585 pinctrl_vpi24_default: vpi24_default { 1586 function = "VPI24"; 1587 groups = "VPI24"; 1588 }; 1589 1590 pinctrl_vpo_default: vpo_default { 1591 function = "VPO"; 1592 groups = "VPO"; 1593 }; 1594 1595 pinctrl_wdtrst1_default: wdtrst1_default { 1596 function = "WDTRST1"; 1597 groups = "WDTRST1"; 1598 }; 1599 1600 pinctrl_wdtrst2_default: wdtrst2_default { 1601 function = "WDTRST2"; 1602 groups = "WDTRST2"; 1603 }; 1604}; 1605