1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) ASPEED Technology Inc. 4 * Chia-Wei Wang <chiawei_wang@aspeedtech.com> 5 */ 6 7#include <config.h> 8#include <version.h> 9#include <asm/secure.h> 10#include <asm/armv7.h> 11#include <linux/linkage.h> 12 13/* 14 * SMP mailbox 15 * +----------------------+ 16 * | | 17 * | mailbox insn. for | 18 * | cpuN polling SMP go | 19 * | | 20 * +----------------------+ 0xC 21 * | mailbox ready signal | 22 * +----------------------+ 0x8 23 * | cpuN GO signal | 24 * +----------------------+ 0x4 25 * | cpuN entrypoint | 26 * +----------------------+ AST_SMP_MAILBOX_BASE 27 */ 28 29#define AST_SMP_MAILBOX_BASE 0x1E6E2180 30#define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 31#define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 32#define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 33#define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 34 35/* AST2600 HW registers */ 36#define AST_SCU_BASE 0x1E6E2000 37#define AST_SCU_PROT_KEY1 (AST_SCU_BASE) 38#define AST_SCU_PROT_KEY2 (AST_SCU_BASE + 0x010) 39#define AST_SCU_REV_ID (AST_SCU_BASE + 0x014) 40#define AST_SCU_HPLL_PARAM (AST_SCU_BASE + 0x200) 41#define AST_SCU_HPLL_PARAM_EXT (AST_SCU_BASE + 0x204) 42#define AST_SCU_HW_STRAP1 (AST_SCU_BASE + 0x500) 43#define AST_SCU_CA7_PARITY_CHK (AST_SCU_BASE + 0x820) 44#define AST_SCU_CA7_PARITY_CLR (AST_SCU_BASE + 0x824) 45 46#define AST_FMC_BASE 0x1E620000 47#define AST_FMC_WDT1_CTRL_MODE (AST_FMC_BASE + 0x060) 48#define AST_FMC_WDT2_CTRL_MODE (AST_FMC_BASE + 0x064) 49 50/* Revision ID */ 51#define REV_ID_AST2600A0 0x05000303 52 53ENTRY(ast_bootmode) 54 ldr r1, =AST_SCU_HW_STRAP1 55 ldr r0, [r1] 56 tst r0, #0x4 57 moveq r0, #0x0 @; AST_BOOTMODE_SPI 58 movne r0, #0x1 @; AST_BOOTMODE_EMMC 59 mov pc, lr 60ENDPROC(ast_bootmode) 61 62.macro scu_unlock 63 movw r0, #0xA8A8 64 movt r0, #0x1688 @; magic key to unlock SCU 65 66 ldr r1, =AST_SCU_PROT_KEY1 67 str r0, [r1] 68 ldr r1, =AST_SCU_PROT_KEY2 69 str r0, [r1] 70.endm 71 72.macro timer_init 73#ifdef CONFIG_FPGA_ASPEED 74 movw r0, #0x7840 75 movt r0, #0x17D 76#else 77 movw r0, #0x2340 78 movt r0, #0x430E 79#endif 80 mcr p15, 0, r0, c14, c0, 0 @; update CNTFRQ 81.endm 82 83 84.globl lowlevel_init 85 86lowlevel_init: 87#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) 88 mov pc, lr 89#else 90 /* setup ARM arch timer frequency */ 91 timer_init 92 93 /* reset SMP mailbox as early as possible */ 94 mov r0, #0x0 95 ldr r1, =AST_SMP_MBOX_FIELD_READY 96 str r0, [r1] 97 98 /* set ACTLR.SMP to enable cache use */ 99 mrc p15, 0, r0, c1, c0, 1 100 orr r0, #0x40 101 mcr p15, 0, r0, c1, c0, 1 102 103 /* 104 * we treat cpu0 as the primary core and 105 * put secondary core (cpuN) to sleep 106 */ 107 mrc p15, 0, r0, c0, c0, 5 @; Read CPU ID register 108 ands r0, #0xFF @; Mask off, leaving the CPU ID field 109 movw r2, #0xAB00 110 movt r2, #0xABBA 111 orr r2, r0 112 113 beq do_primary_core_setup 114 115 /* hold cpuN until mailbox is ready */ 116poll_mailbox_ready: 117 wfe 118 ldr r0, =AST_SMP_MBOX_FIELD_READY 119 ldr r0, [r0] 120 movw r1, #0xCAFE 121 movt r1, #0xBABE 122 cmp r1, r0 123 bne poll_mailbox_ready 124 125 /* parameters for relocated SMP go polling insn. */ 126 ldr r0, =AST_SMP_MBOX_FIELD_GOSIGN 127 ldr r1, =AST_SMP_MBOX_FIELD_ENTRY 128 129 /* no return */ 130 ldr pc, =AST_SMP_MBOX_FIELD_POLLINSN 131 132do_primary_core_setup: 133 /* unlock system control unit */ 134 scu_unlock 135 136 /* tune-up CPU clock for AST2600 A0 */ 137 ldr r0, =AST_SCU_REV_ID 138 ldr r0, [r0] 139 140 ldr r1, =REV_ID_AST2600A0 141 cmp r0, r1 142 143 bne 0f 144 145 /* setup CPU clocks */ 146 ldr r0, =AST_SCU_HW_STRAP1 147 ldr r1, [r0] 148 bic r1, #0x1800 149 orr r1, #0x1000 150 str r1, [r0] 151 152 ldr r0, =AST_SCU_HPLL_PARAM 153 movw r1, #0x4087 154 movt r1, #0x1000 155 str r1, [r0] 156 157 ldr r0, =AST_SCU_HPLL_PARAM_EXT 158 mov r1, #0x47 159 str r1, [r0] 160 161wait_lock: 162 ldr r1, [r0] 163 tst r1, #0x80000000 164 beq wait_lock 165 1660: 167 /* enable cache & SRAM parity check */ 168 mov r0, #0 169 ldr r1, =AST_SCU_CA7_PARITY_CLR 170 str r0, [r1] 171 172 mov r0, #0x11 173 ldr r1, =AST_SCU_CA7_PARITY_CHK 174 str r0, [r1] 175 176 /* disable FMC WDT for SPI address mode detection */ 177 mov r0, #0 178 ldr r1, =AST_FMC_WDT1_CTRL_MODE 179 str r0, [r1] 180 ldr r1, =AST_FMC_WDT2_CTRL_MODE 181 str r0, [r1] 182 183 /* relocate mailbox insn. for cpuN polling SMP go signal */ 184 adrl r0, mailbox_insn 185 adrl r1, mailbox_insn_end 186 187 ldr r2, =#AST_SMP_MBOX_FIELD_POLLINSN 188 189relocate_mailbox_insn: 190 ldr r3, [r0], #0x4 191 str r3, [r2], #0x4 192 cmp r0, r1 193 bne relocate_mailbox_insn 194 195 /* reset SMP go sign */ 196 mov r0, #0 197 ldr r1, =AST_SMP_MBOX_FIELD_GOSIGN 198 str r0, [r1] 199 200 /* notify cpuN mailbox is ready */ 201 movw r0, #0xCAFE 202 movt r0, #0xBABE 203 ldr r1, =AST_SMP_MBOX_FIELD_READY 204 str r0, [r1] 205 sev 206 207 /* back to arch calling code */ 208 mov pc, lr 209 210/* 211 * insn. inside mailbox to poll SMP go signal. 212 * 213 * Note that as this code will be relocated, any 214 * pc-relative assembly should NOT be used. 215 */ 216mailbox_insn: 217 /* 218 * r0 ~ r3 are parameters: 219 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 220 * r1 = AST_SMP_MBOX_FIELD_ENTRY 221 * r2 = per-cpu go sign value 222 * r3 = no used now 223 */ 224poll_mailbox_smp_go: 225 wfe 226 ldr r4, [r0] 227 cmp r2, r4 228 bne poll_mailbox_smp_go 229 230 /* SMP GO signal confirmed, release cpuN */ 231 ldr pc, [r1] 232 233mailbox_insn_end: 234 /* should never reach */ 235 b . 236 237#endif 238