1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3#include "skeleton.dtsi" 4 5/ { 6 model = "Aspeed BMC"; 7 compatible = "aspeed,ast2600"; 8 #address-cells = <1>; 9 #size-cells = <1>; 10 interrupt-parent = <&gic>; 11 12 aliases { 13 i2c0 = &i2c0; 14 i2c1 = &i2c1; 15 i2c2 = &i2c2; 16 i2c3 = &i2c3; 17 i2c4 = &i2c4; 18 i2c5 = &i2c5; 19 i2c6 = &i2c6; 20 i2c7 = &i2c7; 21 i2c8 = &i2c8; 22 i2c9 = &i2c9; 23 i2c10 = &i2c10; 24 i2c11 = &i2c11; 25 i2c12 = &i2c12; 26 i2c13 = &i2c13; 27 i2c14 = &i2c14; 28 i2c15 = &i2c15; 29 serial0 = &uart1; 30 serial1 = &uart2; 31 serial2 = &uart3; 32 serial3 = &uart4; 33 serial4 = &uart5; 34 serial5 = &uart6; 35 serial6 = &uart7; 36 serial7 = &uart8; 37 serial8 = &uart9; 38 serial9 = &uart10; 39 serial10 = &uart11; 40 serial11 = &uart12; 41 serial12 = &uart13; 42 }; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 enable-method = "aspeed,ast2600-smp"; 48 49 cpu@0 { 50 compatible = "arm,cortex-a7"; 51 device_type = "cpu"; 52 reg = <0>; 53 clock-frequency = <48000000>; 54 }; 55 56 cpu@1 { 57 compatible = "arm,cortex-a7"; 58 device_type = "cpu"; 59 reg = <1>; 60 clock-frequency = <48000000>; 61 }; 62 63 }; 64 65 timer { 66 compatible = "arm,armv7-timer"; 67 interrupt-parent = <&gic>; 68 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 69 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 70 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 71 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 72 clock-frequency = <25000000>; 73 }; 74 75 memory@80000000 { 76 device_type = "memory"; 77 reg = <0x80000000 0>; 78 }; 79 80 reserved-memory { 81 #address-cells = <1>; 82 #size-cells = <1>; 83 ranges; 84 85 gfx_memory: framebuffer { 86 size = <0x01000000>; 87 alignment = <0x01000000>; 88 compatible = "shared-dma-pool"; 89 reusable; 90 }; 91 92 video_memory: video { 93 size = <0x04000000>; 94 alignment = <0x01000000>; 95 compatible = "shared-dma-pool"; 96 no-map; 97 }; 98 }; 99 100 ahb { 101 compatible = "simple-bus"; 102 #address-cells = <1>; 103 #size-cells = <1>; 104 device_type = "soc"; 105 ranges; 106 107 gic: interrupt-controller@40461000 { 108 compatible = "arm,cortex-a7-gic"; 109 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 110 #interrupt-cells = <3>; 111 interrupt-controller; 112 interrupt-parent = <&gic>; 113 reg = <0x40461000 0x1000>, 114 <0x40462000 0x1000>, 115 <0x40464000 0x2000>, 116 <0x40466000 0x2000>; 117 }; 118 119 fmc: flash-controller@1e620000 { 120 reg = < 0x1e620000 0xc4 121 0x20000000 0x10000000 >; 122 #address-cells = <1>; 123 #size-cells = <0>; 124 compatible = "aspeed,ast2500-fmc"; 125 status = "disabled"; 126 interrupts = <19>; 127 flash@0 { 128 reg = < 0 >; 129 compatible = "jedec,spi-nor"; 130 status = "disabled"; 131 }; 132 flash@1 { 133 reg = < 1 >; 134 compatible = "jedec,spi-nor"; 135 status = "disabled"; 136 }; 137 flash@2 { 138 reg = < 2 >; 139 compatible = "jedec,spi-nor"; 140 status = "disabled"; 141 }; 142 }; 143 144 spi1: flash-controller@1e630000 { 145 reg = < 0x1e630000 0xc4 146 0x30000000 0x08000000 >; 147 #address-cells = <1>; 148 #size-cells = <0>; 149 compatible = "aspeed,ast2500-spi"; 150 status = "disabled"; 151 flash@0 { 152 reg = < 0 >; 153 compatible = "jedec,spi-nor"; 154 status = "disabled"; 155 }; 156 flash@1 { 157 reg = < 1 >; 158 compatible = "jedec,spi-nor"; 159 status = "disabled"; 160 }; 161 }; 162 163 spi2: flash-controller@1e631000 { 164 reg = < 0x1e631000 0xc4 165 0x38000000 0x08000000 >; 166 #address-cells = <1>; 167 #size-cells = <0>; 168 compatible = "aspeed,ast2500-spi"; 169 status = "disabled"; 170 flash@0 { 171 reg = < 0 >; 172 compatible = "jedec,spi-nor"; 173 status = "disabled"; 174 }; 175 flash@1 { 176 reg = < 1 >; 177 compatible = "jedec,spi-nor"; 178 status = "disabled"; 179 }; 180 }; 181 182 edac: sdram@1e6e0000 { 183 compatible = "aspeed,ast2600-sdram-edac"; 184 reg = <0x1e6e0000 0x174>; 185 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 186 }; 187 188 mdio: ethernet@1e650000 { 189 compatible = "aspeed,aspeed-mdio"; 190 reg = <0x1e650000 0x40>; 191 status = "disabled"; 192 }; 193 194 mac0: ethernet@1e660000 { 195 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 196 reg = <0x1e660000 0x180>, <0x1e650000 0x4>; 197 interrupts = <2>; 198 status = "disabled"; 199 }; 200 201 mac2: ftgmac@1e670000 { 202 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 203 reg = <0x1e670000 0x180>, <0x1e650010 0x4>; 204 #address-cells = <1>; 205 #size-cells = <0>; 206 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 207#if 0 208 phy-handle = <&phy0>; 209#endif 210 status = "disabled"; 211 }; 212 213 mac1: ftgmac@1e680000 { 214 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 215 reg = <0x1e680000 0x180>, <0x1e650008 0x4>; 216 #address-cells = <1>; 217 #size-cells = <0>; 218 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 219#if 0 220 phy-handle = <&phy0>; 221#endif 222 status = "disabled"; 223 }; 224 225 mac3: ftgmac@1e690000 { 226 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 227 reg = <0x1e690000 0x180>, <0x1e650018 0x4>; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 231#if 0 232 phy-handle = <&phy0>; 233#endif 234 status = "disabled"; 235 }; 236 237 238 apb { 239 compatible = "simple-bus"; 240 #address-cells = <1>; 241 #size-cells = <1>; 242 ranges; 243 244 syscon: syscon@1e6e2000 { 245 compatible = "aspeed,g6-scu", "syscon", "simple-mfd"; 246 reg = <0x1e6e2000 0x1000>; 247 #address-cells = <1>; 248 #size-cells = <1>; 249 #clock-cells = <1>; 250 #reset-cells = <1>; 251 ranges = <0 0x1e6e2000 0x1000>; 252 253 pinctrl: pinctrl { 254 compatible = "aspeed,g6-pinctrl"; 255 aspeed,external-nodes = <&gfx &lhc>; 256 257 }; 258 259 vga_scratch: scratch { 260 compatible = "aspeed,bmc-misc"; 261 }; 262 263 scu_ic0: interrupt-controller@0 { 264 #interrupt-cells = <1>; 265 compatible = "aspeed,ast2600-scu-ic"; 266 reg = <0x560 0x10>; 267 interrupt-parent = <&gic>; 268 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 269 interrupt-controller; 270 }; 271 272 scu_ic1: interrupt-controller@1 { 273 #interrupt-cells = <1>; 274 compatible = "aspeed,ast2600-scu-ic"; 275 reg = <0x570 0x10>; 276 interrupt-parent = <&gic>; 277 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 278 interrupt-controller; 279 }; 280 281 }; 282 283 smp-memram@0 { 284 compatible = "aspeed,ast2600-smpmem", "syscon"; 285 reg = <0x1e6e2180 0x40>; 286 }; 287 288 gfx: display@1e6e6000 { 289 compatible = "aspeed,ast2500-gfx", "syscon"; 290 reg = <0x1e6e6000 0x1000>; 291 reg-io-width = <4>; 292 }; 293 294 uart1: serial@1e783000 { 295 compatible = "ns16550a"; 296 reg = <0x1e783000 0x20>; 297 reg-shift = <2>; 298 no-loopback-test; 299 status = "disabled"; 300 }; 301 302 uart5: serial@1e784000 { 303 compatible = "ns16550a"; 304 reg = <0x1e784000 0x1000>; 305 reg-shift = <2>; 306 clock-frequency = <1846154>; 307 no-loopback-test; 308 }; 309 310 wdt1: watchdog@1e785000 { 311 compatible = "aspeed,ast2600-wdt"; 312 reg = <0x1e785000 0x40>; 313 }; 314 315 wdt2: watchdog@1e785040 { 316 compatible = "aspeed,ast2600-wdt"; 317 reg = <0x1e785040 0x40>; 318 }; 319 320 wdt3: watchdog@1e785080 { 321 compatible = "aspeed,ast2600-wdt"; 322 reg = <0x1e785080 0x40>; 323 }; 324 325 wdt4: watchdog@1e7850C0 { 326 compatible = "aspeed,ast2600-wdt"; 327 reg = <0x1e7850C0 0x40>; 328 }; 329 330 lpc: lpc@1e789000 { 331 compatible = "aspeed,ast-lpc", "simple-mfd", "syscon"; 332 reg = <0x1e789000 0x200>; 333 334 #address-cells = <1>; 335 #size-cells = <1>; 336 ranges = <0x0 0x1e789000 0x1000>; 337 338 lpc_bmc: lpc-bmc@0 { 339 compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon"; 340 reg = <0x0 0x80>; 341 reg-io-width = <4>; 342 #address-cells = <1>; 343 #size-cells = <1>; 344 ranges = <0x0 0x0 0x80>; 345 346 kcs1: kcs1@0 { 347 compatible = "aspeed,ast2600-kcs-bmc"; 348 reg = <0x0 0x80>; 349 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 350 kcs_chan = <1>; 351 kcs_addr = <0xCA0>; 352 status = "disabled"; 353 }; 354 355 kcs2: kcs2@0 { 356 compatible = "aspeed,ast2600-kcs-bmc"; 357 reg = <0x0 0x80>; 358 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 359 kcs_chan = <2>; 360 kcs_addr = <0xCA8>; 361 status = "disabled"; 362 }; 363 364 kcs3: kcs3@0 { 365 compatible = "aspeed,ast2600-kcs-bmc"; 366 reg = <0x0 0x80>; 367 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 368 kcs_chan = <3>; 369 kcs_addr = <0xCA2>; 370 }; 371 372 kcs4: kcs4@0 { 373 compatible = "aspeed,ast2600-kcs-bmc"; 374 reg = <0x0 0x120>; 375 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 376 kcs_chan = <4>; 377 kcs_addr = <0xCA4>; 378 status = "disabled"; 379 }; 380 381 }; 382 383 lpc_host: lpc-host@80 { 384 compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon"; 385 reg = <0x80 0x1e0>; 386 reg-io-width = <4>; 387 388 #address-cells = <1>; 389 #size-cells = <1>; 390 ranges = <0x0 0x80 0x1e0>; 391 392 lpc_ctrl: lpc-ctrl@0 { 393 compatible = "aspeed,ast2600-lpc-ctrl"; 394 reg = <0x0 0x80>; 395 status = "disabled"; 396 }; 397 398 lpc_snoop: lpc-snoop@0 { 399 compatible = "aspeed,ast2600-lpc-snoop"; 400 reg = <0x0 0x80>; 401 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 402 snoop-ports = <0x80>; 403 status = "disabled"; 404 }; 405 406 lhc: lhc@20 { 407 compatible = "aspeed,ast2600-lhc"; 408 reg = <0x20 0x24 0x48 0x8>; 409 }; 410 411 lpc_reset: reset-controller@18 { 412 compatible = "aspeed,ast2600-lpc-reset"; 413 reg = <0x18 0x4>; 414 #reset-cells = <1>; 415 status = "disabled"; 416 }; 417 418 ibt: ibt@c0 { 419 compatible = "aspeed,ast2600-ibt-bmc"; 420 reg = <0xc0 0x18>; 421 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 422 status = "disabled"; 423 }; 424 425 sio_regs: regs { 426 compatible = "aspeed,bmc-misc"; 427 }; 428 429 mbox: mbox@180 { 430 compatible = "aspeed,ast2600-mbox"; 431 reg = <0x180 0x5c>; 432 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 433 #mbox-cells = <1>; 434 status = "disabled"; 435 }; 436 }; 437 }; 438 439 uart2: serial@1e78d000 { 440 compatible = "ns16550a"; 441 reg = <0x1e78d000 0x20>; 442 reg-shift = <2>; 443 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 444 no-loopback-test; 445 status = "disabled"; 446 }; 447 448 uart3: serial@1e78e000 { 449 compatible = "ns16550a"; 450 reg = <0x1e78e000 0x20>; 451 reg-shift = <2>; 452 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 453 no-loopback-test; 454 status = "disabled"; 455 }; 456 457 uart4: serial@1e78f000 { 458 compatible = "ns16550a"; 459 reg = <0x1e78f000 0x20>; 460 reg-shift = <2>; 461 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 462 no-loopback-test; 463 status = "disabled"; 464 }; 465 466 i2c: bus@1e78a000 { 467 compatible = "simple-bus"; 468 #address-cells = <1>; 469 #size-cells = <1>; 470 ranges = <0 0x1e78a000 0x1000>; 471 }; 472 473 uart6: serial@1e790000 { 474 compatible = "ns16550a"; 475 reg = <0x1e790000 0x20>; 476 reg-shift = <2>; 477 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 478 no-loopback-test; 479 status = "disabled"; 480 }; 481 482 uart7: serial@1e790100 { 483 compatible = "ns16550a"; 484 reg = <0x1e790100 0x20>; 485 reg-shift = <2>; 486 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 487 no-loopback-test; 488 status = "disabled"; 489 }; 490 491 uart8: serial@1e790200 { 492 compatible = "ns16550a"; 493 reg = <0x1e790200 0x20>; 494 reg-shift = <2>; 495 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 496 no-loopback-test; 497 status = "disabled"; 498 }; 499 500 uart9: serial@1e790300 { 501 compatible = "ns16550a"; 502 reg = <0x1e790300 0x20>; 503 reg-shift = <2>; 504 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 505 no-loopback-test; 506 status = "disabled"; 507 }; 508 509 uart10: serial@1e790400 { 510 compatible = "ns16550a"; 511 reg = <0x1e790400 0x20>; 512 reg-shift = <2>; 513 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 514 no-loopback-test; 515 status = "disabled"; 516 }; 517 518 uart11: serial@1e790500 { 519 compatible = "ns16550a"; 520 reg = <0x1e790400 0x20>; 521 reg-shift = <2>; 522 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 523 no-loopback-test; 524 status = "disabled"; 525 }; 526 527 uart12: serial@1e790600 { 528 compatible = "ns16550a"; 529 reg = <0x1e790600 0x20>; 530 reg-shift = <2>; 531 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 532 no-loopback-test; 533 status = "disabled"; 534 }; 535 536 uart13: serial@1e790700 { 537 compatible = "ns16550a"; 538 reg = <0x1e790700 0x20>; 539 reg-shift = <2>; 540 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 541 no-loopback-test; 542 status = "disabled"; 543 }; 544 545 546 547 }; 548 549 }; 550 551}; 552 553&i2c { 554 i2cglobal: i2cg@00 { 555 compatible = "aspeed,ast2600-i2c-global", "syscon", "simple-mfd"; 556 reg = <0x0 0x40>; 557 558#if 0 559 new-mode; 560#endif 561 }; 562 563 i2c0: i2c@80 { 564 #address-cells = <1>; 565 #size-cells = <0>; 566 #interrupt-cells = <1>; 567 568 reg = <0x80 0x80 0xC00 0x20>; 569 compatible = "aspeed,ast2600-i2c-bus"; 570 bus-frequency = <100000>; 571 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 572 }; 573 574 i2c1: i2c@100 { 575 #address-cells = <1>; 576 #size-cells = <0>; 577 #interrupt-cells = <1>; 578 579 reg = <0x100 0x80 0xC20 0x20>; 580 compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 581 bus-frequency = <100000>; 582 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 583 }; 584 585 i2c2: i2c@180 { 586 #address-cells = <1>; 587 #size-cells = <0>; 588 #interrupt-cells = <1>; 589 590 reg = <0x180 0x80 0xC40 0x20>; 591 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 592 bus-frequency = <100000>; 593 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 594 }; 595 596 i2c3: i2c@200 { 597 #address-cells = <1>; 598 #size-cells = <0>; 599 #interrupt-cells = <1>; 600 601 reg = <0x200 0x40 0xC60 0x20>; 602 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 603 bus-frequency = <100000>; 604 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 605 }; 606 607 i2c4: i2c@280 { 608 #address-cells = <1>; 609 #size-cells = <0>; 610 #interrupt-cells = <1>; 611 612 reg = <0x280 0x80 0xC80 0x20>; 613 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 614 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 615 bus-frequency = <100000>; 616 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 617 }; 618 619 i2c5: i2c@300 { 620 #address-cells = <1>; 621 #size-cells = <0>; 622 #interrupt-cells = <1>; 623 624 reg = <0x300 0x40 0xCA0 0x20>; 625 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 626 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 627 bus-frequency = <100000>; 628 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 629 }; 630 631 i2c6: i2c@380 { 632 #address-cells = <1>; 633 #size-cells = <0>; 634 #interrupt-cells = <1>; 635 636 reg = <0x380 0x80 0xCC0 0x20>; 637 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 638 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 639 bus-frequency = <100000>; 640 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 641 }; 642 643 i2c7: i2c@400 { 644 #address-cells = <1>; 645 #size-cells = <0>; 646 #interrupt-cells = <1>; 647 648 reg = <0x400 0x80 0xCE0 0x20>; 649 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 650 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 651 bus-frequency = <100000>; 652 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 653 }; 654 655 i2c8: i2c@480 { 656 #address-cells = <1>; 657 #size-cells = <0>; 658 #interrupt-cells = <1>; 659 660 reg = <0x480 0x80 0xD00 0x20>; 661 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 662 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 663 bus-frequency = <100000>; 664 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 665 }; 666 667 i2c9: i2c@500 { 668 #address-cells = <1>; 669 #size-cells = <0>; 670 #interrupt-cells = <1>; 671 672 reg = <0x500 0x80 0xD20 0x20>; 673 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 674 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 675 bus-frequency = <100000>; 676 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 677 status = "disabled"; 678 }; 679 680 i2c10: i2c@580 { 681 #address-cells = <1>; 682 #size-cells = <0>; 683 #interrupt-cells = <1>; 684 685 reg = <0x580 0x80 0xD40 0x20>; 686 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 687 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 688 bus-frequency = <100000>; 689 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 690 status = "disabled"; 691 }; 692 693 i2c11: i2c@600 { 694 #address-cells = <1>; 695 #size-cells = <0>; 696 #interrupt-cells = <1>; 697 698 reg = <0x600 0x80 0xD60 0x20>; 699 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 700 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 701 bus-frequency = <100000>; 702 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 703 status = "disabled"; 704 }; 705 706 i2c12: i2c@680 { 707 #address-cells = <1>; 708 #size-cells = <0>; 709 #interrupt-cells = <1>; 710 711 reg = <0x680 0x80 0xD80 0x20>; 712 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 713 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 714 bus-frequency = <100000>; 715 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 716 status = "disabled"; 717 }; 718 719 i2c13: i2c@700 { 720 #address-cells = <1>; 721 #size-cells = <0>; 722 #interrupt-cells = <1>; 723 724 reg = <0x700 0x80 0xDA0 0x20>; 725 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 726 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 727 bus-frequency = <100000>; 728 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 729 status = "disabled"; 730 }; 731 732 i2c14: i2c@780 { 733 #address-cells = <1>; 734 #size-cells = <0>; 735 #interrupt-cells = <1>; 736 737 reg = <0x780 0x80 0xDC0 0x20>; 738 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 739 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 740 bus-frequency = <100000>; 741 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 742 status = "disabled"; 743 }; 744 745 i2c15: i2c@800 { 746 #address-cells = <1>; 747 #size-cells = <0>; 748 #interrupt-cells = <1>; 749 750 reg = <0x800 0x80 0xDE0 0x20>; 751 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 752 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 753 bus-frequency = <100000>; 754 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 755 status = "disabled"; 756 }; 757 758}; 759 760&pinctrl { 761 pinctrl_acpi_default: acpi_default { 762 function = "ACPI"; 763 groups = "ACPI"; 764 }; 765 766 pinctrl_adc0_default: adc0_default { 767 function = "ADC0"; 768 groups = "ADC0"; 769 }; 770 771 pinctrl_adc1_default: adc1_default { 772 function = "ADC1"; 773 groups = "ADC1"; 774 }; 775 776 pinctrl_adc10_default: adc10_default { 777 function = "ADC10"; 778 groups = "ADC10"; 779 }; 780 781 pinctrl_adc11_default: adc11_default { 782 function = "ADC11"; 783 groups = "ADC11"; 784 }; 785 786 pinctrl_adc12_default: adc12_default { 787 function = "ADC12"; 788 groups = "ADC12"; 789 }; 790 791 pinctrl_adc13_default: adc13_default { 792 function = "ADC13"; 793 groups = "ADC13"; 794 }; 795 796 pinctrl_adc14_default: adc14_default { 797 function = "ADC14"; 798 groups = "ADC14"; 799 }; 800 801 pinctrl_adc15_default: adc15_default { 802 function = "ADC15"; 803 groups = "ADC15"; 804 }; 805 806 pinctrl_adc2_default: adc2_default { 807 function = "ADC2"; 808 groups = "ADC2"; 809 }; 810 811 pinctrl_adc3_default: adc3_default { 812 function = "ADC3"; 813 groups = "ADC3"; 814 }; 815 816 pinctrl_adc4_default: adc4_default { 817 function = "ADC4"; 818 groups = "ADC4"; 819 }; 820 821 pinctrl_adc5_default: adc5_default { 822 function = "ADC5"; 823 groups = "ADC5"; 824 }; 825 826 pinctrl_adc6_default: adc6_default { 827 function = "ADC6"; 828 groups = "ADC6"; 829 }; 830 831 pinctrl_adc7_default: adc7_default { 832 function = "ADC7"; 833 groups = "ADC7"; 834 }; 835 836 pinctrl_adc8_default: adc8_default { 837 function = "ADC8"; 838 groups = "ADC8"; 839 }; 840 841 pinctrl_adc9_default: adc9_default { 842 function = "ADC9"; 843 groups = "ADC9"; 844 }; 845 846 pinctrl_bmcint_default: bmcint_default { 847 function = "BMCINT"; 848 groups = "BMCINT"; 849 }; 850 851 pinctrl_ddcclk_default: ddcclk_default { 852 function = "DDCCLK"; 853 groups = "DDCCLK"; 854 }; 855 856 pinctrl_ddcdat_default: ddcdat_default { 857 function = "DDCDAT"; 858 groups = "DDCDAT"; 859 }; 860 861 pinctrl_espi_default: espi_default { 862 function = "ESPI"; 863 groups = "ESPI"; 864 }; 865 866 pinctrl_fwspics1_default: fwspics1_default { 867 function = "FWSPICS1"; 868 groups = "FWSPICS1"; 869 }; 870 871 pinctrl_fwspics2_default: fwspics2_default { 872 function = "FWSPICS2"; 873 groups = "FWSPICS2"; 874 }; 875 876 pinctrl_gpid0_default: gpid0_default { 877 function = "GPID0"; 878 groups = "GPID0"; 879 }; 880 881 pinctrl_gpid2_default: gpid2_default { 882 function = "GPID2"; 883 groups = "GPID2"; 884 }; 885 886 pinctrl_gpid4_default: gpid4_default { 887 function = "GPID4"; 888 groups = "GPID4"; 889 }; 890 891 pinctrl_gpid6_default: gpid6_default { 892 function = "GPID6"; 893 groups = "GPID6"; 894 }; 895 896 pinctrl_gpie0_default: gpie0_default { 897 function = "GPIE0"; 898 groups = "GPIE0"; 899 }; 900 901 pinctrl_gpie2_default: gpie2_default { 902 function = "GPIE2"; 903 groups = "GPIE2"; 904 }; 905 906 pinctrl_gpie4_default: gpie4_default { 907 function = "GPIE4"; 908 groups = "GPIE4"; 909 }; 910 911 pinctrl_gpie6_default: gpie6_default { 912 function = "GPIE6"; 913 groups = "GPIE6"; 914 }; 915 916 pinctrl_i2c10_default: i2c10_default { 917 function = "I2C10"; 918 groups = "I2C10"; 919 }; 920 921 pinctrl_i2c11_default: i2c11_default { 922 function = "I2C11"; 923 groups = "I2C11"; 924 }; 925 926 pinctrl_i2c12_default: i2c12_default { 927 function = "I2C12"; 928 groups = "I2C12"; 929 }; 930 931 pinctrl_i2c13_default: i2c13_default { 932 function = "I2C13"; 933 groups = "I2C13"; 934 }; 935 936 pinctrl_i2c14_default: i2c14_default { 937 function = "I2C14"; 938 groups = "I2C14"; 939 }; 940 941 pinctrl_i2c3_default: i2c3_default { 942 function = "I2C3"; 943 groups = "I2C3"; 944 }; 945 946 pinctrl_i2c4_default: i2c4_default { 947 function = "I2C4"; 948 groups = "I2C4"; 949 }; 950 951 pinctrl_i2c5_default: i2c5_default { 952 function = "I2C5"; 953 groups = "I2C5"; 954 }; 955 956 pinctrl_i2c6_default: i2c6_default { 957 function = "I2C6"; 958 groups = "I2C6"; 959 }; 960 961 pinctrl_i2c7_default: i2c7_default { 962 function = "I2C7"; 963 groups = "I2C7"; 964 }; 965 966 pinctrl_i2c8_default: i2c8_default { 967 function = "I2C8"; 968 groups = "I2C8"; 969 }; 970 971 pinctrl_i2c9_default: i2c9_default { 972 function = "I2C9"; 973 groups = "I2C9"; 974 }; 975 976 pinctrl_lad0_default: lad0_default { 977 function = "LAD0"; 978 groups = "LAD0"; 979 }; 980 981 pinctrl_lad1_default: lad1_default { 982 function = "LAD1"; 983 groups = "LAD1"; 984 }; 985 986 pinctrl_lad2_default: lad2_default { 987 function = "LAD2"; 988 groups = "LAD2"; 989 }; 990 991 pinctrl_lad3_default: lad3_default { 992 function = "LAD3"; 993 groups = "LAD3"; 994 }; 995 996 pinctrl_lclk_default: lclk_default { 997 function = "LCLK"; 998 groups = "LCLK"; 999 }; 1000 1001 pinctrl_lframe_default: lframe_default { 1002 function = "LFRAME"; 1003 groups = "LFRAME"; 1004 }; 1005 1006 pinctrl_lpchc_default: lpchc_default { 1007 function = "LPCHC"; 1008 groups = "LPCHC"; 1009 }; 1010 1011 pinctrl_lpcpd_default: lpcpd_default { 1012 function = "LPCPD"; 1013 groups = "LPCPD"; 1014 }; 1015 1016 pinctrl_lpcplus_default: lpcplus_default { 1017 function = "LPCPLUS"; 1018 groups = "LPCPLUS"; 1019 }; 1020 1021 pinctrl_lpcpme_default: lpcpme_default { 1022 function = "LPCPME"; 1023 groups = "LPCPME"; 1024 }; 1025 1026 pinctrl_lpcrst_default: lpcrst_default { 1027 function = "LPCRST"; 1028 groups = "LPCRST"; 1029 }; 1030 1031 pinctrl_lpcsmi_default: lpcsmi_default { 1032 function = "LPCSMI"; 1033 groups = "LPCSMI"; 1034 }; 1035 1036 pinctrl_lsirq_default: lsirq_default { 1037 function = "LSIRQ"; 1038 groups = "LSIRQ"; 1039 }; 1040 1041 pinctrl_mac1link_default: mac1link_default { 1042 function = "MAC1LINK"; 1043 groups = "MAC1LINK"; 1044 }; 1045 1046 pinctrl_mac2link_default: mac2link_default { 1047 function = "MAC2LINK"; 1048 groups = "MAC2LINK"; 1049 }; 1050 1051 pinctrl_mac3link_default: mac3link_default { 1052 function = "MAC3LINK"; 1053 groups = "MAC3LINK"; 1054 }; 1055 1056 pinctrl_mac4link_default: mac4link_default { 1057 function = "MAC4LINK"; 1058 groups = "MAC4LINK"; 1059 }; 1060 1061 pinctrl_mdio1_default: mdio1_default { 1062 function = "MDIO1"; 1063 groups = "MDIO1"; 1064 }; 1065 1066 pinctrl_mdio2_default: mdio2_default { 1067 function = "MDIO2"; 1068 groups = "MDIO2"; 1069 }; 1070 1071 pinctrl_mdio3_default: mdio3_default { 1072 function = "MDIO3"; 1073 groups = "MDIO3"; 1074 }; 1075 1076 pinctrl_mdio4_default: mdio4_default { 1077 function = "MDIO4"; 1078 groups = "MDIO4"; 1079 }; 1080 1081 pinctrl_ncts1_default: ncts1_default { 1082 function = "NCTS1"; 1083 groups = "NCTS1"; 1084 }; 1085 1086 pinctrl_ncts2_default: ncts2_default { 1087 function = "NCTS2"; 1088 groups = "NCTS2"; 1089 }; 1090 1091 pinctrl_ncts3_default: ncts3_default { 1092 function = "NCTS3"; 1093 groups = "NCTS3"; 1094 }; 1095 1096 pinctrl_ncts4_default: ncts4_default { 1097 function = "NCTS4"; 1098 groups = "NCTS4"; 1099 }; 1100 1101 pinctrl_ndcd1_default: ndcd1_default { 1102 function = "NDCD1"; 1103 groups = "NDCD1"; 1104 }; 1105 1106 pinctrl_ndcd2_default: ndcd2_default { 1107 function = "NDCD2"; 1108 groups = "NDCD2"; 1109 }; 1110 1111 pinctrl_ndcd3_default: ndcd3_default { 1112 function = "NDCD3"; 1113 groups = "NDCD3"; 1114 }; 1115 1116 pinctrl_ndcd4_default: ndcd4_default { 1117 function = "NDCD4"; 1118 groups = "NDCD4"; 1119 }; 1120 1121 pinctrl_ndsr1_default: ndsr1_default { 1122 function = "NDSR1"; 1123 groups = "NDSR1"; 1124 }; 1125 1126 pinctrl_ndsr2_default: ndsr2_default { 1127 function = "NDSR2"; 1128 groups = "NDSR2"; 1129 }; 1130 1131 pinctrl_ndsr3_default: ndsr3_default { 1132 function = "NDSR3"; 1133 groups = "NDSR3"; 1134 }; 1135 1136 pinctrl_ndsr4_default: ndsr4_default { 1137 function = "NDSR4"; 1138 groups = "NDSR4"; 1139 }; 1140 1141 pinctrl_ndtr1_default: ndtr1_default { 1142 function = "NDTR1"; 1143 groups = "NDTR1"; 1144 }; 1145 1146 pinctrl_ndtr2_default: ndtr2_default { 1147 function = "NDTR2"; 1148 groups = "NDTR2"; 1149 }; 1150 1151 pinctrl_ndtr3_default: ndtr3_default { 1152 function = "NDTR3"; 1153 groups = "NDTR3"; 1154 }; 1155 1156 pinctrl_ndtr4_default: ndtr4_default { 1157 function = "NDTR4"; 1158 groups = "NDTR4"; 1159 }; 1160 1161 pinctrl_nri1_default: nri1_default { 1162 function = "NRI1"; 1163 groups = "NRI1"; 1164 }; 1165 1166 pinctrl_nri2_default: nri2_default { 1167 function = "NRI2"; 1168 groups = "NRI2"; 1169 }; 1170 1171 pinctrl_nri3_default: nri3_default { 1172 function = "NRI3"; 1173 groups = "NRI3"; 1174 }; 1175 1176 pinctrl_nri4_default: nri4_default { 1177 function = "NRI4"; 1178 groups = "NRI4"; 1179 }; 1180 1181 pinctrl_nrts1_default: nrts1_default { 1182 function = "NRTS1"; 1183 groups = "NRTS1"; 1184 }; 1185 1186 pinctrl_nrts2_default: nrts2_default { 1187 function = "NRTS2"; 1188 groups = "NRTS2"; 1189 }; 1190 1191 pinctrl_nrts3_default: nrts3_default { 1192 function = "NRTS3"; 1193 groups = "NRTS3"; 1194 }; 1195 1196 pinctrl_nrts4_default: nrts4_default { 1197 function = "NRTS4"; 1198 groups = "NRTS4"; 1199 }; 1200 1201 pinctrl_oscclk_default: oscclk_default { 1202 function = "OSCCLK"; 1203 groups = "OSCCLK"; 1204 }; 1205 1206 pinctrl_pewake_default: pewake_default { 1207 function = "PEWAKE"; 1208 groups = "PEWAKE"; 1209 }; 1210 1211 pinctrl_pnor_default: pnor_default { 1212 function = "PNOR"; 1213 groups = "PNOR"; 1214 }; 1215 1216 pinctrl_pwm0_default: pwm0_default { 1217 function = "PWM0"; 1218 groups = "PWM0"; 1219 }; 1220 1221 pinctrl_pwm1_default: pwm1_default { 1222 function = "PWM1"; 1223 groups = "PWM1"; 1224 }; 1225 1226 pinctrl_pwm2_default: pwm2_default { 1227 function = "PWM2"; 1228 groups = "PWM2"; 1229 }; 1230 1231 pinctrl_pwm3_default: pwm3_default { 1232 function = "PWM3"; 1233 groups = "PWM3"; 1234 }; 1235 1236 pinctrl_pwm4_default: pwm4_default { 1237 function = "PWM4"; 1238 groups = "PWM4"; 1239 }; 1240 1241 pinctrl_pwm5_default: pwm5_default { 1242 function = "PWM5"; 1243 groups = "PWM5"; 1244 }; 1245 1246 pinctrl_pwm6_default: pwm6_default { 1247 function = "PWM6"; 1248 groups = "PWM6"; 1249 }; 1250 1251 pinctrl_pwm7_default: pwm7_default { 1252 function = "PWM7"; 1253 groups = "PWM7"; 1254 }; 1255 1256 pinctrl_rgmii1_default: rgmii1_default { 1257 function = "RGMII1"; 1258 groups = "RGMII1"; 1259 }; 1260 1261 pinctrl_rgmii2_default: rgmii2_default { 1262 function = "RGMII2"; 1263 groups = "RGMII2"; 1264 }; 1265 1266 pinctrl_rmii1_default: rmii1_default { 1267 function = "RMII1"; 1268 groups = "RMII1"; 1269 }; 1270 1271 pinctrl_rmii2_default: rmii2_default { 1272 function = "RMII2"; 1273 groups = "RMII2"; 1274 }; 1275 1276 pinctrl_rxd1_default: rxd1_default { 1277 function = "RXD1"; 1278 groups = "RXD1"; 1279 }; 1280 1281 pinctrl_rxd2_default: rxd2_default { 1282 function = "RXD2"; 1283 groups = "RXD2"; 1284 }; 1285 1286 pinctrl_rxd3_default: rxd3_default { 1287 function = "RXD3"; 1288 groups = "RXD3"; 1289 }; 1290 1291 pinctrl_rxd4_default: rxd4_default { 1292 function = "RXD4"; 1293 groups = "RXD4"; 1294 }; 1295 1296 pinctrl_salt1_default: salt1_default { 1297 function = "SALT1"; 1298 groups = "SALT1"; 1299 }; 1300 1301 pinctrl_salt10_default: salt10_default { 1302 function = "SALT10"; 1303 groups = "SALT10"; 1304 }; 1305 1306 pinctrl_salt11_default: salt11_default { 1307 function = "SALT11"; 1308 groups = "SALT11"; 1309 }; 1310 1311 pinctrl_salt12_default: salt12_default { 1312 function = "SALT12"; 1313 groups = "SALT12"; 1314 }; 1315 1316 pinctrl_salt13_default: salt13_default { 1317 function = "SALT13"; 1318 groups = "SALT13"; 1319 }; 1320 1321 pinctrl_salt14_default: salt14_default { 1322 function = "SALT14"; 1323 groups = "SALT14"; 1324 }; 1325 1326 pinctrl_salt2_default: salt2_default { 1327 function = "SALT2"; 1328 groups = "SALT2"; 1329 }; 1330 1331 pinctrl_salt3_default: salt3_default { 1332 function = "SALT3"; 1333 groups = "SALT3"; 1334 }; 1335 1336 pinctrl_salt4_default: salt4_default { 1337 function = "SALT4"; 1338 groups = "SALT4"; 1339 }; 1340 1341 pinctrl_salt5_default: salt5_default { 1342 function = "SALT5"; 1343 groups = "SALT5"; 1344 }; 1345 1346 pinctrl_salt6_default: salt6_default { 1347 function = "SALT6"; 1348 groups = "SALT6"; 1349 }; 1350 1351 pinctrl_salt7_default: salt7_default { 1352 function = "SALT7"; 1353 groups = "SALT7"; 1354 }; 1355 1356 pinctrl_salt8_default: salt8_default { 1357 function = "SALT8"; 1358 groups = "SALT8"; 1359 }; 1360 1361 pinctrl_salt9_default: salt9_default { 1362 function = "SALT9"; 1363 groups = "SALT9"; 1364 }; 1365 1366 pinctrl_scl1_default: scl1_default { 1367 function = "SCL1"; 1368 groups = "SCL1"; 1369 }; 1370 1371 pinctrl_scl2_default: scl2_default { 1372 function = "SCL2"; 1373 groups = "SCL2"; 1374 }; 1375 1376 pinctrl_sd1_default: sd1_default { 1377 function = "SD1"; 1378 groups = "SD1"; 1379 }; 1380 1381 pinctrl_sd2_default: sd2_default { 1382 function = "SD2"; 1383 groups = "SD2"; 1384 }; 1385 1386 pinctrl_sda1_default: sda1_default { 1387 function = "SDA1"; 1388 groups = "SDA1"; 1389 }; 1390 1391 pinctrl_sda2_default: sda2_default { 1392 function = "SDA2"; 1393 groups = "SDA2"; 1394 }; 1395 1396 pinctrl_sgps1_default: sgps1_default { 1397 function = "SGPS1"; 1398 groups = "SGPS1"; 1399 }; 1400 1401 pinctrl_sgps2_default: sgps2_default { 1402 function = "SGPS2"; 1403 groups = "SGPS2"; 1404 }; 1405 1406 pinctrl_sioonctrl_default: sioonctrl_default { 1407 function = "SIOONCTRL"; 1408 groups = "SIOONCTRL"; 1409 }; 1410 1411 pinctrl_siopbi_default: siopbi_default { 1412 function = "SIOPBI"; 1413 groups = "SIOPBI"; 1414 }; 1415 1416 pinctrl_siopbo_default: siopbo_default { 1417 function = "SIOPBO"; 1418 groups = "SIOPBO"; 1419 }; 1420 1421 pinctrl_siopwreq_default: siopwreq_default { 1422 function = "SIOPWREQ"; 1423 groups = "SIOPWREQ"; 1424 }; 1425 1426 pinctrl_siopwrgd_default: siopwrgd_default { 1427 function = "SIOPWRGD"; 1428 groups = "SIOPWRGD"; 1429 }; 1430 1431 pinctrl_sios3_default: sios3_default { 1432 function = "SIOS3"; 1433 groups = "SIOS3"; 1434 }; 1435 1436 pinctrl_sios5_default: sios5_default { 1437 function = "SIOS5"; 1438 groups = "SIOS5"; 1439 }; 1440 1441 pinctrl_siosci_default: siosci_default { 1442 function = "SIOSCI"; 1443 groups = "SIOSCI"; 1444 }; 1445 1446 pinctrl_spi1_default: spi1_default { 1447 function = "SPI1"; 1448 groups = "SPI1"; 1449 }; 1450 1451 pinctrl_spi1cs1_default: spi1cs1_default { 1452 function = "SPI1CS1"; 1453 groups = "SPI1CS1"; 1454 }; 1455 1456 pinctrl_spi1debug_default: spi1debug_default { 1457 function = "SPI1DEBUG"; 1458 groups = "SPI1DEBUG"; 1459 }; 1460 1461 pinctrl_spi1passthru_default: spi1passthru_default { 1462 function = "SPI1PASSTHRU"; 1463 groups = "SPI1PASSTHRU"; 1464 }; 1465 1466 pinctrl_spi2ck_default: spi2ck_default { 1467 function = "SPI2CK"; 1468 groups = "SPI2CK"; 1469 }; 1470 1471 pinctrl_spi2cs0_default: spi2cs0_default { 1472 function = "SPI2CS0"; 1473 groups = "SPI2CS0"; 1474 }; 1475 1476 pinctrl_spi2cs1_default: spi2cs1_default { 1477 function = "SPI2CS1"; 1478 groups = "SPI2CS1"; 1479 }; 1480 1481 pinctrl_spi2miso_default: spi2miso_default { 1482 function = "SPI2MISO"; 1483 groups = "SPI2MISO"; 1484 }; 1485 1486 pinctrl_spi2mosi_default: spi2mosi_default { 1487 function = "SPI2MOSI"; 1488 groups = "SPI2MOSI"; 1489 }; 1490 1491 pinctrl_timer3_default: timer3_default { 1492 function = "TIMER3"; 1493 groups = "TIMER3"; 1494 }; 1495 1496 pinctrl_timer4_default: timer4_default { 1497 function = "TIMER4"; 1498 groups = "TIMER4"; 1499 }; 1500 1501 pinctrl_timer5_default: timer5_default { 1502 function = "TIMER5"; 1503 groups = "TIMER5"; 1504 }; 1505 1506 pinctrl_timer6_default: timer6_default { 1507 function = "TIMER6"; 1508 groups = "TIMER6"; 1509 }; 1510 1511 pinctrl_timer7_default: timer7_default { 1512 function = "TIMER7"; 1513 groups = "TIMER7"; 1514 }; 1515 1516 pinctrl_timer8_default: timer8_default { 1517 function = "TIMER8"; 1518 groups = "TIMER8"; 1519 }; 1520 1521 pinctrl_txd1_default: txd1_default { 1522 function = "TXD1"; 1523 groups = "TXD1"; 1524 }; 1525 1526 pinctrl_txd2_default: txd2_default { 1527 function = "TXD2"; 1528 groups = "TXD2"; 1529 }; 1530 1531 pinctrl_txd3_default: txd3_default { 1532 function = "TXD3"; 1533 groups = "TXD3"; 1534 }; 1535 1536 pinctrl_txd4_default: txd4_default { 1537 function = "TXD4"; 1538 groups = "TXD4"; 1539 }; 1540 1541 pinctrl_uart6_default: uart6_default { 1542 function = "UART6"; 1543 groups = "UART6"; 1544 }; 1545 1546 pinctrl_usbcki_default: usbcki_default { 1547 function = "USBCKI"; 1548 groups = "USBCKI"; 1549 }; 1550 1551 pinctrl_usb2ah_default: usb2ah_default { 1552 function = "USB2AH"; 1553 groups = "USB2AH"; 1554 }; 1555 1556 pinctrl_usb11bhid_default: usb11bhid_default { 1557 function = "USB11BHID"; 1558 groups = "USB11BHID"; 1559 }; 1560 1561 pinctrl_usb2bh_default: usb2bh_default { 1562 function = "USB2BH"; 1563 groups = "USB2BH"; 1564 }; 1565 1566 pinctrl_vgabiosrom_default: vgabiosrom_default { 1567 function = "VGABIOSROM"; 1568 groups = "VGABIOSROM"; 1569 }; 1570 1571 pinctrl_vgahs_default: vgahs_default { 1572 function = "VGAHS"; 1573 groups = "VGAHS"; 1574 }; 1575 1576 pinctrl_vgavs_default: vgavs_default { 1577 function = "VGAVS"; 1578 groups = "VGAVS"; 1579 }; 1580 1581 pinctrl_vpi24_default: vpi24_default { 1582 function = "VPI24"; 1583 groups = "VPI24"; 1584 }; 1585 1586 pinctrl_vpo_default: vpo_default { 1587 function = "VPO"; 1588 groups = "VPO"; 1589 }; 1590 1591 pinctrl_wdtrst1_default: wdtrst1_default { 1592 function = "WDTRST1"; 1593 groups = "WDTRST1"; 1594 }; 1595 1596 pinctrl_wdtrst2_default: wdtrst2_default { 1597 function = "WDTRST2"; 1598 groups = "WDTRST2"; 1599 }; 1600}; 1601