1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * (C) Copyright 2016 Google, Inc 4 */ 5 6 #include <common.h> 7 #include <clk-uclass.h> 8 #include <dm.h> 9 #include <asm/io.h> 10 #include <asm/arch/scu_ast2500.h> 11 #include <dm/lists.h> 12 #include <dt-bindings/clock/ast2500-scu.h> 13 14 /* 15 * MAC Clock Delay settings, taken from Aspeed SDK 16 */ 17 #define RGMII_TXCLK_ODLY 8 18 #define RMII_RXCLK_IDLY 2 19 20 /* 21 * TGMII Clock Duty constants, taken from Aspeed SDK 22 */ 23 #define RGMII2_TXCK_DUTY 0x66 24 #define RGMII1_TXCK_DUTY 0x64 25 26 #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000) 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 /* 31 * Clock divider/multiplier configuration struct. 32 * For H-PLL and M-PLL the formula is 33 * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) 34 * M - Numerator 35 * N - Denumerator 36 * P - Post Divider 37 * They have the same layout in their control register. 38 * 39 * D-PLL and D2-PLL have extra divider (OD + 1), which is not 40 * yet needed and ignored by clock configurations. 41 */ 42 struct ast2500_div_config { 43 unsigned int num; 44 unsigned int denum; 45 unsigned int post_div; 46 }; 47 48 /* 49 * Get the rate of the M-PLL clock from input clock frequency and 50 * the value of the M-PLL Parameter Register. 51 */ 52 static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg) 53 { 54 const ulong num = (mpll_reg & SCU_MPLL_NUM_MASK) >> SCU_MPLL_NUM_SHIFT; 55 const ulong denum = (mpll_reg & SCU_MPLL_DENUM_MASK) 56 >> SCU_MPLL_DENUM_SHIFT; 57 const ulong post_div = (mpll_reg & SCU_MPLL_POST_MASK) 58 >> SCU_MPLL_POST_SHIFT; 59 60 return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1); 61 } 62 63 /* 64 * Get the rate of the H-PLL clock from input clock frequency and 65 * the value of the H-PLL Parameter Register. 66 */ 67 static ulong ast2500_get_hpll_rate(ulong clkin, u32 hpll_reg) 68 { 69 const ulong num = (hpll_reg & SCU_HPLL_NUM_MASK) >> SCU_HPLL_NUM_SHIFT; 70 const ulong denum = (hpll_reg & SCU_HPLL_DENUM_MASK) 71 >> SCU_HPLL_DENUM_SHIFT; 72 const ulong post_div = (hpll_reg & SCU_HPLL_POST_MASK) 73 >> SCU_HPLL_POST_SHIFT; 74 75 return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1); 76 } 77 78 static ulong ast2500_get_clkin(struct ast2500_scu *scu) 79 { 80 return readl(&scu->hwstrap) & SCU_HWSTRAP_CLKIN_25MHZ 81 ? 25 * 1000 * 1000 : 24 * 1000 * 1000; 82 } 83 84 /** 85 * Get current rate or uart clock 86 * 87 * @scu SCU registers 88 * @uart_index UART index, 1-5 89 * 90 * @return current setting for uart clock rate 91 */ 92 static ulong ast2500_get_uart_clk_rate(struct ast2500_scu *scu, int uart_index) 93 { 94 /* 95 * ast2500 datasheet is very confusing when it comes to UART clocks, 96 * especially when CLKIN = 25 MHz. The settings are in 97 * different registers and it is unclear how they interact. 98 * 99 * This has only been tested with default settings and CLKIN = 24 MHz. 100 */ 101 ulong uart_clkin; 102 103 if (readl(&scu->misc_ctrl2) & 104 (1 << (uart_index - 1 + SCU_MISC2_UARTCLK_SHIFT))) 105 uart_clkin = 192 * 1000 * 1000; 106 else 107 uart_clkin = 24 * 1000 * 1000; 108 109 if (readl(&scu->misc_ctrl1) & SCU_MISC_UARTCLK_DIV13) 110 uart_clkin /= 13; 111 112 return uart_clkin; 113 } 114 115 static ulong ast2500_clk_get_rate(struct clk *clk) 116 { 117 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev); 118 ulong clkin = ast2500_get_clkin(priv->scu); 119 ulong rate; 120 121 switch (clk->id) { 122 case PLL_HPLL: 123 case ARMCLK: 124 /* 125 * This ignores dynamic/static slowdown of ARMCLK and may 126 * be inaccurate. 127 */ 128 rate = ast2500_get_hpll_rate(clkin, 129 readl(&priv->scu->h_pll_param)); 130 break; 131 case MCLK_DDR: 132 rate = ast2500_get_mpll_rate(clkin, 133 readl(&priv->scu->m_pll_param)); 134 break; 135 case BCLK_PCLK: 136 { 137 ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1) 138 & SCU_PCLK_DIV_MASK) 139 >> SCU_PCLK_DIV_SHIFT); 140 rate = ast2500_get_hpll_rate(clkin, 141 readl(&priv-> 142 scu->h_pll_param)); 143 rate = rate / apb_div; 144 } 145 break; 146 case BCLK_HCLK: 147 { 148 ulong ahb_div = 1 + ((readl(&priv->scu->hwstrap) 149 & SCU_HWSTRAP_AXIAHB_DIV_MASK) 150 >> SCU_HWSTRAP_AXIAHB_DIV_SHIFT); 151 ulong axi_div = 2; 152 153 rate = ast2500_get_hpll_rate( 154 clkin, readl(&priv->scu->h_pll_param)); 155 rate = rate / axi_div / ahb_div; 156 } 157 break; 158 case PCLK_UART1: 159 rate = ast2500_get_uart_clk_rate(priv->scu, 1); 160 break; 161 case PCLK_UART2: 162 rate = ast2500_get_uart_clk_rate(priv->scu, 2); 163 break; 164 case PCLK_UART3: 165 rate = ast2500_get_uart_clk_rate(priv->scu, 3); 166 break; 167 case PCLK_UART4: 168 rate = ast2500_get_uart_clk_rate(priv->scu, 4); 169 break; 170 case PCLK_UART5: 171 rate = ast2500_get_uart_clk_rate(priv->scu, 5); 172 break; 173 default: 174 return -ENOENT; 175 } 176 177 return rate; 178 } 179 180 struct ast2500_clock_config { 181 ulong input_rate; 182 ulong rate; 183 struct ast2500_div_config cfg; 184 }; 185 186 static const struct ast2500_clock_config ast2500_clock_config_defaults[] = { 187 { 24000000, 250000000, { .num = 124, .denum = 1, .post_div = 5 } }, 188 }; 189 190 static bool ast2500_get_clock_config_default(ulong input_rate, 191 ulong requested_rate, 192 struct ast2500_div_config *cfg) 193 { 194 int i; 195 196 for (i = 0; i < ARRAY_SIZE(ast2500_clock_config_defaults); i++) { 197 const struct ast2500_clock_config *default_cfg = 198 &ast2500_clock_config_defaults[i]; 199 if (default_cfg->input_rate == input_rate && 200 default_cfg->rate == requested_rate) { 201 *cfg = default_cfg->cfg; 202 return true; 203 } 204 } 205 206 return false; 207 } 208 209 /* 210 * @input_rate - the rate of input clock in Hz 211 * @requested_rate - desired output rate in Hz 212 * @div - this is an IN/OUT parameter, at input all fields of the config 213 * need to be set to their maximum allowed values. 214 * The result (the best config we could find), would also be returned 215 * in this structure. 216 * 217 * @return The clock rate, when the resulting div_config is used. 218 */ 219 static ulong ast2500_calc_clock_config(ulong input_rate, ulong requested_rate, 220 struct ast2500_div_config *cfg) 221 { 222 /* 223 * The assumption is that kHz precision is good enough and 224 * also enough to avoid overflow when multiplying. 225 */ 226 const ulong input_rate_khz = input_rate / 1000; 227 const ulong rate_khz = requested_rate / 1000; 228 const struct ast2500_div_config max_vals = *cfg; 229 struct ast2500_div_config it = { 0, 0, 0 }; 230 ulong delta = rate_khz; 231 ulong new_rate_khz = 0; 232 233 /* 234 * Look for a well known frequency first. 235 */ 236 if (ast2500_get_clock_config_default(input_rate, requested_rate, cfg)) 237 return requested_rate; 238 239 for (; it.denum <= max_vals.denum; ++it.denum) { 240 for (it.post_div = 0; it.post_div <= max_vals.post_div; 241 ++it.post_div) { 242 it.num = (rate_khz * (it.post_div + 1) / input_rate_khz) 243 * (it.denum + 1); 244 if (it.num > max_vals.num) 245 continue; 246 247 new_rate_khz = (input_rate_khz 248 * ((it.num + 1) / (it.denum + 1))) 249 / (it.post_div + 1); 250 251 /* Keep the rate below requested one. */ 252 if (new_rate_khz > rate_khz) 253 continue; 254 255 if (new_rate_khz - rate_khz < delta) { 256 delta = new_rate_khz - rate_khz; 257 *cfg = it; 258 if (delta == 0) 259 return new_rate_khz * 1000; 260 } 261 } 262 } 263 264 return new_rate_khz * 1000; 265 } 266 267 static ulong ast2500_configure_ddr(struct ast2500_scu *scu, ulong rate) 268 { 269 ulong clkin = ast2500_get_clkin(scu); 270 u32 mpll_reg; 271 struct ast2500_div_config div_cfg = { 272 .num = (SCU_MPLL_NUM_MASK >> SCU_MPLL_NUM_SHIFT), 273 .denum = (SCU_MPLL_DENUM_MASK >> SCU_MPLL_DENUM_SHIFT), 274 .post_div = (SCU_MPLL_POST_MASK >> SCU_MPLL_POST_SHIFT), 275 }; 276 277 ast2500_calc_clock_config(clkin, rate, &div_cfg); 278 279 mpll_reg = readl(&scu->m_pll_param); 280 mpll_reg &= ~(SCU_MPLL_POST_MASK | SCU_MPLL_NUM_MASK 281 | SCU_MPLL_DENUM_MASK); 282 mpll_reg |= (div_cfg.post_div << SCU_MPLL_POST_SHIFT) 283 | (div_cfg.num << SCU_MPLL_NUM_SHIFT) 284 | (div_cfg.denum << SCU_MPLL_DENUM_SHIFT); 285 286 ast_scu_unlock(scu); 287 writel(mpll_reg, &scu->m_pll_param); 288 ast_scu_lock(scu); 289 290 return ast2500_get_mpll_rate(clkin, mpll_reg); 291 } 292 293 static ulong ast2500_configure_mac(struct ast2500_scu *scu, int index) 294 { 295 ulong clkin = ast2500_get_clkin(scu); 296 ulong hpll_rate = ast2500_get_hpll_rate(clkin, 297 readl(&scu->h_pll_param)); 298 ulong required_rate; 299 u32 hwstrap; 300 u32 divisor; 301 u32 reset_bit; 302 u32 clkstop_bit; 303 304 /* 305 * According to data sheet, for 10/100 mode the MAC clock frequency 306 * should be at least 25MHz and for 1000 mode at least 100MHz 307 */ 308 hwstrap = readl(&scu->hwstrap); 309 if (hwstrap & (SCU_HWSTRAP_MAC1_RGMII | SCU_HWSTRAP_MAC2_RGMII)) 310 required_rate = 100 * 1000 * 1000; 311 else 312 required_rate = 25 * 1000 * 1000; 313 314 divisor = hpll_rate / required_rate; 315 316 if (divisor < 4) { 317 /* Clock can't run fast enough, but let's try anyway */ 318 debug("MAC clock too slow\n"); 319 divisor = 4; 320 } else if (divisor > 16) { 321 /* Can't slow down the clock enough, but let's try anyway */ 322 debug("MAC clock too fast\n"); 323 divisor = 16; 324 } 325 326 switch (index) { 327 case 1: 328 reset_bit = SCU_SYSRESET_MAC1; 329 clkstop_bit = SCU_CLKSTOP_MAC1; 330 break; 331 case 2: 332 reset_bit = SCU_SYSRESET_MAC2; 333 clkstop_bit = SCU_CLKSTOP_MAC2; 334 break; 335 default: 336 return -EINVAL; 337 } 338 339 ast_scu_unlock(scu); 340 clrsetbits_le32(&scu->clk_sel1, SCU_MACCLK_MASK, 341 ((divisor - 2) / 2) << SCU_MACCLK_SHIFT); 342 343 /* 344 * Disable MAC, start its clock and re-enable it. 345 * The procedure and the delays (100us & 10ms) are 346 * specified in the datasheet. 347 */ 348 setbits_le32(&scu->sysreset_ctrl1, reset_bit); 349 udelay(100); 350 clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit); 351 mdelay(10); 352 clrbits_le32(&scu->sysreset_ctrl1, reset_bit); 353 354 writel((RGMII2_TXCK_DUTY << SCU_CLKDUTY_RGMII2TXCK_SHIFT) 355 | (RGMII1_TXCK_DUTY << SCU_CLKDUTY_RGMII1TXCK_SHIFT), 356 &scu->clk_duty_sel); 357 358 ast_scu_lock(scu); 359 360 return required_rate; 361 } 362 363 static ulong ast2500_configure_d2pll(struct ast2500_scu *scu, ulong rate) 364 { 365 /* 366 * The values and the meaning of the next three 367 * parameters are undocumented. Taken from Aspeed SDK. 368 * 369 * TODO(clg@kaod.org): the SIP and SIC values depend on the 370 * Numerator value 371 */ 372 const u32 d2_pll_ext_param = 0x2c; 373 const u32 d2_pll_sip = 0x11; 374 const u32 d2_pll_sic = 0x18; 375 u32 clk_delay_settings = 376 (RMII_RXCLK_IDLY << SCU_MICDS_MAC1RMII_RDLY_SHIFT) 377 | (RMII_RXCLK_IDLY << SCU_MICDS_MAC2RMII_RDLY_SHIFT) 378 | (RGMII_TXCLK_ODLY << SCU_MICDS_MAC1RGMII_TXDLY_SHIFT) 379 | (RGMII_TXCLK_ODLY << SCU_MICDS_MAC2RGMII_TXDLY_SHIFT); 380 struct ast2500_div_config div_cfg = { 381 .num = SCU_D2PLL_NUM_MASK >> SCU_D2PLL_NUM_SHIFT, 382 .denum = SCU_D2PLL_DENUM_MASK >> SCU_D2PLL_DENUM_SHIFT, 383 .post_div = SCU_D2PLL_POST_MASK >> SCU_D2PLL_POST_SHIFT, 384 }; 385 ulong clkin = ast2500_get_clkin(scu); 386 ulong new_rate; 387 388 ast_scu_unlock(scu); 389 writel((d2_pll_ext_param << SCU_D2PLL_EXT1_PARAM_SHIFT) 390 | SCU_D2PLL_EXT1_OFF 391 | SCU_D2PLL_EXT1_RESET, &scu->d2_pll_ext_param[0]); 392 393 /* 394 * Select USB2.0 port1 PHY clock as a clock source for GCRT. 395 * This would disconnect it from D2-PLL. 396 */ 397 clrsetbits_le32(&scu->misc_ctrl1, SCU_MISC_D2PLL_OFF, 398 SCU_MISC_GCRT_USB20CLK); 399 400 new_rate = ast2500_calc_clock_config(clkin, rate, &div_cfg); 401 writel((d2_pll_sip << SCU_D2PLL_SIP_SHIFT) 402 | (d2_pll_sic << SCU_D2PLL_SIC_SHIFT) 403 | (div_cfg.num << SCU_D2PLL_NUM_SHIFT) 404 | (div_cfg.denum << SCU_D2PLL_DENUM_SHIFT) 405 | (div_cfg.post_div << SCU_D2PLL_POST_SHIFT), 406 &scu->d2_pll_param); 407 408 clrbits_le32(&scu->d2_pll_ext_param[0], 409 SCU_D2PLL_EXT1_OFF | SCU_D2PLL_EXT1_RESET); 410 411 clrsetbits_le32(&scu->misc_ctrl2, 412 SCU_MISC2_RGMII_HPLL | SCU_MISC2_RMII_MPLL 413 | SCU_MISC2_RGMII_CLKDIV_MASK | 414 SCU_MISC2_RMII_CLKDIV_MASK, 415 (4 << SCU_MISC2_RMII_CLKDIV_SHIFT)); 416 417 writel(clk_delay_settings | SCU_MICDS_RGMIIPLL, &scu->mac_clk_delay); 418 writel(clk_delay_settings, &scu->mac_clk_delay_100M); 419 writel(clk_delay_settings, &scu->mac_clk_delay_10M); 420 421 ast_scu_lock(scu); 422 423 return new_rate; 424 } 425 426 static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate) 427 { 428 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev); 429 430 ulong new_rate; 431 switch (clk->id) { 432 case PLL_MPLL: 433 case MCLK_DDR: 434 new_rate = ast2500_configure_ddr(priv->scu, rate); 435 break; 436 case PLL_D2PLL: 437 new_rate = ast2500_configure_d2pll(priv->scu, rate); 438 break; 439 default: 440 return -ENOENT; 441 } 442 443 return new_rate; 444 } 445 446 static int ast2500_clk_enable(struct clk *clk) 447 { 448 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev); 449 450 switch (clk->id) { 451 /* 452 * For MAC clocks the clock rate is 453 * configured based on whether RGMII or RMII mode has been selected 454 * through hardware strapping. 455 */ 456 case PCLK_MAC1: 457 ast2500_configure_mac(priv->scu, 1); 458 break; 459 case PCLK_MAC2: 460 ast2500_configure_mac(priv->scu, 2); 461 break; 462 case PLL_D2PLL: 463 ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE); 464 break; 465 default: 466 return -ENOENT; 467 } 468 469 return 0; 470 } 471 472 struct clk_ops ast2500_clk_ops = { 473 .get_rate = ast2500_clk_get_rate, 474 .set_rate = ast2500_clk_set_rate, 475 .enable = ast2500_clk_enable, 476 }; 477 478 static int ast2500_clk_probe(struct udevice *dev) 479 { 480 struct ast2500_clk_priv *priv = dev_get_priv(dev); 481 482 priv->scu = devfdt_get_addr_ptr(dev); 483 if (IS_ERR(priv->scu)) 484 return PTR_ERR(priv->scu); 485 486 return 0; 487 } 488 489 static int ast2500_clk_bind(struct udevice *dev) 490 { 491 int ret; 492 493 /* The reset driver does not have a device node, so bind it here */ 494 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); 495 if (ret) 496 debug("Warning: No reset driver: ret=%d\n", ret); 497 498 return 0; 499 } 500 501 static const struct udevice_id ast2500_clk_ids[] = { 502 { .compatible = "aspeed,ast2500-scu" }, 503 { } 504 }; 505 506 U_BOOT_DRIVER(aspeed_ast2500_scu) = { 507 .name = "aspeed_ast2500_scu", 508 .id = UCLASS_CLK, 509 .of_match = ast2500_clk_ids, 510 .priv_auto_alloc_size = sizeof(struct ast2500_clk_priv), 511 .ops = &ast2500_clk_ops, 512 .bind = ast2500_clk_bind, 513 .probe = ast2500_clk_probe, 514 }; 515