1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 2 /* 3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 4 */ 5 6 #include <common.h> 7 #include <clk-uclass.h> 8 #include <div64.h> 9 #include <dm.h> 10 #include <regmap.h> 11 #include <spl.h> 12 #include <syscon.h> 13 #include <linux/io.h> 14 #include <linux/iopoll.h> 15 #include <dt-bindings/clock/stm32mp1-clks.h> 16 #include <dt-bindings/clock/stm32mp1-clksrc.h> 17 18 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) 19 /* activate clock tree initialization in the driver */ 20 #define STM32MP1_CLOCK_TREE_INIT 21 #endif 22 23 #define MAX_HSI_HZ 64000000 24 25 /* TIMEOUT */ 26 #define TIMEOUT_200MS 200000 27 #define TIMEOUT_1S 1000000 28 29 /* STGEN registers */ 30 #define STGENC_CNTCR 0x00 31 #define STGENC_CNTSR 0x04 32 #define STGENC_CNTCVL 0x08 33 #define STGENC_CNTCVU 0x0C 34 #define STGENC_CNTFID0 0x20 35 36 #define STGENC_CNTCR_EN BIT(0) 37 38 /* RCC registers */ 39 #define RCC_OCENSETR 0x0C 40 #define RCC_OCENCLRR 0x10 41 #define RCC_HSICFGR 0x18 42 #define RCC_MPCKSELR 0x20 43 #define RCC_ASSCKSELR 0x24 44 #define RCC_RCK12SELR 0x28 45 #define RCC_MPCKDIVR 0x2C 46 #define RCC_AXIDIVR 0x30 47 #define RCC_APB4DIVR 0x3C 48 #define RCC_APB5DIVR 0x40 49 #define RCC_RTCDIVR 0x44 50 #define RCC_MSSCKSELR 0x48 51 #define RCC_PLL1CR 0x80 52 #define RCC_PLL1CFGR1 0x84 53 #define RCC_PLL1CFGR2 0x88 54 #define RCC_PLL1FRACR 0x8C 55 #define RCC_PLL1CSGR 0x90 56 #define RCC_PLL2CR 0x94 57 #define RCC_PLL2CFGR1 0x98 58 #define RCC_PLL2CFGR2 0x9C 59 #define RCC_PLL2FRACR 0xA0 60 #define RCC_PLL2CSGR 0xA4 61 #define RCC_I2C46CKSELR 0xC0 62 #define RCC_CPERCKSELR 0xD0 63 #define RCC_STGENCKSELR 0xD4 64 #define RCC_DDRITFCR 0xD8 65 #define RCC_BDCR 0x140 66 #define RCC_RDLSICR 0x144 67 #define RCC_MP_APB4ENSETR 0x200 68 #define RCC_MP_APB5ENSETR 0x208 69 #define RCC_MP_AHB5ENSETR 0x210 70 #define RCC_MP_AHB6ENSETR 0x218 71 #define RCC_OCRDYR 0x808 72 #define RCC_DBGCFGR 0x80C 73 #define RCC_RCK3SELR 0x820 74 #define RCC_RCK4SELR 0x824 75 #define RCC_MCUDIVR 0x830 76 #define RCC_APB1DIVR 0x834 77 #define RCC_APB2DIVR 0x838 78 #define RCC_APB3DIVR 0x83C 79 #define RCC_PLL3CR 0x880 80 #define RCC_PLL3CFGR1 0x884 81 #define RCC_PLL3CFGR2 0x888 82 #define RCC_PLL3FRACR 0x88C 83 #define RCC_PLL3CSGR 0x890 84 #define RCC_PLL4CR 0x894 85 #define RCC_PLL4CFGR1 0x898 86 #define RCC_PLL4CFGR2 0x89C 87 #define RCC_PLL4FRACR 0x8A0 88 #define RCC_PLL4CSGR 0x8A4 89 #define RCC_I2C12CKSELR 0x8C0 90 #define RCC_I2C35CKSELR 0x8C4 91 #define RCC_UART6CKSELR 0x8E4 92 #define RCC_UART24CKSELR 0x8E8 93 #define RCC_UART35CKSELR 0x8EC 94 #define RCC_UART78CKSELR 0x8F0 95 #define RCC_SDMMC12CKSELR 0x8F4 96 #define RCC_SDMMC3CKSELR 0x8F8 97 #define RCC_ETHCKSELR 0x8FC 98 #define RCC_QSPICKSELR 0x900 99 #define RCC_FMCCKSELR 0x904 100 #define RCC_USBCKSELR 0x91C 101 #define RCC_DSICKSELR 0x924 102 #define RCC_ADCCKSELR 0x928 103 #define RCC_MP_APB1ENSETR 0xA00 104 #define RCC_MP_APB2ENSETR 0XA08 105 #define RCC_MP_APB3ENSETR 0xA10 106 #define RCC_MP_AHB2ENSETR 0xA18 107 #define RCC_MP_AHB3ENSETR 0xA20 108 #define RCC_MP_AHB4ENSETR 0xA28 109 110 /* used for most of SELR register */ 111 #define RCC_SELR_SRC_MASK GENMASK(2, 0) 112 #define RCC_SELR_SRCRDY BIT(31) 113 114 /* Values of RCC_MPCKSELR register */ 115 #define RCC_MPCKSELR_HSI 0 116 #define RCC_MPCKSELR_HSE 1 117 #define RCC_MPCKSELR_PLL 2 118 #define RCC_MPCKSELR_PLL_MPUDIV 3 119 120 /* Values of RCC_ASSCKSELR register */ 121 #define RCC_ASSCKSELR_HSI 0 122 #define RCC_ASSCKSELR_HSE 1 123 #define RCC_ASSCKSELR_PLL 2 124 125 /* Values of RCC_MSSCKSELR register */ 126 #define RCC_MSSCKSELR_HSI 0 127 #define RCC_MSSCKSELR_HSE 1 128 #define RCC_MSSCKSELR_CSI 2 129 #define RCC_MSSCKSELR_PLL 3 130 131 /* Values of RCC_CPERCKSELR register */ 132 #define RCC_CPERCKSELR_HSI 0 133 #define RCC_CPERCKSELR_CSI 1 134 #define RCC_CPERCKSELR_HSE 2 135 136 /* used for most of DIVR register : max div for RTC */ 137 #define RCC_DIVR_DIV_MASK GENMASK(5, 0) 138 #define RCC_DIVR_DIVRDY BIT(31) 139 140 /* Masks for specific DIVR registers */ 141 #define RCC_APBXDIV_MASK GENMASK(2, 0) 142 #define RCC_MPUDIV_MASK GENMASK(2, 0) 143 #define RCC_AXIDIV_MASK GENMASK(2, 0) 144 #define RCC_MCUDIV_MASK GENMASK(3, 0) 145 146 /* offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */ 147 #define RCC_MP_ENCLRR_OFFSET 4 148 149 /* Fields of RCC_BDCR register */ 150 #define RCC_BDCR_LSEON BIT(0) 151 #define RCC_BDCR_LSEBYP BIT(1) 152 #define RCC_BDCR_LSERDY BIT(2) 153 #define RCC_BDCR_DIGBYP BIT(3) 154 #define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4) 155 #define RCC_BDCR_LSEDRV_SHIFT 4 156 #define RCC_BDCR_LSECSSON BIT(8) 157 #define RCC_BDCR_RTCCKEN BIT(20) 158 #define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16) 159 #define RCC_BDCR_RTCSRC_SHIFT 16 160 161 /* Fields of RCC_RDLSICR register */ 162 #define RCC_RDLSICR_LSION BIT(0) 163 #define RCC_RDLSICR_LSIRDY BIT(1) 164 165 /* used for ALL PLLNCR registers */ 166 #define RCC_PLLNCR_PLLON BIT(0) 167 #define RCC_PLLNCR_PLLRDY BIT(1) 168 #define RCC_PLLNCR_DIVPEN BIT(4) 169 #define RCC_PLLNCR_DIVQEN BIT(5) 170 #define RCC_PLLNCR_DIVREN BIT(6) 171 #define RCC_PLLNCR_DIVEN_SHIFT 4 172 173 /* used for ALL PLLNCFGR1 registers */ 174 #define RCC_PLLNCFGR1_DIVM_SHIFT 16 175 #define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16) 176 #define RCC_PLLNCFGR1_DIVN_SHIFT 0 177 #define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0) 178 /* only for PLL3 and PLL4 */ 179 #define RCC_PLLNCFGR1_IFRGE_SHIFT 24 180 #define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24) 181 182 /* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */ 183 #define RCC_PLLNCFGR2_SHIFT(div_id) ((div_id) * 8) 184 #define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0) 185 #define RCC_PLLNCFGR2_DIVP_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_P) 186 #define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0) 187 #define RCC_PLLNCFGR2_DIVQ_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_Q) 188 #define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8) 189 #define RCC_PLLNCFGR2_DIVR_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_R) 190 #define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16) 191 192 /* used for ALL PLLNFRACR registers */ 193 #define RCC_PLLNFRACR_FRACV_SHIFT 3 194 #define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3) 195 #define RCC_PLLNFRACR_FRACLE BIT(16) 196 197 /* used for ALL PLLNCSGR registers */ 198 #define RCC_PLLNCSGR_INC_STEP_SHIFT 16 199 #define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16) 200 #define RCC_PLLNCSGR_MOD_PER_SHIFT 0 201 #define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0) 202 #define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15 203 #define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15) 204 205 /* used for RCC_OCENSETR and RCC_OCENCLRR registers */ 206 #define RCC_OCENR_HSION BIT(0) 207 #define RCC_OCENR_CSION BIT(4) 208 #define RCC_OCENR_DIGBYP BIT(7) 209 #define RCC_OCENR_HSEON BIT(8) 210 #define RCC_OCENR_HSEBYP BIT(10) 211 #define RCC_OCENR_HSECSSON BIT(11) 212 213 /* Fields of RCC_OCRDYR register */ 214 #define RCC_OCRDYR_HSIRDY BIT(0) 215 #define RCC_OCRDYR_HSIDIVRDY BIT(2) 216 #define RCC_OCRDYR_CSIRDY BIT(4) 217 #define RCC_OCRDYR_HSERDY BIT(8) 218 219 /* Fields of DDRITFCR register */ 220 #define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20) 221 #define RCC_DDRITFCR_DDRCKMOD_SHIFT 20 222 #define RCC_DDRITFCR_DDRCKMOD_SSR 0 223 224 /* Fields of RCC_HSICFGR register */ 225 #define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0) 226 227 /* used for MCO related operations */ 228 #define RCC_MCOCFG_MCOON BIT(12) 229 #define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4) 230 #define RCC_MCOCFG_MCODIV_SHIFT 4 231 #define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0) 232 233 enum stm32mp1_parent_id { 234 /* 235 * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved 236 * they are used as index in osc[] as entry point 237 */ 238 _HSI, 239 _HSE, 240 _CSI, 241 _LSI, 242 _LSE, 243 _I2S_CKIN, 244 NB_OSC, 245 246 /* other parent source */ 247 _HSI_KER = NB_OSC, 248 _HSE_KER, 249 _HSE_KER_DIV2, 250 _CSI_KER, 251 _PLL1_P, 252 _PLL1_Q, 253 _PLL1_R, 254 _PLL2_P, 255 _PLL2_Q, 256 _PLL2_R, 257 _PLL3_P, 258 _PLL3_Q, 259 _PLL3_R, 260 _PLL4_P, 261 _PLL4_Q, 262 _PLL4_R, 263 _ACLK, 264 _PCLK1, 265 _PCLK2, 266 _PCLK3, 267 _PCLK4, 268 _PCLK5, 269 _HCLK6, 270 _HCLK2, 271 _CK_PER, 272 _CK_MPU, 273 _CK_MCU, 274 _DSI_PHY, 275 _USB_PHY_48, 276 _PARENT_NB, 277 _UNKNOWN_ID = 0xff, 278 }; 279 280 enum stm32mp1_parent_sel { 281 _I2C12_SEL, 282 _I2C35_SEL, 283 _I2C46_SEL, 284 _UART6_SEL, 285 _UART24_SEL, 286 _UART35_SEL, 287 _UART78_SEL, 288 _SDMMC12_SEL, 289 _SDMMC3_SEL, 290 _ETH_SEL, 291 _QSPI_SEL, 292 _FMC_SEL, 293 _USBPHY_SEL, 294 _USBO_SEL, 295 _STGEN_SEL, 296 _DSI_SEL, 297 _ADC12_SEL, 298 _PARENT_SEL_NB, 299 _UNKNOWN_SEL = 0xff, 300 }; 301 302 enum stm32mp1_pll_id { 303 _PLL1, 304 _PLL2, 305 _PLL3, 306 _PLL4, 307 _PLL_NB 308 }; 309 310 enum stm32mp1_div_id { 311 _DIV_P, 312 _DIV_Q, 313 _DIV_R, 314 _DIV_NB, 315 }; 316 317 enum stm32mp1_clksrc_id { 318 CLKSRC_MPU, 319 CLKSRC_AXI, 320 CLKSRC_MCU, 321 CLKSRC_PLL12, 322 CLKSRC_PLL3, 323 CLKSRC_PLL4, 324 CLKSRC_RTC, 325 CLKSRC_MCO1, 326 CLKSRC_MCO2, 327 CLKSRC_NB 328 }; 329 330 enum stm32mp1_clkdiv_id { 331 CLKDIV_MPU, 332 CLKDIV_AXI, 333 CLKDIV_MCU, 334 CLKDIV_APB1, 335 CLKDIV_APB2, 336 CLKDIV_APB3, 337 CLKDIV_APB4, 338 CLKDIV_APB5, 339 CLKDIV_RTC, 340 CLKDIV_MCO1, 341 CLKDIV_MCO2, 342 CLKDIV_NB 343 }; 344 345 enum stm32mp1_pllcfg { 346 PLLCFG_M, 347 PLLCFG_N, 348 PLLCFG_P, 349 PLLCFG_Q, 350 PLLCFG_R, 351 PLLCFG_O, 352 PLLCFG_NB 353 }; 354 355 enum stm32mp1_pllcsg { 356 PLLCSG_MOD_PER, 357 PLLCSG_INC_STEP, 358 PLLCSG_SSCG_MODE, 359 PLLCSG_NB 360 }; 361 362 enum stm32mp1_plltype { 363 PLL_800, 364 PLL_1600, 365 PLL_TYPE_NB 366 }; 367 368 struct stm32mp1_pll { 369 u8 refclk_min; 370 u8 refclk_max; 371 u8 divn_max; 372 }; 373 374 struct stm32mp1_clk_gate { 375 u16 offset; 376 u8 bit; 377 u8 index; 378 u8 set_clr; 379 u8 sel; 380 u8 fixed; 381 }; 382 383 struct stm32mp1_clk_sel { 384 u16 offset; 385 u8 src; 386 u8 msk; 387 u8 nb_parent; 388 const u8 *parent; 389 }; 390 391 #define REFCLK_SIZE 4 392 struct stm32mp1_clk_pll { 393 enum stm32mp1_plltype plltype; 394 u16 rckxselr; 395 u16 pllxcfgr1; 396 u16 pllxcfgr2; 397 u16 pllxfracr; 398 u16 pllxcr; 399 u16 pllxcsgr; 400 u8 refclk[REFCLK_SIZE]; 401 }; 402 403 struct stm32mp1_clk_data { 404 const struct stm32mp1_clk_gate *gate; 405 const struct stm32mp1_clk_sel *sel; 406 const struct stm32mp1_clk_pll *pll; 407 const int nb_gate; 408 }; 409 410 struct stm32mp1_clk_priv { 411 fdt_addr_t base; 412 const struct stm32mp1_clk_data *data; 413 ulong osc[NB_OSC]; 414 struct udevice *osc_dev[NB_OSC]; 415 }; 416 417 #define STM32MP1_CLK(off, b, idx, s) \ 418 { \ 419 .offset = (off), \ 420 .bit = (b), \ 421 .index = (idx), \ 422 .set_clr = 0, \ 423 .sel = (s), \ 424 .fixed = _UNKNOWN_ID, \ 425 } 426 427 #define STM32MP1_CLK_F(off, b, idx, f) \ 428 { \ 429 .offset = (off), \ 430 .bit = (b), \ 431 .index = (idx), \ 432 .set_clr = 0, \ 433 .sel = _UNKNOWN_SEL, \ 434 .fixed = (f), \ 435 } 436 437 #define STM32MP1_CLK_SET_CLR(off, b, idx, s) \ 438 { \ 439 .offset = (off), \ 440 .bit = (b), \ 441 .index = (idx), \ 442 .set_clr = 1, \ 443 .sel = (s), \ 444 .fixed = _UNKNOWN_ID, \ 445 } 446 447 #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f) \ 448 { \ 449 .offset = (off), \ 450 .bit = (b), \ 451 .index = (idx), \ 452 .set_clr = 1, \ 453 .sel = _UNKNOWN_SEL, \ 454 .fixed = (f), \ 455 } 456 457 #define STM32MP1_CLK_PARENT(idx, off, s, m, p) \ 458 [(idx)] = { \ 459 .offset = (off), \ 460 .src = (s), \ 461 .msk = (m), \ 462 .parent = (p), \ 463 .nb_parent = ARRAY_SIZE((p)) \ 464 } 465 466 #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\ 467 p1, p2, p3, p4) \ 468 [(idx)] = { \ 469 .plltype = (type), \ 470 .rckxselr = (off1), \ 471 .pllxcfgr1 = (off2), \ 472 .pllxcfgr2 = (off3), \ 473 .pllxfracr = (off4), \ 474 .pllxcr = (off5), \ 475 .pllxcsgr = (off6), \ 476 .refclk[0] = (p1), \ 477 .refclk[1] = (p2), \ 478 .refclk[2] = (p3), \ 479 .refclk[3] = (p4), \ 480 } 481 482 static const u8 stm32mp1_clks[][2] = { 483 {CK_PER, _CK_PER}, 484 {CK_MPU, _CK_MPU}, 485 {CK_AXI, _ACLK}, 486 {CK_MCU, _CK_MCU}, 487 {CK_HSE, _HSE}, 488 {CK_CSI, _CSI}, 489 {CK_LSI, _LSI}, 490 {CK_LSE, _LSE}, 491 {CK_HSI, _HSI}, 492 {CK_HSE_DIV2, _HSE_KER_DIV2}, 493 }; 494 495 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { 496 STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL), 497 STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL), 498 STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL), 499 STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL), 500 STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), 501 STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL), 502 STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL), 503 STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL), 504 STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL), 505 STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL), 506 STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL), 507 508 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), 509 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), 510 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), 511 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), 512 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), 513 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), 514 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL), 515 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL), 516 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL), 517 STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL), 518 519 STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), 520 521 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3), 522 523 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q), 524 STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q), 525 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL), 526 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), 527 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), 528 STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), 529 530 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), 531 STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), 532 533 STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2), 534 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 5, ADC12_K, _ADC12_SEL), 535 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), 536 STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), 537 538 STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL), 539 STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 12, IPCC, _UNKNOWN_SEL), 540 541 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), 542 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), 543 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), 544 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL), 545 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL), 546 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL), 547 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL), 548 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL), 549 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL), 550 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL), 551 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), 552 553 STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL), 554 555 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _ETH_SEL), 556 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL), 557 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL), 558 STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK), 559 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL), 560 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL), 561 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL), 562 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL), 563 STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL), 564 565 STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), 566 }; 567 568 static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER}; 569 static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER}; 570 static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER}; 571 static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, 572 _HSE_KER}; 573 static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, 574 _HSE_KER}; 575 static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, 576 _HSE_KER}; 577 static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, 578 _HSE_KER}; 579 static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER}; 580 static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER}; 581 static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q}; 582 static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER}; 583 static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER}; 584 static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2}; 585 static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48}; 586 static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER}; 587 static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P}; 588 static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q}; 589 590 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { 591 STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents), 592 STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents), 593 STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents), 594 STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents), 595 STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7, 596 uart24_parents), 597 STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7, 598 uart35_parents), 599 STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7, 600 uart78_parents), 601 STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7, 602 sdmmc12_parents), 603 STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7, 604 sdmmc3_parents), 605 STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents), 606 STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents), 607 STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents), 608 STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents), 609 STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents), 610 STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents), 611 STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents), 612 STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x1, adc_parents), 613 }; 614 615 #ifdef STM32MP1_CLOCK_TREE_INIT 616 /* define characteristic of PLL according type */ 617 #define DIVN_MIN 24 618 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { 619 [PLL_800] = { 620 .refclk_min = 4, 621 .refclk_max = 16, 622 .divn_max = 99, 623 }, 624 [PLL_1600] = { 625 .refclk_min = 8, 626 .refclk_max = 16, 627 .divn_max = 199, 628 }, 629 }; 630 #endif /* STM32MP1_CLOCK_TREE_INIT */ 631 632 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { 633 STM32MP1_CLK_PLL(_PLL1, PLL_1600, 634 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, 635 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, 636 _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID), 637 STM32MP1_CLK_PLL(_PLL2, PLL_1600, 638 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, 639 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, 640 _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID), 641 STM32MP1_CLK_PLL(_PLL3, PLL_800, 642 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, 643 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, 644 _HSI, _HSE, _CSI, _UNKNOWN_ID), 645 STM32MP1_CLK_PLL(_PLL4, PLL_800, 646 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, 647 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, 648 _HSI, _HSE, _CSI, _I2S_CKIN), 649 }; 650 651 /* Prescaler table lookups for clock computation */ 652 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */ 653 static const u8 stm32mp1_mcu_div[16] = { 654 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9 655 }; 656 657 /* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/ 658 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div 659 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div 660 static const u8 stm32mp1_mpu_apbx_div[8] = { 661 0, 1, 2, 3, 4, 4, 4, 4 662 }; 663 664 /* div = /1 /2 /3 /4 */ 665 static const u8 stm32mp1_axi_div[8] = { 666 1, 2, 3, 4, 4, 4, 4, 4 667 }; 668 669 static const __maybe_unused 670 char * const stm32mp1_clk_parent_name[_PARENT_NB] = { 671 [_HSI] = "HSI", 672 [_HSE] = "HSE", 673 [_CSI] = "CSI", 674 [_LSI] = "LSI", 675 [_LSE] = "LSE", 676 [_I2S_CKIN] = "I2S_CKIN", 677 [_HSI_KER] = "HSI_KER", 678 [_HSE_KER] = "HSE_KER", 679 [_HSE_KER_DIV2] = "HSE_KER_DIV2", 680 [_CSI_KER] = "CSI_KER", 681 [_PLL1_P] = "PLL1_P", 682 [_PLL1_Q] = "PLL1_Q", 683 [_PLL1_R] = "PLL1_R", 684 [_PLL2_P] = "PLL2_P", 685 [_PLL2_Q] = "PLL2_Q", 686 [_PLL2_R] = "PLL2_R", 687 [_PLL3_P] = "PLL3_P", 688 [_PLL3_Q] = "PLL3_Q", 689 [_PLL3_R] = "PLL3_R", 690 [_PLL4_P] = "PLL4_P", 691 [_PLL4_Q] = "PLL4_Q", 692 [_PLL4_R] = "PLL4_R", 693 [_ACLK] = "ACLK", 694 [_PCLK1] = "PCLK1", 695 [_PCLK2] = "PCLK2", 696 [_PCLK3] = "PCLK3", 697 [_PCLK4] = "PCLK4", 698 [_PCLK5] = "PCLK5", 699 [_HCLK6] = "KCLK6", 700 [_HCLK2] = "HCLK2", 701 [_CK_PER] = "CK_PER", 702 [_CK_MPU] = "CK_MPU", 703 [_CK_MCU] = "CK_MCU", 704 [_USB_PHY_48] = "USB_PHY_48", 705 [_DSI_PHY] = "DSI_PHY_PLL", 706 }; 707 708 static const __maybe_unused 709 char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = { 710 [_I2C12_SEL] = "I2C12", 711 [_I2C35_SEL] = "I2C35", 712 [_I2C46_SEL] = "I2C46", 713 [_UART6_SEL] = "UART6", 714 [_UART24_SEL] = "UART24", 715 [_UART35_SEL] = "UART35", 716 [_UART78_SEL] = "UART78", 717 [_SDMMC12_SEL] = "SDMMC12", 718 [_SDMMC3_SEL] = "SDMMC3", 719 [_ETH_SEL] = "ETH", 720 [_QSPI_SEL] = "QSPI", 721 [_FMC_SEL] = "FMC", 722 [_USBPHY_SEL] = "USBPHY", 723 [_USBO_SEL] = "USBO", 724 [_STGEN_SEL] = "STGEN", 725 [_DSI_SEL] = "DSI", 726 [_ADC12_SEL] = "ADC12", 727 }; 728 729 static const struct stm32mp1_clk_data stm32mp1_data = { 730 .gate = stm32mp1_clk_gate, 731 .sel = stm32mp1_clk_sel, 732 .pll = stm32mp1_clk_pll, 733 .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate), 734 }; 735 736 static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx) 737 { 738 if (idx >= NB_OSC) { 739 debug("%s: clk id %d not found\n", __func__, idx); 740 return 0; 741 } 742 743 debug("%s: clk id %d = %x : %ld kHz\n", __func__, idx, 744 (u32)priv->osc[idx], priv->osc[idx] / 1000); 745 746 return priv->osc[idx]; 747 } 748 749 static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id) 750 { 751 const struct stm32mp1_clk_gate *gate = priv->data->gate; 752 int i, nb_clks = priv->data->nb_gate; 753 754 for (i = 0; i < nb_clks; i++) { 755 if (gate[i].index == id) 756 break; 757 } 758 759 if (i == nb_clks) { 760 printf("%s: clk id %d not found\n", __func__, (u32)id); 761 return -EINVAL; 762 } 763 764 return i; 765 } 766 767 static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv, 768 int i) 769 { 770 const struct stm32mp1_clk_gate *gate = priv->data->gate; 771 772 if (gate[i].sel > _PARENT_SEL_NB) { 773 printf("%s: parents for clk id %d not found\n", 774 __func__, i); 775 return -EINVAL; 776 } 777 778 return gate[i].sel; 779 } 780 781 static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv, 782 int i) 783 { 784 const struct stm32mp1_clk_gate *gate = priv->data->gate; 785 786 if (gate[i].fixed == _UNKNOWN_ID) 787 return -ENOENT; 788 789 return gate[i].fixed; 790 } 791 792 static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv, 793 unsigned long id) 794 { 795 const struct stm32mp1_clk_sel *sel = priv->data->sel; 796 int i; 797 int s, p; 798 799 for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++) 800 if (stm32mp1_clks[i][0] == id) 801 return stm32mp1_clks[i][1]; 802 803 i = stm32mp1_clk_get_id(priv, id); 804 if (i < 0) 805 return i; 806 807 p = stm32mp1_clk_get_fixed_parent(priv, i); 808 if (p >= 0 && p < _PARENT_NB) 809 return p; 810 811 s = stm32mp1_clk_get_sel(priv, i); 812 if (s < 0) 813 return s; 814 815 p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk; 816 817 if (p < sel[s].nb_parent) { 818 #ifdef DEBUG 819 debug("%s: %s clock is the parent %s of clk id %d\n", __func__, 820 stm32mp1_clk_parent_name[sel[s].parent[p]], 821 stm32mp1_clk_parent_sel_name[s], 822 (u32)id); 823 #endif 824 return sel[s].parent[p]; 825 } 826 827 pr_err("%s: no parents defined for clk id %d\n", 828 __func__, (u32)id); 829 830 return -EINVAL; 831 } 832 833 static ulong pll_get_fref_ck(struct stm32mp1_clk_priv *priv, 834 int pll_id) 835 { 836 const struct stm32mp1_clk_pll *pll = priv->data->pll; 837 u32 selr; 838 int src; 839 ulong refclk; 840 841 /* Get current refclk */ 842 selr = readl(priv->base + pll[pll_id].rckxselr); 843 src = selr & RCC_SELR_SRC_MASK; 844 845 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]); 846 debug("PLL%d : selr=%x refclk = %d kHz\n", 847 pll_id, selr, (u32)(refclk / 1000)); 848 849 return refclk; 850 } 851 852 /* 853 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL 854 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1) 855 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) 856 * => in all the case Fpll_y_ck = pll_get_fvco() / (DIVy + 1) 857 */ 858 static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv, 859 int pll_id) 860 { 861 const struct stm32mp1_clk_pll *pll = priv->data->pll; 862 int divm, divn; 863 ulong refclk, fvco; 864 u32 cfgr1, fracr; 865 866 cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1); 867 fracr = readl(priv->base + pll[pll_id].pllxfracr); 868 869 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; 870 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 871 872 debug("PLL%d : cfgr1=%x fracr=%x DIVN=%d DIVM=%d\n", 873 pll_id, cfgr1, fracr, divn, divm); 874 875 refclk = pll_get_fref_ck(priv, pll_id); 876 877 /* with FRACV : 878 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) 879 * without FRACV 880 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) 881 */ 882 if (fracr & RCC_PLLNFRACR_FRACLE) { 883 u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) 884 >> RCC_PLLNFRACR_FRACV_SHIFT; 885 fvco = (ulong)lldiv((unsigned long long)refclk * 886 (((divn + 1) << 13) + fracv), 887 ((unsigned long long)(divm + 1)) << 13); 888 } else { 889 fvco = (ulong)(refclk * (divn + 1) / (divm + 1)); 890 } 891 debug("PLL%d : %s = %ld\n", pll_id, __func__, fvco); 892 893 return fvco; 894 } 895 896 static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv, 897 int pll_id, int div_id) 898 { 899 const struct stm32mp1_clk_pll *pll = priv->data->pll; 900 int divy; 901 ulong dfout; 902 u32 cfgr2; 903 904 debug("%s(%d, %d)\n", __func__, pll_id, div_id); 905 if (div_id >= _DIV_NB) 906 return 0; 907 908 cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2); 909 divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK; 910 911 debug("PLL%d : cfgr2=%x DIVY=%d\n", pll_id, cfgr2, divy); 912 913 dfout = pll_get_fvco(priv, pll_id) / (divy + 1); 914 debug(" => dfout = %d kHz\n", (u32)(dfout / 1000)); 915 916 return dfout; 917 } 918 919 static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p) 920 { 921 u32 reg; 922 ulong clock = 0; 923 924 switch (p) { 925 case _CK_MPU: 926 /* MPU sub system */ 927 reg = readl(priv->base + RCC_MPCKSELR); 928 switch (reg & RCC_SELR_SRC_MASK) { 929 case RCC_MPCKSELR_HSI: 930 clock = stm32mp1_clk_get_fixed(priv, _HSI); 931 break; 932 case RCC_MPCKSELR_HSE: 933 clock = stm32mp1_clk_get_fixed(priv, _HSE); 934 break; 935 case RCC_MPCKSELR_PLL: 936 case RCC_MPCKSELR_PLL_MPUDIV: 937 clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P); 938 if (p == RCC_MPCKSELR_PLL_MPUDIV) { 939 reg = readl(priv->base + RCC_MPCKDIVR); 940 clock /= stm32mp1_mpu_div[reg & 941 RCC_MPUDIV_MASK]; 942 } 943 break; 944 } 945 break; 946 /* AXI sub system */ 947 case _ACLK: 948 case _HCLK2: 949 case _HCLK6: 950 case _PCLK4: 951 case _PCLK5: 952 reg = readl(priv->base + RCC_ASSCKSELR); 953 switch (reg & RCC_SELR_SRC_MASK) { 954 case RCC_ASSCKSELR_HSI: 955 clock = stm32mp1_clk_get_fixed(priv, _HSI); 956 break; 957 case RCC_ASSCKSELR_HSE: 958 clock = stm32mp1_clk_get_fixed(priv, _HSE); 959 break; 960 case RCC_ASSCKSELR_PLL: 961 clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P); 962 break; 963 } 964 965 /* System clock divider */ 966 reg = readl(priv->base + RCC_AXIDIVR); 967 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; 968 969 switch (p) { 970 case _PCLK4: 971 reg = readl(priv->base + RCC_APB4DIVR); 972 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 973 break; 974 case _PCLK5: 975 reg = readl(priv->base + RCC_APB5DIVR); 976 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 977 break; 978 default: 979 break; 980 } 981 break; 982 /* MCU sub system */ 983 case _CK_MCU: 984 case _PCLK1: 985 case _PCLK2: 986 case _PCLK3: 987 reg = readl(priv->base + RCC_MSSCKSELR); 988 switch (reg & RCC_SELR_SRC_MASK) { 989 case RCC_MSSCKSELR_HSI: 990 clock = stm32mp1_clk_get_fixed(priv, _HSI); 991 break; 992 case RCC_MSSCKSELR_HSE: 993 clock = stm32mp1_clk_get_fixed(priv, _HSE); 994 break; 995 case RCC_MSSCKSELR_CSI: 996 clock = stm32mp1_clk_get_fixed(priv, _CSI); 997 break; 998 case RCC_MSSCKSELR_PLL: 999 clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P); 1000 break; 1001 } 1002 1003 /* MCU clock divider */ 1004 reg = readl(priv->base + RCC_MCUDIVR); 1005 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK]; 1006 1007 switch (p) { 1008 case _PCLK1: 1009 reg = readl(priv->base + RCC_APB1DIVR); 1010 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 1011 break; 1012 case _PCLK2: 1013 reg = readl(priv->base + RCC_APB2DIVR); 1014 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 1015 break; 1016 case _PCLK3: 1017 reg = readl(priv->base + RCC_APB3DIVR); 1018 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 1019 break; 1020 case _CK_MCU: 1021 default: 1022 break; 1023 } 1024 break; 1025 case _CK_PER: 1026 reg = readl(priv->base + RCC_CPERCKSELR); 1027 switch (reg & RCC_SELR_SRC_MASK) { 1028 case RCC_CPERCKSELR_HSI: 1029 clock = stm32mp1_clk_get_fixed(priv, _HSI); 1030 break; 1031 case RCC_CPERCKSELR_HSE: 1032 clock = stm32mp1_clk_get_fixed(priv, _HSE); 1033 break; 1034 case RCC_CPERCKSELR_CSI: 1035 clock = stm32mp1_clk_get_fixed(priv, _CSI); 1036 break; 1037 } 1038 break; 1039 case _HSI: 1040 case _HSI_KER: 1041 clock = stm32mp1_clk_get_fixed(priv, _HSI); 1042 break; 1043 case _CSI: 1044 case _CSI_KER: 1045 clock = stm32mp1_clk_get_fixed(priv, _CSI); 1046 break; 1047 case _HSE: 1048 case _HSE_KER: 1049 case _HSE_KER_DIV2: 1050 clock = stm32mp1_clk_get_fixed(priv, _HSE); 1051 if (p == _HSE_KER_DIV2) 1052 clock >>= 1; 1053 break; 1054 case _LSI: 1055 clock = stm32mp1_clk_get_fixed(priv, _LSI); 1056 break; 1057 case _LSE: 1058 clock = stm32mp1_clk_get_fixed(priv, _LSE); 1059 break; 1060 /* PLL */ 1061 case _PLL1_P: 1062 case _PLL1_Q: 1063 case _PLL1_R: 1064 clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P); 1065 break; 1066 case _PLL2_P: 1067 case _PLL2_Q: 1068 case _PLL2_R: 1069 clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P); 1070 break; 1071 case _PLL3_P: 1072 case _PLL3_Q: 1073 case _PLL3_R: 1074 clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P); 1075 break; 1076 case _PLL4_P: 1077 case _PLL4_Q: 1078 case _PLL4_R: 1079 clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P); 1080 break; 1081 /* other */ 1082 case _USB_PHY_48: 1083 clock = 48000000; 1084 break; 1085 case _DSI_PHY: 1086 { 1087 struct clk clk; 1088 struct udevice *dev = NULL; 1089 1090 if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy", 1091 &dev)) { 1092 if (clk_request(dev, &clk)) { 1093 pr_err("ck_dsi_phy request"); 1094 } else { 1095 clk.id = 0; 1096 clock = clk_get_rate(&clk); 1097 } 1098 } 1099 break; 1100 } 1101 default: 1102 break; 1103 } 1104 1105 debug("%s(%d) clock = %lx : %ld kHz\n", 1106 __func__, p, clock, clock / 1000); 1107 1108 return clock; 1109 } 1110 1111 static int stm32mp1_clk_enable(struct clk *clk) 1112 { 1113 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev); 1114 const struct stm32mp1_clk_gate *gate = priv->data->gate; 1115 int i = stm32mp1_clk_get_id(priv, clk->id); 1116 1117 if (i < 0) 1118 return i; 1119 1120 if (gate[i].set_clr) 1121 writel(BIT(gate[i].bit), priv->base + gate[i].offset); 1122 else 1123 setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit)); 1124 1125 debug("%s: id clock %d has been enabled\n", __func__, (u32)clk->id); 1126 1127 return 0; 1128 } 1129 1130 static int stm32mp1_clk_disable(struct clk *clk) 1131 { 1132 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev); 1133 const struct stm32mp1_clk_gate *gate = priv->data->gate; 1134 int i = stm32mp1_clk_get_id(priv, clk->id); 1135 1136 if (i < 0) 1137 return i; 1138 1139 if (gate[i].set_clr) 1140 writel(BIT(gate[i].bit), 1141 priv->base + gate[i].offset 1142 + RCC_MP_ENCLRR_OFFSET); 1143 else 1144 clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit)); 1145 1146 debug("%s: id clock %d has been disabled\n", __func__, (u32)clk->id); 1147 1148 return 0; 1149 } 1150 1151 static ulong stm32mp1_clk_get_rate(struct clk *clk) 1152 { 1153 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev); 1154 int p = stm32mp1_clk_get_parent(priv, clk->id); 1155 ulong rate; 1156 1157 if (p < 0) 1158 return 0; 1159 1160 rate = stm32mp1_clk_get(priv, p); 1161 1162 #ifdef DEBUG 1163 debug("%s: computed rate for id clock %d is %d (parent is %s)\n", 1164 __func__, (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]); 1165 #endif 1166 return rate; 1167 } 1168 1169 #ifdef STM32MP1_CLOCK_TREE_INIT 1170 static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset, 1171 u32 mask_on) 1172 { 1173 u32 address = rcc + offset; 1174 1175 if (enable) 1176 setbits_le32(address, mask_on); 1177 else 1178 clrbits_le32(address, mask_on); 1179 } 1180 1181 static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on) 1182 { 1183 writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR)); 1184 } 1185 1186 static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset, 1187 u32 mask_rdy) 1188 { 1189 u32 mask_test = 0; 1190 u32 address = rcc + offset; 1191 u32 val; 1192 int ret; 1193 1194 if (enable) 1195 mask_test = mask_rdy; 1196 1197 ret = readl_poll_timeout(address, val, 1198 (val & mask_rdy) == mask_test, 1199 TIMEOUT_1S); 1200 1201 if (ret) 1202 pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n", 1203 mask_rdy, address, enable, readl(address)); 1204 1205 return ret; 1206 } 1207 1208 static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp, 1209 int lsedrv) 1210 { 1211 u32 value; 1212 1213 if (digbyp) 1214 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP); 1215 1216 if (bypass || digbyp) 1217 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP); 1218 1219 /* 1220 * warning: not recommended to switch directly from "high drive" 1221 * to "medium low drive", and vice-versa. 1222 */ 1223 value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) 1224 >> RCC_BDCR_LSEDRV_SHIFT; 1225 1226 while (value != lsedrv) { 1227 if (value > lsedrv) 1228 value--; 1229 else 1230 value++; 1231 1232 clrsetbits_le32(rcc + RCC_BDCR, 1233 RCC_BDCR_LSEDRV_MASK, 1234 value << RCC_BDCR_LSEDRV_SHIFT); 1235 } 1236 1237 stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON); 1238 } 1239 1240 static void stm32mp1_lse_wait(fdt_addr_t rcc) 1241 { 1242 stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY); 1243 } 1244 1245 static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable) 1246 { 1247 stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION); 1248 stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY); 1249 } 1250 1251 static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css) 1252 { 1253 if (digbyp) 1254 writel(RCC_OCENR_DIGBYP, rcc + RCC_OCENSETR); 1255 if (bypass || digbyp) 1256 writel(RCC_OCENR_HSEBYP, rcc + RCC_OCENSETR); 1257 1258 stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON); 1259 stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY); 1260 1261 if (css) 1262 writel(RCC_OCENR_HSECSSON, rcc + RCC_OCENSETR); 1263 } 1264 1265 static void stm32mp1_csi_set(fdt_addr_t rcc, int enable) 1266 { 1267 stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_CSION); 1268 stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY); 1269 } 1270 1271 static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable) 1272 { 1273 stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION); 1274 stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY); 1275 } 1276 1277 static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv) 1278 { 1279 u32 address = rcc + RCC_OCRDYR; 1280 u32 val; 1281 int ret; 1282 1283 clrsetbits_le32(rcc + RCC_HSICFGR, 1284 RCC_HSICFGR_HSIDIV_MASK, 1285 RCC_HSICFGR_HSIDIV_MASK & hsidiv); 1286 1287 ret = readl_poll_timeout(address, val, 1288 val & RCC_OCRDYR_HSIDIVRDY, 1289 TIMEOUT_200MS); 1290 if (ret) 1291 pr_err("HSIDIV failed @ 0x%x: 0x%x\n", 1292 address, readl(address)); 1293 1294 return ret; 1295 } 1296 1297 static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq) 1298 { 1299 u8 hsidiv; 1300 u32 hsidivfreq = MAX_HSI_HZ; 1301 1302 for (hsidiv = 0; hsidiv < 4; hsidiv++, 1303 hsidivfreq = hsidivfreq / 2) 1304 if (hsidivfreq == hsifreq) 1305 break; 1306 1307 if (hsidiv == 4) { 1308 pr_err("clk-hsi frequency invalid"); 1309 return -1; 1310 } 1311 1312 if (hsidiv > 0) 1313 return stm32mp1_set_hsidiv(rcc, hsidiv); 1314 1315 return 0; 1316 } 1317 1318 static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id) 1319 { 1320 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1321 1322 writel(RCC_PLLNCR_PLLON, priv->base + pll[pll_id].pllxcr); 1323 } 1324 1325 static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output) 1326 { 1327 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1328 u32 pllxcr = priv->base + pll[pll_id].pllxcr; 1329 u32 val; 1330 int ret; 1331 1332 ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY, 1333 TIMEOUT_200MS); 1334 1335 if (ret) { 1336 pr_err("PLL%d start failed @ 0x%x: 0x%x\n", 1337 pll_id, pllxcr, readl(pllxcr)); 1338 return ret; 1339 } 1340 1341 /* start the requested output */ 1342 setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT); 1343 1344 return 0; 1345 } 1346 1347 static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id) 1348 { 1349 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1350 u32 pllxcr = priv->base + pll[pll_id].pllxcr; 1351 u32 val; 1352 1353 /* stop all output */ 1354 clrbits_le32(pllxcr, 1355 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN); 1356 1357 /* stop PLL */ 1358 clrbits_le32(pllxcr, RCC_PLLNCR_PLLON); 1359 1360 /* wait PLL stopped */ 1361 return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0, 1362 TIMEOUT_200MS); 1363 } 1364 1365 static void pll_config_output(struct stm32mp1_clk_priv *priv, 1366 int pll_id, u32 *pllcfg) 1367 { 1368 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1369 fdt_addr_t rcc = priv->base; 1370 u32 value; 1371 1372 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) 1373 & RCC_PLLNCFGR2_DIVP_MASK; 1374 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) 1375 & RCC_PLLNCFGR2_DIVQ_MASK; 1376 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) 1377 & RCC_PLLNCFGR2_DIVR_MASK; 1378 writel(value, rcc + pll[pll_id].pllxcfgr2); 1379 } 1380 1381 static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id, 1382 u32 *pllcfg, u32 fracv) 1383 { 1384 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1385 fdt_addr_t rcc = priv->base; 1386 enum stm32mp1_plltype type = pll[pll_id].plltype; 1387 int src; 1388 ulong refclk; 1389 u8 ifrge = 0; 1390 u32 value; 1391 1392 src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK; 1393 1394 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) / 1395 (pllcfg[PLLCFG_M] + 1); 1396 1397 if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) || 1398 refclk > (stm32mp1_pll[type].refclk_max * 1000000)) { 1399 debug("invalid refclk = %x\n", (u32)refclk); 1400 return -EINVAL; 1401 } 1402 if (type == PLL_800 && refclk >= 8000000) 1403 ifrge = 1; 1404 1405 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) 1406 & RCC_PLLNCFGR1_DIVN_MASK; 1407 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) 1408 & RCC_PLLNCFGR1_DIVM_MASK; 1409 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) 1410 & RCC_PLLNCFGR1_IFRGE_MASK; 1411 writel(value, rcc + pll[pll_id].pllxcfgr1); 1412 1413 /* fractional configuration: load sigma-delta modulator (SDM) */ 1414 1415 /* Write into FRACV the new fractional value , and FRACLE to 0 */ 1416 writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT, 1417 rcc + pll[pll_id].pllxfracr); 1418 1419 /* Write FRACLE to 1 : FRACV value is loaded into the SDM */ 1420 setbits_le32(rcc + pll[pll_id].pllxfracr, 1421 RCC_PLLNFRACR_FRACLE); 1422 1423 pll_config_output(priv, pll_id, pllcfg); 1424 1425 return 0; 1426 } 1427 1428 static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg) 1429 { 1430 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1431 u32 pllxcsg; 1432 1433 pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) & 1434 RCC_PLLNCSGR_MOD_PER_MASK) | 1435 ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) & 1436 RCC_PLLNCSGR_INC_STEP_MASK) | 1437 ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & 1438 RCC_PLLNCSGR_SSCG_MODE_MASK); 1439 1440 writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr); 1441 } 1442 1443 static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc) 1444 { 1445 u32 address = priv->base + (clksrc >> 4); 1446 u32 val; 1447 int ret; 1448 1449 clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK); 1450 ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY, 1451 TIMEOUT_200MS); 1452 if (ret) 1453 pr_err("CLKSRC %x start failed @ 0x%x: 0x%x\n", 1454 clksrc, address, readl(address)); 1455 1456 return ret; 1457 } 1458 1459 static void stgen_config(struct stm32mp1_clk_priv *priv) 1460 { 1461 int p; 1462 u32 stgenc, cntfid0; 1463 ulong rate; 1464 1465 stgenc = (u32)syscon_get_first_range(STM32MP_SYSCON_STGEN); 1466 1467 cntfid0 = readl(stgenc + STGENC_CNTFID0); 1468 p = stm32mp1_clk_get_parent(priv, STGEN_K); 1469 rate = stm32mp1_clk_get(priv, p); 1470 1471 if (cntfid0 != rate) { 1472 u64 counter; 1473 1474 pr_debug("System Generic Counter (STGEN) update\n"); 1475 clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN); 1476 counter = (u64)readl(stgenc + STGENC_CNTCVL); 1477 counter |= ((u64)(readl(stgenc + STGENC_CNTCVU))) << 32; 1478 counter = lldiv(counter * (u64)rate, cntfid0); 1479 writel((u32)counter, stgenc + STGENC_CNTCVL); 1480 writel((u32)(counter >> 32), stgenc + STGENC_CNTCVU); 1481 writel(rate, stgenc + STGENC_CNTFID0); 1482 setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN); 1483 1484 __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate)); 1485 1486 /* need to update gd->arch.timer_rate_hz with new frequency */ 1487 timer_init(); 1488 pr_debug("gd->arch.timer_rate_hz = %x\n", 1489 (u32)gd->arch.timer_rate_hz); 1490 pr_debug("Tick = %x\n", (u32)(get_ticks())); 1491 } 1492 } 1493 1494 static int set_clkdiv(unsigned int clkdiv, u32 address) 1495 { 1496 u32 val; 1497 int ret; 1498 1499 clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK); 1500 ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY, 1501 TIMEOUT_200MS); 1502 if (ret) 1503 pr_err("CLKDIV %x start failed @ 0x%x: 0x%x\n", 1504 clkdiv, address, readl(address)); 1505 1506 return ret; 1507 } 1508 1509 static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv, 1510 u32 clksrc, u32 clkdiv) 1511 { 1512 u32 address = priv->base + (clksrc >> 4); 1513 1514 /* 1515 * binding clksrc : bit15-4 offset 1516 * bit3: disable 1517 * bit2-0: MCOSEL[2:0] 1518 */ 1519 if (clksrc & 0x8) { 1520 clrbits_le32(address, RCC_MCOCFG_MCOON); 1521 } else { 1522 clrsetbits_le32(address, 1523 RCC_MCOCFG_MCOSRC_MASK, 1524 clksrc & RCC_MCOCFG_MCOSRC_MASK); 1525 clrsetbits_le32(address, 1526 RCC_MCOCFG_MCODIV_MASK, 1527 clkdiv << RCC_MCOCFG_MCODIV_SHIFT); 1528 setbits_le32(address, RCC_MCOCFG_MCOON); 1529 } 1530 } 1531 1532 static void set_rtcsrc(struct stm32mp1_clk_priv *priv, 1533 unsigned int clksrc, 1534 int lse_css) 1535 { 1536 u32 address = priv->base + RCC_BDCR; 1537 1538 if (readl(address) & RCC_BDCR_RTCCKEN) 1539 goto skip_rtc; 1540 1541 if (clksrc == CLK_RTC_DISABLED) 1542 goto skip_rtc; 1543 1544 clrsetbits_le32(address, 1545 RCC_BDCR_RTCSRC_MASK, 1546 clksrc << RCC_BDCR_RTCSRC_SHIFT); 1547 1548 setbits_le32(address, RCC_BDCR_RTCCKEN); 1549 1550 skip_rtc: 1551 if (lse_css) 1552 setbits_le32(address, RCC_BDCR_LSECSSON); 1553 } 1554 1555 static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs) 1556 { 1557 u32 address = priv->base + ((pkcs >> 4) & 0xFFF); 1558 u32 value = pkcs & 0xF; 1559 u32 mask = 0xF; 1560 1561 if (pkcs & BIT(31)) { 1562 mask <<= 4; 1563 value <<= 4; 1564 } 1565 clrsetbits_le32(address, mask, value); 1566 } 1567 1568 static int stm32mp1_clktree(struct udevice *dev) 1569 { 1570 struct stm32mp1_clk_priv *priv = dev_get_priv(dev); 1571 fdt_addr_t rcc = priv->base; 1572 unsigned int clksrc[CLKSRC_NB]; 1573 unsigned int clkdiv[CLKDIV_NB]; 1574 unsigned int pllcfg[_PLL_NB][PLLCFG_NB]; 1575 ofnode plloff[_PLL_NB]; 1576 int ret; 1577 int i, len; 1578 int lse_css = 0; 1579 const u32 *pkcs_cell; 1580 1581 /* check mandatory field */ 1582 ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB); 1583 if (ret < 0) { 1584 debug("field st,clksrc invalid: error %d\n", ret); 1585 return -FDT_ERR_NOTFOUND; 1586 } 1587 1588 ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB); 1589 if (ret < 0) { 1590 debug("field st,clkdiv invalid: error %d\n", ret); 1591 return -FDT_ERR_NOTFOUND; 1592 } 1593 1594 /* check mandatory field in each pll */ 1595 for (i = 0; i < _PLL_NB; i++) { 1596 char name[12]; 1597 1598 sprintf(name, "st,pll@%d", i); 1599 plloff[i] = dev_read_subnode(dev, name); 1600 if (!ofnode_valid(plloff[i])) 1601 continue; 1602 ret = ofnode_read_u32_array(plloff[i], "cfg", 1603 pllcfg[i], PLLCFG_NB); 1604 if (ret < 0) { 1605 debug("field cfg invalid: error %d\n", ret); 1606 return -FDT_ERR_NOTFOUND; 1607 } 1608 } 1609 1610 debug("configuration MCO\n"); 1611 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]); 1612 stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]); 1613 1614 debug("switch ON osillator\n"); 1615 /* 1616 * switch ON oscillator found in device-tree, 1617 * HSI already ON after bootrom 1618 */ 1619 if (priv->osc[_LSI]) 1620 stm32mp1_lsi_set(rcc, 1); 1621 1622 if (priv->osc[_LSE]) { 1623 int bypass, digbyp, lsedrv; 1624 struct udevice *dev = priv->osc_dev[_LSE]; 1625 1626 bypass = dev_read_bool(dev, "st,bypass"); 1627 digbyp = dev_read_bool(dev, "st,digbypass"); 1628 lse_css = dev_read_bool(dev, "st,css"); 1629 lsedrv = dev_read_u32_default(dev, "st,drive", 1630 LSEDRV_MEDIUM_HIGH); 1631 1632 stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv); 1633 } 1634 1635 if (priv->osc[_HSE]) { 1636 int bypass, digbyp, css; 1637 struct udevice *dev = priv->osc_dev[_HSE]; 1638 1639 bypass = dev_read_bool(dev, "st,bypass"); 1640 digbyp = dev_read_bool(dev, "st,digbypass"); 1641 css = dev_read_bool(dev, "st,css"); 1642 1643 stm32mp1_hse_enable(rcc, bypass, digbyp, css); 1644 } 1645 /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR) 1646 * => switch on CSI even if node is not present in device tree 1647 */ 1648 stm32mp1_csi_set(rcc, 1); 1649 1650 /* come back to HSI */ 1651 debug("come back to HSI\n"); 1652 set_clksrc(priv, CLK_MPU_HSI); 1653 set_clksrc(priv, CLK_AXI_HSI); 1654 set_clksrc(priv, CLK_MCU_HSI); 1655 1656 debug("pll stop\n"); 1657 for (i = 0; i < _PLL_NB; i++) 1658 pll_stop(priv, i); 1659 1660 /* configure HSIDIV */ 1661 debug("configure HSIDIV\n"); 1662 if (priv->osc[_HSI]) { 1663 stm32mp1_hsidiv(rcc, priv->osc[_HSI]); 1664 stgen_config(priv); 1665 } 1666 1667 /* select DIV */ 1668 debug("select DIV\n"); 1669 /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */ 1670 writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR); 1671 set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR); 1672 set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR); 1673 set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR); 1674 set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR); 1675 set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR); 1676 set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR); 1677 set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR); 1678 1679 /* no ready bit for RTC */ 1680 writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR); 1681 1682 /* configure PLLs source */ 1683 debug("configure PLLs source\n"); 1684 set_clksrc(priv, clksrc[CLKSRC_PLL12]); 1685 set_clksrc(priv, clksrc[CLKSRC_PLL3]); 1686 set_clksrc(priv, clksrc[CLKSRC_PLL4]); 1687 1688 /* configure and start PLLs */ 1689 debug("configure PLLs\n"); 1690 for (i = 0; i < _PLL_NB; i++) { 1691 u32 fracv; 1692 u32 csg[PLLCSG_NB]; 1693 1694 debug("configure PLL %d @ %d\n", i, 1695 ofnode_to_offset(plloff[i])); 1696 if (!ofnode_valid(plloff[i])) 1697 continue; 1698 1699 fracv = ofnode_read_u32_default(plloff[i], "frac", 0); 1700 pll_config(priv, i, pllcfg[i], fracv); 1701 ret = ofnode_read_u32_array(plloff[i], "csg", csg, PLLCSG_NB); 1702 if (!ret) { 1703 pll_csg(priv, i, csg); 1704 } else if (ret != -FDT_ERR_NOTFOUND) { 1705 debug("invalid csg node for pll@%d res=%d\n", i, ret); 1706 return ret; 1707 } 1708 pll_start(priv, i); 1709 } 1710 1711 /* wait and start PLLs ouptut when ready */ 1712 for (i = 0; i < _PLL_NB; i++) { 1713 if (!ofnode_valid(plloff[i])) 1714 continue; 1715 debug("output PLL %d\n", i); 1716 pll_output(priv, i, pllcfg[i][PLLCFG_O]); 1717 } 1718 1719 /* wait LSE ready before to use it */ 1720 if (priv->osc[_LSE]) 1721 stm32mp1_lse_wait(rcc); 1722 1723 /* configure with expected clock source */ 1724 debug("CLKSRC\n"); 1725 set_clksrc(priv, clksrc[CLKSRC_MPU]); 1726 set_clksrc(priv, clksrc[CLKSRC_AXI]); 1727 set_clksrc(priv, clksrc[CLKSRC_MCU]); 1728 set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css); 1729 1730 /* configure PKCK */ 1731 debug("PKCK\n"); 1732 pkcs_cell = dev_read_prop(dev, "st,pkcs", &len); 1733 if (pkcs_cell) { 1734 bool ckper_disabled = false; 1735 1736 for (i = 0; i < len / sizeof(u32); i++) { 1737 u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]); 1738 1739 if (pkcs == CLK_CKPER_DISABLED) { 1740 ckper_disabled = true; 1741 continue; 1742 } 1743 pkcs_config(priv, pkcs); 1744 } 1745 /* CKPER is source for some peripheral clock 1746 * (FMC-NAND / QPSI-NOR) and switching source is allowed 1747 * only if previous clock is still ON 1748 * => deactivated CKPER only after switching clock 1749 */ 1750 if (ckper_disabled) 1751 pkcs_config(priv, CLK_CKPER_DISABLED); 1752 } 1753 1754 /* STGEN clock source can change with CLK_STGEN_XXX */ 1755 stgen_config(priv); 1756 1757 debug("oscillator off\n"); 1758 /* switch OFF HSI if not found in device-tree */ 1759 if (!priv->osc[_HSI]) 1760 stm32mp1_hsi_set(rcc, 0); 1761 1762 /* Software Self-Refresh mode (SSR) during DDR initilialization */ 1763 clrsetbits_le32(priv->base + RCC_DDRITFCR, 1764 RCC_DDRITFCR_DDRCKMOD_MASK, 1765 RCC_DDRITFCR_DDRCKMOD_SSR << 1766 RCC_DDRITFCR_DDRCKMOD_SHIFT); 1767 1768 return 0; 1769 } 1770 #endif /* STM32MP1_CLOCK_TREE_INIT */ 1771 1772 static int pll_set_output_rate(struct udevice *dev, 1773 int pll_id, 1774 int div_id, 1775 unsigned long clk_rate) 1776 { 1777 struct stm32mp1_clk_priv *priv = dev_get_priv(dev); 1778 const struct stm32mp1_clk_pll *pll = priv->data->pll; 1779 u32 pllxcr = priv->base + pll[pll_id].pllxcr; 1780 int div; 1781 ulong fvco; 1782 1783 if (div_id > _DIV_NB) 1784 return -EINVAL; 1785 1786 fvco = pll_get_fvco(priv, pll_id); 1787 1788 if (fvco <= clk_rate) 1789 div = 1; 1790 else 1791 div = DIV_ROUND_UP(fvco, clk_rate); 1792 1793 if (div > 128) 1794 div = 128; 1795 1796 debug("fvco = %ld, clk_rate = %ld, div=%d\n", fvco, clk_rate, div); 1797 /* stop the requested output */ 1798 clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT); 1799 /* change divider */ 1800 clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2, 1801 RCC_PLLNCFGR2_DIVX_MASK << RCC_PLLNCFGR2_SHIFT(div_id), 1802 (div - 1) << RCC_PLLNCFGR2_SHIFT(div_id)); 1803 /* start the requested output */ 1804 setbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT); 1805 1806 return 0; 1807 } 1808 1809 static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate) 1810 { 1811 struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev); 1812 int p; 1813 1814 switch (clk->id) { 1815 case LTDC_PX: 1816 case DSI_PX: 1817 break; 1818 default: 1819 pr_err("not supported"); 1820 return -EINVAL; 1821 } 1822 1823 p = stm32mp1_clk_get_parent(priv, clk->id); 1824 if (p < 0) 1825 return -EINVAL; 1826 1827 switch (p) { 1828 case _PLL4_Q: 1829 /* for LTDC_PX and DSI_PX case */ 1830 return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate); 1831 } 1832 1833 return -EINVAL; 1834 } 1835 1836 static void stm32mp1_osc_clk_init(const char *name, 1837 struct stm32mp1_clk_priv *priv, 1838 int index) 1839 { 1840 struct clk clk; 1841 struct udevice *dev = NULL; 1842 1843 priv->osc[index] = 0; 1844 clk.id = 0; 1845 if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) { 1846 if (clk_request(dev, &clk)) 1847 pr_err("%s request", name); 1848 else 1849 priv->osc[index] = clk_get_rate(&clk); 1850 } 1851 priv->osc_dev[index] = dev; 1852 } 1853 1854 static void stm32mp1_osc_init(struct udevice *dev) 1855 { 1856 struct stm32mp1_clk_priv *priv = dev_get_priv(dev); 1857 int i; 1858 const char *name[NB_OSC] = { 1859 [_LSI] = "clk-lsi", 1860 [_LSE] = "clk-lse", 1861 [_HSI] = "clk-hsi", 1862 [_HSE] = "clk-hse", 1863 [_CSI] = "clk-csi", 1864 [_I2S_CKIN] = "i2s_ckin", 1865 }; 1866 1867 for (i = 0; i < NB_OSC; i++) { 1868 stm32mp1_osc_clk_init(name[i], priv, i); 1869 debug("%d: %s => %x\n", i, name[i], (u32)priv->osc[i]); 1870 } 1871 } 1872 1873 static void __maybe_unused stm32mp1_clk_dump(struct stm32mp1_clk_priv *priv) 1874 { 1875 char buf[32]; 1876 int i, s, p; 1877 1878 printf("Clocks:\n"); 1879 for (i = 0; i < _PARENT_NB; i++) { 1880 printf("- %s : %s MHz\n", 1881 stm32mp1_clk_parent_name[i], 1882 strmhz(buf, stm32mp1_clk_get(priv, i))); 1883 } 1884 printf("Source Clocks:\n"); 1885 for (i = 0; i < _PARENT_SEL_NB; i++) { 1886 p = (readl(priv->base + priv->data->sel[i].offset) >> 1887 priv->data->sel[i].src) & priv->data->sel[i].msk; 1888 if (p < priv->data->sel[i].nb_parent) { 1889 s = priv->data->sel[i].parent[p]; 1890 printf("- %s(%d) => parent %s(%d)\n", 1891 stm32mp1_clk_parent_sel_name[i], i, 1892 stm32mp1_clk_parent_name[s], s); 1893 } else { 1894 printf("- %s(%d) => parent index %d is invalid\n", 1895 stm32mp1_clk_parent_sel_name[i], i, p); 1896 } 1897 } 1898 } 1899 1900 #ifdef CONFIG_CMD_CLK 1901 int soc_clk_dump(void) 1902 { 1903 struct udevice *dev; 1904 struct stm32mp1_clk_priv *priv; 1905 int ret; 1906 1907 ret = uclass_get_device_by_driver(UCLASS_CLK, 1908 DM_GET_DRIVER(stm32mp1_clock), 1909 &dev); 1910 if (ret) 1911 return ret; 1912 1913 priv = dev_get_priv(dev); 1914 1915 stm32mp1_clk_dump(priv); 1916 1917 return 0; 1918 } 1919 #endif 1920 1921 static int stm32mp1_clk_probe(struct udevice *dev) 1922 { 1923 int result = 0; 1924 struct stm32mp1_clk_priv *priv = dev_get_priv(dev); 1925 1926 priv->base = dev_read_addr(dev->parent); 1927 if (priv->base == FDT_ADDR_T_NONE) 1928 return -EINVAL; 1929 1930 priv->data = (void *)&stm32mp1_data; 1931 1932 if (!priv->data->gate || !priv->data->sel || 1933 !priv->data->pll) 1934 return -EINVAL; 1935 1936 stm32mp1_osc_init(dev); 1937 1938 #ifdef STM32MP1_CLOCK_TREE_INIT 1939 /* clock tree init is done only one time, before relocation */ 1940 if (!(gd->flags & GD_FLG_RELOC)) 1941 result = stm32mp1_clktree(dev); 1942 #endif 1943 1944 #ifndef CONFIG_SPL_BUILD 1945 #if defined(DEBUG) 1946 /* display debug information for probe after relocation */ 1947 if (gd->flags & GD_FLG_RELOC) 1948 stm32mp1_clk_dump(priv); 1949 #endif 1950 1951 #if defined(CONFIG_DISPLAY_CPUINFO) 1952 if (gd->flags & GD_FLG_RELOC) { 1953 char buf[32]; 1954 1955 printf("Clocks:\n"); 1956 printf("- MPU : %s MHz\n", 1957 strmhz(buf, stm32mp1_clk_get(priv, _CK_MPU))); 1958 printf("- MCU : %s MHz\n", 1959 strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU))); 1960 printf("- AXI : %s MHz\n", 1961 strmhz(buf, stm32mp1_clk_get(priv, _ACLK))); 1962 printf("- PER : %s MHz\n", 1963 strmhz(buf, stm32mp1_clk_get(priv, _CK_PER))); 1964 /* DDRPHYC father */ 1965 printf("- DDR : %s MHz\n", 1966 strmhz(buf, stm32mp1_clk_get(priv, _PLL2_R))); 1967 } 1968 #endif /* CONFIG_DISPLAY_CPUINFO */ 1969 #endif 1970 1971 return result; 1972 } 1973 1974 static const struct clk_ops stm32mp1_clk_ops = { 1975 .enable = stm32mp1_clk_enable, 1976 .disable = stm32mp1_clk_disable, 1977 .get_rate = stm32mp1_clk_get_rate, 1978 .set_rate = stm32mp1_clk_set_rate, 1979 }; 1980 1981 U_BOOT_DRIVER(stm32mp1_clock) = { 1982 .name = "stm32mp1_clk", 1983 .id = UCLASS_CLK, 1984 .ops = &stm32mp1_clk_ops, 1985 .priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv), 1986 .probe = stm32mp1_clk_probe, 1987 }; 1988