1/* 2 * This program is distributed in the hope that it will be useful, 3 * but WITHOUT ANY WARRANTY; without even the implied warranty of 4 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 5 * GNU General Public License for more details. 6 * 7 * You should have received a copy of the GNU General Public License 8 * along with this program; if not, write to the Free Software 9 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 10 */ 11/* 12 * Board specific setup info 13 * 14 ****************************************************************************** 15 * ASPEED Technology Inc. 16 * AST26x0 DDR3/DDR4 SDRAM controller initialization sequence for FPGA 17 * 18 * Version : 2 19 * Release date: 2019.02.19 20 * 21 * Priority of fix item: 22 * [P1] = critical 23 * [P2] = nice to have 24 * [P3] = minor 25 * 26 * Change List : 27 * V0 |2018.03.28 : 1.[P1] Initial release for simulation 28 * 29 * Optional define variable 30 * 1. ECC Function enable 31 * ASTMMC_DRAM_ECC // define to enable ECC function 32 * ASTMMC_DRAM_ECC_SIZE // define the ECC protected memory size 33 * 2. UART5 message output // 34 * ASTMMC_UART_BASE // select UART port base 35 * 3. DRAM Type 36 * ASTMMC_DDR4_8GX8 // DDR4 (16Gb) 8Gbit X8 stacked part 37 ****************************************************************************** 38 */ 39 40#include <config.h> 41#include <version.h> 42#include <asm/secure.h> 43#include <asm/armv7.h> 44 45#ifdef CONFIG_CPU_ARM1176 46#define ASTMMC_DDR_DDR3 47#else 48#define ASTMMC_READ_TRAINING 49#endif 50 51/****************************************************************************** 52 Calibration Macro Start 53 Usable registers: 54 r0, r1, r2, r3, r5, r6, r7, r8, r9, r10, r11 55 ******************************************************************************/ 56#define ASTMMC_INIT_VER 0x02 // 8bit verison number 57#define ASTMMC_INIT_DATE 0x20190219 // Release date 58 59/* PATTERN_TABLE, 60 init_delay_timer, 61 check_delay_timer, 62 clear_delay_timer, 63 print_hex_char, 64 print_hex_byte, 65 print_hex_word, 66 print_hex_dword, 67 are for DRAM calibration */ 68 69#define ASTMMC_UART_BASE 0x1E784000 70 71#ifdef CONFIG_DRAM_ECC 72#define ASTMMC_DRAM_ECC 73#define ASTMMC_DRAM_ECC_SIZE CONFIG_DRAM_ECC_SIZE 74#else 75#define ASTMMC_DRAM_ECC_SIZE 0x0 76#endif 77 78#define ASTMMC_REG_MCR10 0x00 79#define ASTMMC_REG_MCR14 0x04 80#define ASTMMC_REG_MCR18 0x08 81#define ASTMMC_REG_MCR1C 0x0C 82#define ASTMMC_REG_MCR20 0x10 83#define ASTMMC_REG_MCR24 0x14 84#define ASTMMC_REG_MCR28 0x18 85#define ASTMMC_REG_MCR2C 0x1C 86#define ASTMMC_REG_RFC 0x20 87 88TIME_TABLE_DDR3: 89 .word 0x02070306 // MCR10 90 .word 0x05021133 // MCR14 91 .word 0x06010200 // MCR18 92 .word 0x00000020 // MCR1C 93 .word 0x00071320 // MCR20 94 .word 0x00000200 // MCR24 95 .word 0x00000000 // MCR28 96 .word 0x00000000 // MCR2C 97 .word 0x17263434 // MCRFC 98TIME_TABLE_DDR4: 99 .word 0x030C0207 // MCR10 100 .word 0x04451133 // MCR14 101 .word 0x0E010200 // MCR18 102 .word 0x00000140 // MCR1C 103 .word 0x03010100 // MCR20 104 .word 0x00000000 // MCR24 105 .word 0x04C00000 // MCR28 106 .word 0x00000050 // MCR2C 107 .word 0x17263434 // MCRFC 108 109PATTERN_TABLE: 110 .word 0xff00ff00 111 .word 0xcc33cc33 112 .word 0xaa55aa55 113 .word 0x88778877 114 .word 0x92cc4d6e // 5 115 .word 0x543d3cde 116 .word 0xf1e843c7 117 .word 0x7c61d253 118 .word 0x00000000 // 8 119 120 .macro init_delay_timer 121 ldr r0, =0x1e782024 // Set Timer3 Reload 122 str r2, [r0] 123 124 ldr r0, =0x1e782034 // Clear Timer3 ISR 125 ldr r1, =0x00000004 126 str r1, [r0] 127 128 ldr r0, =0x1e782030 // Enable Timer3 129 mov r2, #7 130 mov r1, r2, lsl #8 131 str r1, [r0] 132 133 ldr r0, =0x1e782034 // Check ISR for Timer3 timeout 134 .endm 135 136 .macro check_delay_timer 137 ldr r1, [r0] 138 bic r1, r1, #0xFFFFFFFB 139 mov r2, r1, lsr #2 140 cmp r2, #0x01 141 .endm 142 143 .macro clear_delay_timer 144 ldr r0, =0x1e78203C // Disable Timer3 145 mov r2, #0xF 146 mov r1, r2, lsl #8 147 str r1, [r0] 148 149 ldr r0, =0x1e782034 // Clear Timer3 ISR 150 ldr r1, =0x00000004 151 str r1, [r0] 152 .endm 153 154 .macro print_hex_char 155 and r1, r1, #0xF 156 cmp r1, #9 157 addgt r1, r1, #0x37 158 addle r1, r1, #0x30 159 str r1, [r0] 160 .endm 161 162 .macro print_hex_byte 163 ldr r0, =ASTMMC_UART_BASE 164 mov r1, r2, lsr #4 165 print_hex_char 166 mov r1, r2 167 print_hex_char 168 .endm 169 170 .macro print_hex_word 171 ldr r0, =ASTMMC_UART_BASE 172 mov r1, r2, lsr #12 173 print_hex_char 174 mov r1, r2, lsr #8 175 print_hex_char 176 mov r1, r2, lsr #4 177 print_hex_char 178 mov r1, r2 179 print_hex_char 180 .endm 181 182 .macro print_hex_dword 183 ldr r0, =ASTMMC_UART_BASE 184 mov r1, r2, lsr #28 185 print_hex_char 186 mov r1, r2, lsr #24 187 print_hex_char 188 mov r1, r2, lsr #20 189 print_hex_char 190 mov r1, r2, lsr #16 191 print_hex_char 192 mov r1, r2, lsr #12 193 print_hex_char 194 mov r1, r2, lsr #8 195 print_hex_char 196 mov r1, r2, lsr #4 197 print_hex_char 198 mov r1, r2 199 print_hex_char 200 .endm 201 202/****************************************************************************** 203 Calibration Macro End 204 ******************************************************************************/ 205 206.globl lowlevel_init 207lowlevel_init: 208 209#ifndef CONFIG_CPU_ARM1176 210 /* Put secondary core to sleep */ 211 mrc p15, 0, r0, c0, c0, 5 @; Read CPU ID register 212 ands r0, r0, #0x03 @; Mask off, leaving the CPU ID field 213#ifdef CONFIG_ASPEED_NONSECUR_MODE 214 blne secondary_cpu_init 215#else 216 blne relocate 217 @blne wait_for_kickup 218 b init_uart 219#endif 220 221#if 1 222relocate: 223 adrl r0, wait_for_kickup 224 ldr r1, =0x1000f000 // ; r1 = pointer to destination block 225 mov r2, #0x20 // ; r2 = number of words to copy 226wordcopy: 227 ldr r3, [r0], #4 // ; load a word from the source and 228 str r3, [r1], #4 // ; store it to the destination 229 subs r2, r2, #1 // ; decrement the counter 230 bne wordcopy //1 ; ... copy more 231 232 ldr r0, =0x1E6E2180 233 LDR r1, =0x1e784000 234 ldr r4, =0xABBAADDA 235 ldr r3, =0x1E6E2184 236 237 ldr r5, =0x10000000 238 ldr r6, =0x1000f000 239 str r6, [r5] 240 mov lr, r6 241 mov pc, lr 242#endif 243#endif 244 245init_uart: 246 /* save lr */ 247 mov r4, lr 248 249 /*Initialize the Debug UART here*/ 250 ldr r0, =(ASTMMC_UART_BASE | 0x0c) 251 mov r1, #0x83 252 str r1, [r0] 253 254 ldr r0, =(ASTMMC_UART_BASE | 0x00) 255 mov r1, #0x01 256 str r1, [r0] 257 258 ldr r0, =(ASTMMC_UART_BASE | 0x04) 259 mov r1, #0x00 260 str r1, [r0] 261 262 ldr r0, =(ASTMMC_UART_BASE | 0x0c) 263 mov r1, #0x03 264 str r1, [r0] 265 266 ldr r0, =(ASTMMC_UART_BASE | 0x08) 267 mov r1, #0x07 268 str r1, [r0] 269 270init_dram: 271 272/* Test - DRAM initial time */ 273 ldr r0, =0x1e78203c 274 ldr r1, =0x0000F000 275 str r1, [r0] 276 277 ldr r0, =0x1e782044 278 ldr r1, =0xFFFFFFFF 279 str r1, [r0] 280 281 ldr r0, =0x1e782030 282 ldr r1, =0x00003000 283 str r1, [r0] 284/* Test - DRAM initial time */ 285 286 /*Set Scratch register Bit 7 before initialize*/ 287 ldr r0, =0x1e6e2000 288 ldr r1, =0x1688a8a8 289 str r1, [r0] 290 ldr r0, =0x1e6e2010 291 str r1, [r0] 292 293/* ldr r0, =0x1e6e2100 294 ldr r1, [r0] 295 orr r1, r1, #0x80 296 str r1, [r0] 297*/ 298/****************************************************************************** 299 Disable WDT for SPI Address mode detection function 300 ******************************************************************************/ 301 ldr r0, =0x1e620060 302 mov r1, #0 303 str r1, [r0] 304 305 ldr r0, =0x1e620064 306 mov r1, #0 307 str r1, [r0] 308 309 ldr r0, =0x1e78500c 310 mov r1, #0 311 str r1, [r0] 312 ldr r0, =0x1e78504c 313 str r1, [r0] 314 ldr r0, =0x1e78508c 315 str r1, [r0] 316 ldr r0, =0x1e7850cc 317 str r1, [r0] 318 319#ifdef CONFIG_CPU_ARM1176 320 /* Enable AXI_P */ 321/* ldr r0, =0x00000016 322 mrc p15, 0, r1, c15, c2, 4 323 mcr p15, 0, r0, c15, c2, 4 324*/ 325init_arm11: 326 /* Start of ES40004A PLL init */ 327 /* Step 1. Program PLL_config and keep power down */ 328 ldr r0, =0x33000000 329 ldr r1, =0x01000000 330 str r1, [r0] 331 ldr r1, =0x0102001A @ 324 MHz 332 str r1, [r0] 333 334 /* Step 2. Wait 1us for PLL initialization */ 335 ldr r2, =0x00000100 336delay_ES40004A_pll_init: 337 subs r2, r2, #1 338 bne delay_ES40004A_pll_init 339 340 /* Step 3. Program PLL_config to exit Power down */ 341 ldr r1, =0x0002001A 342 str r1, [r0] 343 344 /* Step 4. Check pll_ld = 1?. Read PLL_config, check bit 27. */ 345 ldr r2, =0x08000000 @ bit[27] PLL lock detection 346check_pll_ld: 347 ldr r1, [r0] 348 tst r1, r2 349 beq check_pll_ld 350 351 /* Step 5. Program aclk_div */ 352 ldr r0, =0x33000004 353 ldr r1, =0x00000007 @ CPU/AXI = 8/1 354 str r1, [r0] 355 356 /* Step 6. Program set_pll */ 357 ldr r1, =0x00010007 358 str r1, [r0] 359 /* End of ES40004A PLL init */ 360#endif 361 362#if 1 363 /* skip SDRAM initialization (will be done in C function) */ 364 b platform_exit 365#else 366 /* Check Scratch Register Bit 6 */ 367 ldr r0, =0x1e6e2100 368 ldr r1, [r0] 369 bic r1, r1, #0xFFFFFFBF 370 mov r2, r1, lsr #6 371 cmp r2, #0x01 372 beq platform_exit 373#endif 374 375ddr_init_start: 376 377/* Debug - UART console message */ 378 ldr r0, =ASTMMC_UART_BASE 379 mov r1, #'\r' // '\r' 380 str r1, [r0] 381 mov r1, #'\n' // '\n' 382 str r1, [r0] 383 mov r1, #'D' // 'D' 384 str r1, [r0] 385 mov r1, #'R' // 'R' 386 str r1, [r0] 387 mov r1, #'A' // 'A' 388 str r1, [r0] 389 mov r1, #'M' // 'M' 390 str r1, [r0] 391 mov r1, #' ' // ' ' 392 str r1, [r0] 393 mov r1, #'I' // 'I' 394 str r1, [r0] 395 mov r1, #'n' // 'n' 396 str r1, [r0] 397 mov r1, #'i' // 'i' 398 str r1, [r0] 399 mov r1, #'t' // 't' 400 str r1, [r0] 401 mov r1, #'-' // '-' 402 str r1, [r0] 403 mov r1, #'V' // 'V' 404 str r1, [r0] 405 mov r2, #ASTMMC_INIT_VER 406 print_hex_byte 407 ldr r0, =(ASTMMC_UART_BASE | 0x14) 408wait_print: 409 ldr r1, [r0] 410 tst r1, #0x40 411 beq wait_print 412 ldr r0, =ASTMMC_UART_BASE 413 mov r1, #'-' // '-' 414 str r1, [r0] 415 mov r1, #'D' // 'D' 416 str r1, [r0] 417 mov r1, #'D' // 'D' 418 str r1, [r0] 419 mov r1, #'R' // 'R' 420 str r1, [r0] 421/* Debug - UART console message */ 422 423 clear_delay_timer 424 425 /* Delay about 5us */ 426 ldr r2, =0x00000005 // Set Timer3 Reload = 5 us 427 init_delay_timer 428delay_0: 429 check_delay_timer 430 bne delay_0 431 clear_delay_timer 432 /* end delay 5us */ 433 434/****************************************************************************** 435 Init DRAM common registers 436 ******************************************************************************/ 437 ldr r0, =0x1e6e0000 438 ldr r1, =0xFC600309 439 str r1, [r0] 440 441 ldr r0, =0x1e6e0034 // disable SDRAM reset 442 ldr r1, =0x000000C0 443 str r1, [r0] 444 445 ldr r0, =0x1e6e0008 446 ldr r1, =0x0044000B /* VGA */ 447 str r1, [r0] 448 449 ldr r0, =0x1e6e0038 450 ldr r1, =0x00100000 451 str r1, [r0] 452 453 ldr r0, =0x1e6e003c 454 ldr r1, =0xFFFFFFFF 455 str r1, [r0] 456 457 ldr r0, =0x1e6e0040 458 ldr r1, =0x88888888 459 str r1, [r0] 460 461 ldr r0, =0x1e6e0044 462 ldr r1, =0x88888888 463 str r1, [r0] 464 465 ldr r0, =0x1e6e0048 466 ldr r1, =0x88888888 467 str r1, [r0] 468 469 ldr r0, =0x1e6e004c 470 ldr r1, =0x88888888 471 str r1, [r0] 472 473 ldr r0, =0x1e6e0050 474 ldr r1, =0x80000000 475 str r1, [r0] 476 477 ldr r0, =0x1e6e0054 478 ldr r1, =ASTMMC_DRAM_ECC_SIZE 479 str r1, [r0] 480 481 ldr r0, =0x1e6e0070 482 ldr r1, =0x00000000 483 str r1, [r0] 484 add r0, #0x4 485 str r1, [r0] 486 add r0, #0x4 487 str r1, [r0] 488 add r0, #0x4 489 str r1, [r0] 490 491 ldr r0, =0x1e6e0080 492 ldr r1, =0xFFFFFFFF 493 str r1, [r0] 494 495 ldr r0, =0x1e6e0084 496 ldr r1, =0x00000000 497 str r1, [r0] 498 499 ldr r0, =0x1e6e0100 500 ldr r1, =0x000000FF 501 str r1, [r0] 502 503 /* Delay about 500us */ 504 ldr r2, =0x000001F4 // Set Timer3 Reload = 500 us 505 init_delay_timer 506ddr3_delay_poweron: 507 check_delay_timer 508 bne ddr3_delay_poweron 509 clear_delay_timer 510 /* end delay 500us */ 511 512 /* Check DRAM Type by H/W Trapping */ 513#ifdef ASTMMC_DDR_DDR3 514 b ddr3_init 515#else 516 ldr r0, =0x1e6e2500 517 ldr r1, [r0] 518 tst r1, #0x20 // bit[5]=1 => DDR3 519 beq ddr4_init 520 b ddr3_init 521#endif 522.LTORG 523 524/****************************************************************************** 525 DDR3 Init 526 ******************************************************************************/ 527ddr3_init: 528/* Debug - UART console message */ 529 ldr r0, =ASTMMC_UART_BASE 530 mov r1, #'3' // '3' 531 str r1, [r0] 532 mov r1, #'\r' // '\r' 533 str r1, [r0] 534 mov r1, #'\n' // '\n' 535 str r1, [r0] 536/* Debug - UART console message */ 537 538 adrl r5, TIME_TABLE_DDR3 // Init DRAM parameter table 539 540 ldr r0, =0x1e6e0004 541 ldr r1, =0x00000006 // 8Gb 542 str r1, [r0] 543 544 ldr r0, =0x1e6e0010 545 mov r2, #0x0 // init loop counter 546 mov r3, r5 547ddr3_init_param: 548 ldr r1, [r3] 549 str r1, [r0] 550 add r0, #0x4 551 add r3, #0x4 552 add r2, #0x1 553 cmp r2, #0x8 554 blt ddr3_init_param 555 556 ldr r0, =0x1e6e0034 // PWRCTL, first time enable CKE, wait at least 200 us 557 ldr r1, =0x000000C1 558 str r1, [r0] 559 560 /* Delay about 500us */ 561 ldr r2, =0x000001F4 // Set Timer3 Reload = 500 us 562 init_delay_timer 563ddr3_delay_cke_on: 564 check_delay_timer 565 bne ddr3_delay_cke_on 566 clear_delay_timer 567 /* end delay 500us */ 568 569 ldr r0, =0x1e6e000c 570 ldr r1, =0x00000040 571 str r1, [r0] 572 573 ldr r0, =0x1e6e0030 574 ldr r1, =0x00000005 // MR2 575 str r1, [r0] 576 ldr r1, =0x00000007 // MR3 577 str r1, [r0] 578 ldr r1, =0x00000003 // MR1 579 str r1, [r0] 580 ldr r1, =0x00000011 // MR0 + DLL_RESET 581 str r1, [r0] 582 583 ldr r0, =0x1e6e000c // REFSET 584 ldr r1, =0x00005D41 585 str r1, [r0] 586 587 ldr r0, =0x1e6e0034 588 ldr r2, =0x70000000 589ddr3_check_dllrdy: 590 ldr r1, [r0] 591 tst r1, r2 592 bne ddr3_check_dllrdy 593 594 ldr r0, =0x1e6e000c 595 ldr r1, =0x40005DA1 596 str r1, [r0] 597 598 ldr r0, =0x1e6e0034 599 ldr r1, =0x000001A3 600 str r1, [r0] 601 602 b Calibration_End 603.LTORG 604/****************************************************************************** 605 End DDR3 Init 606 ******************************************************************************/ 607/****************************************************************************** 608 DDR4 Init 609 ******************************************************************************/ 610ddr4_init: 611/* Debug - UART console message */ 612 ldr r0, =ASTMMC_UART_BASE 613 mov r1, #'4' // '4' 614 str r1, [r0] 615 mov r1, #'\r' // '\r' 616 str r1, [r0] 617 mov r1, #'\n' // '\n' 618 str r1, [r0] 619/* Debug - UART console message */ 620 621 adrl r5, TIME_TABLE_DDR4 // Init DRAM parameter table 622 623 ldr r0, =0x1e6e0004 624#ifdef ASTMMC_DDR4_8GX8 625 ldr r1, =0x00000037 // Init to 16GB 626#else 627 ldr r1, =0x00000017 // Init to 16GB 628#endif 629 str r1, [r0] 630 631 ldr r0, =0x1e6e0010 632 mov r2, #0x0 // init loop counter 633 mov r3, r5 634ddr4_init_param: 635 ldr r1, [r3] 636 str r1, [r0] 637 add r0, #0x4 638 add r3, #0x4 639 add r2, #0x1 640 cmp r2, #0x8 641 blt ddr4_init_param 642 643 ldr r0, =0x1e6e0034 // PWRCTL, 1st enable CKE, wait at least 200 us 644 ldr r1, =0x000000C1 645 str r1, [r0] 646 647 /* Delay about 500us */ 648 ldr r2, =0x000001F4 // Set Timer3 Reload = 500 us 649 init_delay_timer 650ddr4_delay_cke_on: 651 check_delay_timer 652 bne ddr4_delay_cke_on 653 clear_delay_timer 654 /* end delay 500us */ 655 656 ldr r0, =0x1e6e000c 657 ldr r1, =0x00000040 658 str r1, [r0] 659 660 ldr r0, =0x1e6e0030 661 ldr r1, =0x00000007 // MR3 662 str r1, [r0] 663 ldr r1, =0x0000000D // MR6 664 str r1, [r0] 665 ldr r1, =0x0000000B // MR5 666 str r1, [r0] 667 ldr r1, =0x00000009 // MR4 668 str r1, [r0] 669 ldr r1, =0x00000005 // MR2 670 str r1, [r0] 671 ldr r1, =0x00000003 // MR1 672 str r1, [r0] 673 ldr r1, =0x00000011 // MR0 + DLL_RESET 674 str r1, [r0] 675 676 ldr r0, =0x1e6e000c // REFSET 677 ldr r1, =0x00005D41 678 str r1, [r0] 679 680 ldr r0, =0x1e6e0034 681 ldr r2, =0x70000000 682ddr4_check_dllrdy: 683 ldr r1, [r0] 684 tst r1, r2 685 bne ddr4_check_dllrdy 686 687 ldr r0, =0x1e6e000c 688 ldr r1, =0x40005DA1 689 str r1, [r0] 690 691 ldr r0, =0x1e6e0034 692 ldr r1, =0x000001A3 693 str r1, [r0] 694 695 /* Set DDR Vref */ 696 ldr r0, =0x1e6e002c 697 ldr r2, [r0] 698 orr r1, r2, #0x80 699 str r1, [r0] 700 ldr r0, =0x1e6e0030 701 mov r1, #0x1d 702 str r1, [r0] 703 ldr r0, =0x1e6e002c 704 str r2, [r0] 705 ldr r0, =0x1e6e0030 706 mov r1, #0x1d 707 str r1, [r0] 708 709 b Calibration_End 710.LTORG 711/****************************************************************************** 712 Common Process 713 *****************************************************************************/ 714 715/****************************************************************************** 716 Other features configuration 717 *****************************************************************************/ 718Calibration_End: 719 720 mov r10,#0x0 // jump indication 721 722#ifdef ASTMMC_READ_TRAINING 723 /*************************************** 724 Finetune PLL to search the read window 725 Use register r0, r1, r2, r3, r6, r7, r8 726 r9, r10,r11 727 ****************************************/ 728 ldr r0, =0x80000000 729 ldr r1, =0x12345678 730 str r1, [r0] 731 ldr r0, =0x80000004 732 ldr r1, =0xaabbccdd 733 str r1, [r0] 734 735 mov r9, #0x3 // win 736 mov r10,#0x0 // gwin 737 mov r11,#0x0 // gwin PLL margin 738ddr_gate_win_main: 739 tst r9, #0x80 740 bne ddr_gate_win_end 741 ldr r0, =0x1e6e0100 742 str r9, [r0] 743/* Debug - UART console message */ 744 ldr r0, =ASTMMC_UART_BASE 745 mov r1, #'\r' // '\r' 746 str r1, [r0] 747 mov r1, #'\n' // '\n' 748 str r1, [r0] 749 mov r2, r9 750 print_hex_byte 751 mov r1, #'-' // '-' 752 str r1, [r0] 753/* Debug - UART console message */ 754 b search_read_bypass_head 755 756ddr_gate_win_next: 757 mov r9, r9, lsl #1 758 cmp r10,#0x0 759 beq ddr_gate_win_main 760 cmp r7, #0x0 761 bne ddr_gate_win_main 762 763ddr_gate_win_end: 764 mov r9, #0x7 // big win 765 cmp r10,#0x0 766 beq ddr_gate_win_main 767 ldr r0, =0x1e6e0100 768 str r10,[r0] 769 mov r2, r10 770/* Debug - UART console message */ 771 ldr r0, =ASTMMC_UART_BASE 772 mov r1, #'\r' // '\r' 773 str r1, [r0] 774 mov r1, #'\n' // '\n' 775 str r1, [r0] 776 mov r1, #'G' // 'G' 777 str r1, [r0] 778 mov r1, #'W' // 'W' 779 str r1, [r0] 780 mov r1, #'i' // 'i' 781 str r1, [r0] 782 mov r1, #'n' // 'n' 783 str r1, [r0] 784 mov r1, #'=' // '=' 785 str r1, [r0] 786 print_hex_byte 787 mov r1, #'\r' // '\r' 788 str r1, [r0] 789 mov r1, #'\n' // '\n' 790 str r1, [r0] 791 ldr r0, =(ASTMMC_UART_BASE | 0x14) 792wait_print_6: 793 ldr r1, [r0] 794 tst r1, #0x40 795 beq wait_print_6 796/* Debug - UART console message */ 797 798 mov r9, #0x0 // jump indication 799 800search_read_bypass_head: 801 ldr r0, =0x80000000 802 ldr r1, [r0] 803 add r0, r0, #0x4 804 ldr r2, [r0] 805 add r2, r1, r2 806 ldr r1, =0xBCF02355 // 0x12345678 + 0xaabbccdd = 0xbcf02355 807 cmp r1, r2 808 bne search_read_bypass_end 809 ldr r0, =0x1e6e2400 810 ldr r1, =0x303 811 str r1, [r0] 812 ldr r0, =0x1e6e2004 813 ldr r2, =0x00000100 814check_mpll_done_0: 815 ldr r1, [r0] 816 tst r1, r2 817 beq check_mpll_done_0 818 ldr r0, =0x1e6e2400 819 ldr r1, =0x103 820 str r1, [r0] 821 b search_read_bypass_head 822 823search_read_bypass_end: 824 825 ldr r6, =0xFFF // PLL_min 826 ldr r7, =0x0 // PLL_max 827 ldr r3, =0x0 // pll counter 828search_read_main: 829 ldr r0, =0x1e6e2400 830 ldr r1, =0x301 831 str r1, [r0] 832 ldr r0, =0x1e6e2004 833 ldr r2, =0x00000100 834check_mpll_done_1: 835 ldr r1, [r0] 836 tst r1, r2 837 beq check_mpll_done_1 838 ldr r0, =0x1e6e2400 839 ldr r1, =0x101 840 str r1, [r0] 841 842 add r3, r3, #0x1 843 ldr r0, =0x80000000 844 ldr r1, [r0] 845 add r0, r0, #0x4 846 ldr r2, [r0] 847 add r2, r1, r2 848 ldr r1, =0xBCF02355 849 cmp r1, r2 850 bne search_read_main_fail 851 cmp r6, r3 852 movgt r6, r3 853 cmp r7, r3 854 movlt r7, r3 855/* Debug - UART console message */ 856 ldr r0, =(ASTMMC_UART_BASE | 0x14) 857wait_print_3: 858 ldr r1, [r0] 859 tst r1, #0x40 860 beq wait_print_3 861 ldr r0, =ASTMMC_UART_BASE 862 mov r1, #'*' // '*' 863 str r1, [r0] 864/* Debug - UART console message */ 865 b search_read_main 866 867search_read_main_fail: 868 cmp r9, #0x0 869 bne search_read_main_fail_for_gatewin 870 cmp r7, #0x0 871 beq search_read_main 872 sub r2, r7, r6 873/* Debug - UART console message */ 874 ldr r0, =ASTMMC_UART_BASE 875 mov r1, #'E' // 'E' 876 str r1, [r0] 877 print_hex_byte 878 mov r1, #'\r' // '\r' 879 str r1, [r0] 880 mov r1, #'\n' // '\n' 881 str r1, [r0] 882/* Debug - UART console message */ 883 cmp r2, #30 884 bgt search_read_main_pass 885 ldr r6, =0xFFF 886 ldr r7, =0x0 887 b search_read_main 888 889search_read_main_fail_for_gatewin: 890 add r0, r7, #0xFF 891 cmp r3, r0 892 bge ddr_gate_win_next 893 cmp r7, #0x0 894 beq search_read_main 895 sub r2, r7, r6 896 cmp r2, r11 897 movgt r11,r2 898 movgt r10,r9 899 orreq r10,r9, r10 900/* Debug - UART console message */ 901 ldr r0, =ASTMMC_UART_BASE 902 mov r1, #'M' // 'M' 903 str r1, [r0] 904 print_hex_byte 905/* Debug - UART console message */ 906 b ddr_gate_win_next 907 908search_read_main_pass: 909 sub r8, r7, r6 910 mov r8, r8, lsr #1 911 912 ldr r6, =0xFFF // PLL_min 913 ldr r7, =0x0 // PLL_max 914 ldr r3, =0x0 // pll counter 915search_read_main2: 916 add r1, r6, r8 917 cmp r3, r1 918 bge search_read_end 919 ldr r0, =0x1e6e2400 920 ldr r1, =0x301 921 str r1, [r0] 922 ldr r0, =0x1e6e2004 923 ldr r2, =0x00000100 924check_mpll_done_2: 925 ldr r1, [r0] 926 tst r1, r2 927 beq check_mpll_done_2 928 ldr r0, =0x1e6e2400 929 ldr r1, =0x101 930 str r1, [r0] 931 932 add r3, r3, #0x1 933 ldr r0, =0x80000000 934 ldr r1, [r0] 935 add r0, r0, #0x4 936 ldr r2, [r0] 937 add r2, r1, r2 938 ldr r1, =0xBCF02355 939 cmp r1, r2 940 bne search_read_main2_fail 941 cmp r6, r3 942 movgt r6, r3 943 cmp r7, r3 944 movlt r7, r3 945/* Debug - UART console message */ 946 ldr r0, =(ASTMMC_UART_BASE | 0x14) 947wait_print_4: 948 ldr r1, [r0] 949 tst r1, #0x40 950 beq wait_print_4 951 ldr r0, =ASTMMC_UART_BASE 952 mov r1, #'#' // '#' 953 str r1, [r0] 954/* Debug - UART console message */ 955 b search_read_main2 956 957search_read_main2_fail: 958 cmp r7, #0x0 959 beq search_read_main2 960/* Debug - UART console message */ 961 ldr r0, =ASTMMC_UART_BASE 962 mov r1, #'E' // 'E' 963 str r1, [r0] 964 mov r1, #'\r' // '\r' 965 str r1, [r0] 966 mov r1, #'\n' // '\n' 967 str r1, [r0] 968/* Debug - UART console message */ 969 ldr r6, =0xFFF 970 ldr r7, =0x0 971 b search_read_main2 972 973search_read_end: 974/* Debug - UART console message */ 975 ldr r0, =ASTMMC_UART_BASE 976 mov r1, #'\r' // '\r' 977 str r1, [r0] 978 mov r1, #'\n' // '\n' 979 str r1, [r0] 980/* Debug - UART console message */ 981#endif 982 983 /******************************* 984 Check DRAM Size 985 2Gb : 0x80000000 ~ 0x8FFFFFFF 986 4Gb : 0x80000000 ~ 0x9FFFFFFF 987 8Gb : 0x80000000 ~ 0xBFFFFFFF 988 16Gb: 0x80000000 ~ 0xFFFFFFFF 989 *******************************/ 990 ldr r0, =0x1e6e0004 991 ldr r6, [r0] 992 bic r6, r6, #0x00000003 // record MCR04 993 ldr r7, [r5, #ASTMMC_REG_RFC] 994 995check_dram_size: 996 ldr r0, =0xC0100000 997 ldr r1, =0xC1C2C3C4 998 str r1, [r0] 999 ldr r0, =0xA0100000 1000 ldr r1, =0xA1A2A3A4 1001 str r1, [r0] 1002 ldr r0, =0x90100000 1003 ldr r1, =0x91929394 1004 str r1, [r0] 1005 ldr r0, =0x80100000 1006 ldr r1, =0x81828384 1007 str r1, [r0] 1008 ldr r0, =0xC0100000 1009 ldr r1, =0xC1C2C3C4 1010 ldr r2, [r0] 1011 mov r3, #0x16 // '16' 1012 cmp r2, r1 // == 16Gbit 1013 orreq r6, r6, #0x03 1014 beq check_dram_size_end 1015 mov r7, r7, lsr #8 1016 ldr r0, =0xA0100000 1017 ldr r1, =0xA1A2A3A4 1018 ldr r2, [r0] 1019 mov r3, #0x08 // '8' 1020 cmp r2, r1 // == 8Gbit 1021 orreq r6, r6, #0x02 1022 beq check_dram_size_end 1023 mov r7, r7, lsr #8 1024 ldr r0, =0x90100000 1025 ldr r1, =0x91929394 1026 ldr r2, [r0] 1027 mov r3, #0x04 // '4' 1028 cmp r2, r1 // == 4Gbit 1029 orreq r6, r6, #0x01 1030 beq check_dram_size_end 1031 mov r7, r7, lsr #8 // == 2Gbit 1032 mov r3, #0x02 // '2' 1033 1034check_dram_size_end: 1035 ldr r0, =0x1e6e0004 1036 str r6, [r0] 1037 ldr r0, =0x1e6e0014 1038 ldr r1, [r0] 1039 bic r1, r1, #0x000000FF 1040 and r7, r7, #0xFF 1041 orr r1, r1, r7 1042 str r1, [r0] 1043 1044 /* Version Number */ 1045 ldr r0, =0x1e6e0004 1046 ldr r1, [r0] 1047 mov r2, #ASTMMC_INIT_VER 1048 orr r1, r1, r2, lsl #20 1049 str r1, [r0] 1050 1051 ldr r0, =0x1e6e0088 1052 ldr r1, =ASTMMC_INIT_DATE 1053 str r1, [r0] 1054 1055/* Debug - UART console message */ 1056 ldr r0, =ASTMMC_UART_BASE 1057 mov r1, #'S' // 'S' 1058 str r1, [r0] 1059 mov r1, #'i' // 'i' 1060 str r1, [r0] 1061 mov r1, #'z' // 'z' 1062 str r1, [r0] 1063 mov r1, #'e' // 'e' 1064 str r1, [r0] 1065 mov r1, #'-' // '-' 1066 str r1, [r0] 1067 mov r2, r3 1068 print_hex_byte 1069 mov r1, #'G' // 'G' 1070 str r1, [r0] 1071 mov r1, #'b' // 'b' 1072 str r1, [r0] 1073 mov r1, #'\r' // '\r' 1074 str r1, [r0] 1075 mov r1, #'\n' // '\n' 1076 str r1, [r0] 1077 ldr r0, =(ASTMMC_UART_BASE | 0x14) 1078wait_print_2: 1079 ldr r1, [r0] 1080 tst r1, #0x40 1081 beq wait_print_2 1082/* Debug - UART console message */ 1083 1084 mov r9, #0x1 // jump indication 1085 /*************************************** 1086 Search read gating window 1087 Use r7, r8, r9 1088 ****************************************/ 1089 mov r7, #0x3 // win 1090 mov r8, #0x0 // gwin 1091 mov r9, #0x0 // jump indication 1092 1093ddr_gate_train_main: 1094 tst r7, #0x80 1095 bne ddr_gate_train_end 1096 ldr r0, =0x1e6e0100 1097 str r7, [r0] 1098/* Debug - UART console message */ 1099 ldr r0, =ASTMMC_UART_BASE 1100 mov r2, r7 1101 print_hex_byte 1102 mov r1, #'-' // '-' 1103 str r1, [r0] 1104/* Debug - UART console message */ 1105 b ddr_test_start 1106 1107ddr_gate_train_pass: 1108/* Debug - UART console message */ 1109 ldr r0, =ASTMMC_UART_BASE 1110 mov r1, #'P' // 'P' 1111 str r1, [r0] 1112 mov r1, #'a' // 'a' 1113 str r1, [r0] 1114 mov r1, #'s' // 's' 1115 str r1, [r0] 1116 mov r1, #'s' // 's' 1117 str r1, [r0] 1118 mov r1, #'\r' // '\r' 1119 str r1, [r0] 1120 mov r1, #'\n' // '\n' 1121 str r1, [r0] 1122 ldr r0, =(ASTMMC_UART_BASE | 0x14) 1123wait_print_5: 1124 ldr r1, [r0] 1125 tst r1, #0x40 1126 beq wait_print_5 1127/* Debug - UART console message */ 1128 orr r8, r7, r8 1129 mov r7, r7, lsl #1 1130 b ddr_gate_train_main 1131 1132ddr_gate_train_fail: 1133 mov r7, r7, lsl #1 1134 cmp r8, #0x0 1135 beq ddr_gate_train_main 1136 1137ddr_gate_train_end: 1138 mov r7, #0x7 // big win 1139 cmp r8, #0x0 1140 beq ddr_gate_train_main 1141 ldr r0, =0x1e6e0100 1142 str r8, [r0] 1143 1144 /******************************************** 1145 DDRTest 1146 Use r0, r1, r2, r3, r6, r11 1147 ********************************************/ 1148 mov r9, #0x1 // jump indication 1149ddr_test_start: 1150 ldr r0, =0x1e6e0074 1151 ldr r1, =0x0000FFFF // test size = 64KB 1152 str r1, [r0] 1153 ldr r0, =0x1e6e007c 1154 ldr r1, =0xFF00FF00 1155 str r1, [r0] 1156 1157ddr_test_single: 1158 mov r6, #0x00 // initialize loop index, r1 is loop index 1159ddr_test_single_loop: 1160/* Debug - UART console message */ 1161 ldr r0, =ASTMMC_UART_BASE 1162 mov r1, r6 1163 print_hex_char 1164/* Debug - UART console message */ 1165 ldr r0, =0x1e6e0070 1166 ldr r2, =0x00000000 1167 str r2, [r0] 1168 mov r2, r6, lsl #3 1169 orr r2, r2, #0x85 // test command = 0x85 | (datagen << 3) 1170 str r2, [r0] 1171 ldr r3, =0x3000 1172 ldr r11, =0x500000 1173ddr_wait_engine_idle_0: 1174 subs r11, r11, #1 1175 beq ddr_test_fail 1176 ldr r2, [r0] 1177 tst r2, r3 // D[12] = idle bit 1178 beq ddr_wait_engine_idle_0 1179 1180 ldr r0, =0x1e6e0070 // read fail bit status 1181 ldr r3, =0x2000 1182 ldr r2, [r0] 1183 tst r2, r3 // D[13] = fail bit 1184 bne ddr_test_fail 1185 1186 add r6, r6, #1 // increase the test mode index 1187 cmp r6, #0x08 // test 8 modes 1188 bne ddr_test_single_loop 1189 1190ddr_test_burst: 1191 mov r6, #0x00 // initialize loop index, r1 is loop index 1192ddr_test_burst_loop: 1193/* Debug - UART console message */ 1194 ldr r0, =ASTMMC_UART_BASE 1195 mov r1, r6 1196 print_hex_char 1197/* Debug - UART console message */ 1198 ldr r0, =0x1e6e0070 1199 ldr r2, =0x00000000 1200 str r2, [r0] 1201 mov r2, r6, lsl #3 1202 orr r2, r2, #0xC1 // test command = 0xC1 | (datagen << 3) 1203 str r2, [r0] 1204 ldr r3, =0x3000 1205 ldr r11, =0x500000 1206ddr_wait_engine_idle_1: 1207 subs r11, r11, #1 1208 beq ddr_test_fail 1209 ldr r2, [r0] 1210 tst r2, r3 // D[12] = idle bit 1211 beq ddr_wait_engine_idle_1 1212 1213 ldr r0, =0x1e6e0070 // read fail bit status 1214 ldr r3, =0x2000 1215 ldr r2, [r0] 1216 tst r2, r3 // D[13] = fail bit 1217 bne ddr_test_fail 1218 1219 add r6, r6, #1 // increase the test mode index 1220 cmp r6, #0x08 // test 8 modes 1221 bne ddr_test_burst_loop 1222 1223 ldr r0, =0x1e6e0070 1224 ldr r1, =0x00000000 1225 str r1, [r0] 1226 1227 cmp r9, #0x0 1228 beq ddr_gate_train_pass 1229 b set_scratch // CBRTest() return(1) 1230 1231ddr_test_fail: 1232/* Debug - UART console message */ 1233 ldr r0, =ASTMMC_UART_BASE 1234 mov r1, #'F' // 'F' 1235 str r1, [r0] 1236 mov r1, #'a' // 'a' 1237 str r1, [r0] 1238 mov r1, #'i' // 'i' 1239 str r1, [r0] 1240 mov r1, #'l' // 'l' 1241 str r1, [r0] 1242 mov r1, #'\r' // '\r' 1243 str r1, [r0] 1244 mov r1, #'\n' // '\n' 1245 str r1, [r0] 1246 ldr r0, =(ASTMMC_UART_BASE | 0x14) 1247wait_print_1: 1248 ldr r1, [r0] 1249 tst r1, #0x40 1250 beq wait_print_1 1251/* Debug - UART console message */ 1252 cmp r9, #0x0 1253 beq ddr_gate_train_fail 1254 b ddr_init_start 1255 1256set_scratch: 1257 /*Set Scratch register Bit 6 after ddr initial finished */ 1258/* ldr r0, =0x1e6e2100 1259 ldr r1, [r0] 1260 orr r1, r1, #0x41 1261 str r1, [r0] 1262*/ 1263 1264/* Debug - UART console message */ 1265 ldr r0, =ASTMMC_UART_BASE 1266 mov r1, #'D' // 'D' 1267 str r1, [r0] 1268 mov r1, #'o' // 'o' 1269 str r1, [r0] 1270 mov r1, #'n' // 'n' 1271 str r1, [r0] 1272 mov r1, #'e' // 'e' 1273 str r1, [r0] 1274 mov r1, #'\r' // '\r' 1275 str r1, [r0] 1276 mov r1, #'\n' // '\n' 1277 str r1, [r0] 1278/* Debug - UART console message */ 1279 1280#ifdef CONFIG_ASPEED_NONSECUR_MODE 1281 mov r6,pc 1282 bl start_sec 1283#endif 1284 1285platform_exit: 1286 1287#ifdef ASTMMC_DRAM_ECC 1288 ldr r0, =0x1e6e0004 1289 ldr r2, =0x00000280 1290 ldr r1, [r0] 1291 orr r1, r1, r2 1292 str r1, [r0] 1293 1294 ldr r0, =0x1e6e007C 1295 ldr r1, =0x00000000 1296 str r1, [r0] 1297 ldr r0, =0x1e6e0074 1298 str r1, [r0] 1299 1300 ldr r0, =0x1e6e0070 1301 ldr r1, =0x00000221 1302 str r1, [r0] 1303 1304 ldr r2, =0x00001000 1305ECC_Init_Flag: 1306 ldr r1, [r0] 1307 tst r1, r2 @ D[12] = 1, Done 1308 beq ECC_Init_Flag 1309 1310 ldr r1, =0x00000000 1311 str r1, [r0] 1312 1313 ldr r0, =0x1e6e0050 1314 ldr r1, =0x80000000 1315 str r1, [r0] 1316 1317 ldr r0, =0x1e6e0050 1318 ldr r1, =0x40000000 1319 str r1, [r0] 1320#endif 1321 1322 /* restore lr */ 1323 mov lr, r4 1324 1325 /* back to arch calling code */ 1326 mov pc, lr 1327 1328secondary_cpu_init: 1329#ifdef CONFIG_ASPEED_NONSECUR_MODE 1330 mov r6,pc 1331 bl start_sec 1332#endif 1333wait_for_kickup: 1334 wfe 1335 ldr r2,[r3] 1336 cmp r2,r4 1337 bne wait_for_kickup 1338 1339 MOV r2,#'[' 1340 STR r2,[r1] 1341 MOV r2,#'1' 1342 STR r2,[r1] 1343 MOV r2,#'C' 1344 STR r2,[r1] 1345 MOV r2,#'P' 1346 STR r2,[r1] 1347 MOV r2,#'U' 1348 STR r2,[r1] 1349 MOV r2,#']' 1350 STR r2,[r1] 1351 MOV r2,#'\n' 1352 STR r2,[r1] 1353 MOV r2,#'\r' 1354 STR r2,[r1] 1355 ldr pc, [r0] 1356 ldr pc, [r0] 1357 b wait_for_kickup 1358