1// SPDX-License-Identifier: GPL-2.0+ 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3#include "skeleton.dtsi" 4 5/ { 6 model = "Aspeed BMC"; 7 compatible = "aspeed,ast2600"; 8 #address-cells = <1>; 9 #size-cells = <1>; 10 interrupt-parent = <&gic>; 11 12 aliases { 13 i2c0 = &i2c0; 14 i2c1 = &i2c1; 15 i2c2 = &i2c2; 16 i2c3 = &i2c3; 17 i2c4 = &i2c4; 18 i2c5 = &i2c5; 19 i2c6 = &i2c6; 20 i2c7 = &i2c7; 21 i2c8 = &i2c8; 22 i2c9 = &i2c9; 23 i2c10 = &i2c10; 24 i2c11 = &i2c11; 25 i2c12 = &i2c12; 26 i2c13 = &i2c13; 27 i2c14 = &i2c14; 28 i2c15 = &i2c15; 29 serial0 = &uart1; 30 serial1 = &uart2; 31 serial2 = &uart3; 32 serial3 = &uart4; 33 serial4 = &uart5; 34 serial5 = &uart6; 35 serial6 = &uart7; 36 serial7 = &uart8; 37 serial8 = &uart9; 38 serial9 = &uart10; 39 serial10 = &uart11; 40 serial11 = &uart12; 41 serial12 = &uart13; 42 }; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 enable-method = "aspeed,ast2600-smp"; 48 49 cpu@0 { 50 compatible = "arm,cortex-a7"; 51 device_type = "cpu"; 52 reg = <0>; 53 clock-frequency = <48000000>; 54 }; 55 56 cpu@1 { 57 compatible = "arm,cortex-a7"; 58 device_type = "cpu"; 59 reg = <1>; 60 clock-frequency = <48000000>; 61 }; 62 63 }; 64 65 timer { 66 compatible = "arm,armv7-timer"; 67 interrupt-parent = <&gic>; 68 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 69 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 70 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 71 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 72 clock-frequency = <25000000>; 73 }; 74 75 memory@80000000 { 76 device_type = "memory"; 77 reg = <0x80000000 0>; 78 }; 79 80 reserved-memory { 81 #address-cells = <1>; 82 #size-cells = <1>; 83 ranges; 84 85 gfx_memory: framebuffer { 86 size = <0x01000000>; 87 alignment = <0x01000000>; 88 compatible = "shared-dma-pool"; 89 reusable; 90 }; 91 92 video_memory: video { 93 size = <0x04000000>; 94 alignment = <0x01000000>; 95 compatible = "shared-dma-pool"; 96 no-map; 97 }; 98 }; 99 100 ahb { 101 compatible = "simple-bus"; 102 #address-cells = <1>; 103 #size-cells = <1>; 104 device_type = "soc"; 105 ranges; 106 107 gic: interrupt-controller@40461000 { 108 compatible = "arm,cortex-a7-gic"; 109 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 110 #interrupt-cells = <3>; 111 interrupt-controller; 112 interrupt-parent = <&gic>; 113 reg = <0x40461000 0x1000>, 114 <0x40462000 0x1000>, 115 <0x40464000 0x2000>, 116 <0x40466000 0x2000>; 117 }; 118 119 fmc: flash-controller@1e620000 { 120 reg = < 0x1e620000 0xc4 121 0x20000000 0x10000000 >; 122 #address-cells = <1>; 123 #size-cells = <0>; 124 compatible = "aspeed,ast2500-fmc"; 125 status = "disabled"; 126 interrupts = <19>; 127 clocks = <&scu ASPEED_CLK_AHB>; 128 flash@0 { 129 reg = < 0 >; 130 compatible = "jedec,spi-nor"; 131 status = "disabled"; 132 }; 133 flash@1 { 134 reg = < 1 >; 135 compatible = "jedec,spi-nor"; 136 status = "disabled"; 137 }; 138 flash@2 { 139 reg = < 2 >; 140 compatible = "jedec,spi-nor"; 141 status = "disabled"; 142 }; 143 }; 144 145 spi1: flash-controller@1e630000 { 146 reg = < 0x1e630000 0xc4 147 0x30000000 0x08000000 >; 148 #address-cells = <1>; 149 #size-cells = <0>; 150 compatible = "aspeed,ast2500-spi"; 151 clocks = <&scu ASPEED_CLK_AHB>; 152 status = "disabled"; 153 flash@0 { 154 reg = < 0 >; 155 compatible = "jedec,spi-nor"; 156 status = "disabled"; 157 }; 158 flash@1 { 159 reg = < 1 >; 160 compatible = "jedec,spi-nor"; 161 status = "disabled"; 162 }; 163 }; 164 165 spi2: flash-controller@1e631000 { 166 reg = < 0x1e631000 0xc4 167 0x38000000 0x08000000 >; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 compatible = "aspeed,ast2500-spi"; 171 clocks = <&scu ASPEED_CLK_AHB>; 172 status = "disabled"; 173 flash@0 { 174 reg = < 0 >; 175 compatible = "jedec,spi-nor"; 176 status = "disabled"; 177 }; 178 flash@1 { 179 reg = < 1 >; 180 compatible = "jedec,spi-nor"; 181 status = "disabled"; 182 }; 183 }; 184 185 edac: sdram@1e6e0000 { 186 compatible = "aspeed,ast2600-sdram-edac"; 187 reg = <0x1e6e0000 0x174>; 188 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 189 }; 190 191 mdio: ethernet@1e650000 { 192 compatible = "aspeed,aspeed-mdio"; 193 reg = <0x1e650000 0x40>; 194 resets = <&rst ASPEED_RESET_MII>; 195 status = "disabled"; 196 }; 197 198 mac0: ethernet@1e660000 { 199 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 200 reg = <0x1e660000 0x180>, <0x1e650000 0x4>; 201 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 202 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>; 203 status = "disabled"; 204 }; 205 206 mac2: ftgmac@1e670000 { 207 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 208 reg = <0x1e670000 0x180>, <0x1e650010 0x4>; 209 #address-cells = <1>; 210 #size-cells = <0>; 211 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 212 clocks = <&scu ASPEED_CLK_GATE_MAC3CLK>; 213#if 0 214 phy-handle = <&phy0>; 215#endif 216 status = "disabled"; 217 }; 218 219 mac1: ftgmac@1e680000 { 220 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 221 reg = <0x1e680000 0x180>, <0x1e650008 0x4>; 222 #address-cells = <1>; 223 #size-cells = <0>; 224 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 225 clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>; 226#if 0 227 phy-handle = <&phy0>; 228#endif 229 status = "disabled"; 230 }; 231 232 mac3: ftgmac@1e690000 { 233 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 234 reg = <0x1e690000 0x180>, <0x1e650018 0x4>; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&scu ASPEED_CLK_GATE_MAC4CLK>; 239#if 0 240 phy-handle = <&phy0>; 241#endif 242 status = "disabled"; 243 }; 244 245 246 apb { 247 compatible = "simple-bus"; 248 #address-cells = <1>; 249 #size-cells = <1>; 250 ranges; 251 252 syscon: syscon@1e6e2000 { 253 compatible = "aspeed,g6-scu", "syscon", "simple-mfd"; 254 reg = <0x1e6e2000 0x1000>; 255 #address-cells = <1>; 256 #size-cells = <1>; 257 #clock-cells = <1>; 258 #reset-cells = <1>; 259 ranges = <0 0x1e6e2000 0x1000>; 260 261 pinctrl: pinctrl { 262 compatible = "aspeed,g6-pinctrl"; 263 aspeed,external-nodes = <&gfx &lhc>; 264 265 }; 266 267 vga_scratch: scratch { 268 compatible = "aspeed,bmc-misc"; 269 }; 270 271 scu_ic0: interrupt-controller@0 { 272 #interrupt-cells = <1>; 273 compatible = "aspeed,ast2600-scu-ic"; 274 reg = <0x560 0x10>; 275 interrupt-parent = <&gic>; 276 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 277 interrupt-controller; 278 }; 279 280 scu_ic1: interrupt-controller@1 { 281 #interrupt-cells = <1>; 282 compatible = "aspeed,ast2600-scu-ic"; 283 reg = <0x570 0x10>; 284 interrupt-parent = <&gic>; 285 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 286 interrupt-controller; 287 }; 288 289 }; 290 291 smp-memram@0 { 292 compatible = "aspeed,ast2600-smpmem", "syscon"; 293 reg = <0x1e6e2180 0x40>; 294 }; 295 296 gfx: display@1e6e6000 { 297 compatible = "aspeed,ast2500-gfx", "syscon"; 298 reg = <0x1e6e6000 0x1000>; 299 reg-io-width = <4>; 300 }; 301 302 uart1: serial@1e783000 { 303 compatible = "ns16550a"; 304 reg = <0x1e783000 0x20>; 305 reg-shift = <2>; 306 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>; 308 no-loopback-test; 309 status = "disabled"; 310 }; 311 312 uart5: serial@1e784000 { 313 compatible = "ns16550a"; 314 reg = <0x1e784000 0x1000>; 315 reg-shift = <2>; 316 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>; 317 no-loopback-test; 318 }; 319 320 wdt1: watchdog@1e785000 { 321 compatible = "aspeed,ast2600-wdt"; 322 reg = <0x1e785000 0x40>; 323 }; 324 325 wdt2: watchdog@1e785040 { 326 compatible = "aspeed,ast2600-wdt"; 327 reg = <0x1e785040 0x40>; 328 }; 329 330 wdt3: watchdog@1e785080 { 331 compatible = "aspeed,ast2600-wdt"; 332 reg = <0x1e785080 0x40>; 333 }; 334 335 wdt4: watchdog@1e7850C0 { 336 compatible = "aspeed,ast2600-wdt"; 337 reg = <0x1e7850C0 0x40>; 338 }; 339 340 lpc: lpc@1e789000 { 341 compatible = "aspeed,ast-lpc", "simple-mfd", "syscon"; 342 reg = <0x1e789000 0x200>; 343 344 #address-cells = <1>; 345 #size-cells = <1>; 346 ranges = <0x0 0x1e789000 0x1000>; 347 348 lpc_bmc: lpc-bmc@0 { 349 compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon"; 350 reg = <0x0 0x80>; 351 reg-io-width = <4>; 352 #address-cells = <1>; 353 #size-cells = <1>; 354 ranges = <0x0 0x0 0x80>; 355 356 kcs1: kcs1@0 { 357 compatible = "aspeed,ast2600-kcs-bmc"; 358 reg = <0x0 0x80>; 359 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 360 kcs_chan = <1>; 361 kcs_addr = <0xCA0>; 362 status = "disabled"; 363 }; 364 365 kcs2: kcs2@0 { 366 compatible = "aspeed,ast2600-kcs-bmc"; 367 reg = <0x0 0x80>; 368 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 369 kcs_chan = <2>; 370 kcs_addr = <0xCA8>; 371 status = "disabled"; 372 }; 373 374 kcs3: kcs3@0 { 375 compatible = "aspeed,ast2600-kcs-bmc"; 376 reg = <0x0 0x80>; 377 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 378 kcs_chan = <3>; 379 kcs_addr = <0xCA2>; 380 }; 381 382 kcs4: kcs4@0 { 383 compatible = "aspeed,ast2600-kcs-bmc"; 384 reg = <0x0 0x120>; 385 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 386 kcs_chan = <4>; 387 kcs_addr = <0xCA4>; 388 status = "disabled"; 389 }; 390 391 }; 392 393 lpc_host: lpc-host@80 { 394 compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon"; 395 reg = <0x80 0x1e0>; 396 reg-io-width = <4>; 397 398 #address-cells = <1>; 399 #size-cells = <1>; 400 ranges = <0x0 0x80 0x1e0>; 401 402 lpc_ctrl: lpc-ctrl@0 { 403 compatible = "aspeed,ast2600-lpc-ctrl"; 404 reg = <0x0 0x80>; 405 status = "disabled"; 406 }; 407 408 lpc_snoop: lpc-snoop@0 { 409 compatible = "aspeed,ast2600-lpc-snoop"; 410 reg = <0x0 0x80>; 411 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 412 snoop-ports = <0x80>; 413 status = "disabled"; 414 }; 415 416 lhc: lhc@20 { 417 compatible = "aspeed,ast2600-lhc"; 418 reg = <0x20 0x24 0x48 0x8>; 419 }; 420 421 lpc_reset: reset-controller@18 { 422 compatible = "aspeed,ast2600-lpc-reset"; 423 reg = <0x18 0x4>; 424 #reset-cells = <1>; 425 status = "disabled"; 426 }; 427 428 ibt: ibt@c0 { 429 compatible = "aspeed,ast2600-ibt-bmc"; 430 reg = <0xc0 0x18>; 431 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 432 status = "disabled"; 433 }; 434 435 sio_regs: regs { 436 compatible = "aspeed,bmc-misc"; 437 }; 438 439 mbox: mbox@180 { 440 compatible = "aspeed,ast2600-mbox"; 441 reg = <0x180 0x5c>; 442 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 443 #mbox-cells = <1>; 444 status = "disabled"; 445 }; 446 }; 447 }; 448 449 uart2: serial@1e78d000 { 450 compatible = "ns16550a"; 451 reg = <0x1e78d000 0x20>; 452 reg-shift = <2>; 453 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 454 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>; 455 no-loopback-test; 456 status = "disabled"; 457 }; 458 459 uart3: serial@1e78e000 { 460 compatible = "ns16550a"; 461 reg = <0x1e78e000 0x20>; 462 reg-shift = <2>; 463 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 464 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>; 465 no-loopback-test; 466 status = "disabled"; 467 }; 468 469 uart4: serial@1e78f000 { 470 compatible = "ns16550a"; 471 reg = <0x1e78f000 0x20>; 472 reg-shift = <2>; 473 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 474 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>; 475 no-loopback-test; 476 status = "disabled"; 477 }; 478 479 i2c: bus@1e78a000 { 480 compatible = "simple-bus"; 481 #address-cells = <1>; 482 #size-cells = <1>; 483 ranges = <0 0x1e78a000 0x1000>; 484 }; 485 486 uart6: serial@1e790000 { 487 compatible = "ns16550a"; 488 reg = <0x1e790000 0x20>; 489 reg-shift = <2>; 490 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 491 clocks = <&scu ASPEED_CLK_GATE_UART6CLK>; 492 no-loopback-test; 493 status = "disabled"; 494 }; 495 496 uart7: serial@1e790100 { 497 compatible = "ns16550a"; 498 reg = <0x1e790100 0x20>; 499 reg-shift = <2>; 500 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 501 clocks = <&scu ASPEED_CLK_GATE_UART7CLK>; 502 no-loopback-test; 503 status = "disabled"; 504 }; 505 506 uart8: serial@1e790200 { 507 compatible = "ns16550a"; 508 reg = <0x1e790200 0x20>; 509 reg-shift = <2>; 510 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&scu ASPEED_CLK_GATE_UART8CLK>; 512 no-loopback-test; 513 status = "disabled"; 514 }; 515 516 uart9: serial@1e790300 { 517 compatible = "ns16550a"; 518 reg = <0x1e790300 0x20>; 519 reg-shift = <2>; 520 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&scu ASPEED_CLK_GATE_UART9CLK>; 522 no-loopback-test; 523 status = "disabled"; 524 }; 525 526 uart10: serial@1e790400 { 527 compatible = "ns16550a"; 528 reg = <0x1e790400 0x20>; 529 reg-shift = <2>; 530 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 531 clocks = <&scu ASPEED_CLK_GATE_UART10CLK>; 532 no-loopback-test; 533 status = "disabled"; 534 }; 535 536 uart11: serial@1e790500 { 537 compatible = "ns16550a"; 538 reg = <0x1e790400 0x20>; 539 reg-shift = <2>; 540 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&scu ASPEED_CLK_GATE_UART11CLK>; 542 no-loopback-test; 543 status = "disabled"; 544 }; 545 546 uart12: serial@1e790600 { 547 compatible = "ns16550a"; 548 reg = <0x1e790600 0x20>; 549 reg-shift = <2>; 550 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&scu ASPEED_CLK_GATE_UART12CLK>; 552 no-loopback-test; 553 status = "disabled"; 554 }; 555 556 uart13: serial@1e790700 { 557 compatible = "ns16550a"; 558 reg = <0x1e790700 0x20>; 559 reg-shift = <2>; 560 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 561 clocks = <&scu ASPEED_CLK_GATE_UART13CLK>; 562 no-loopback-test; 563 status = "disabled"; 564 }; 565 566 567 568 }; 569 570 }; 571 572}; 573 574&i2c { 575 i2cglobal: i2cg@00 { 576 compatible = "aspeed,ast2600-i2c-global", "syscon", "simple-mfd"; 577 reg = <0x0 0x40>; 578 579#if 0 580 new-mode; 581#endif 582 }; 583 584 i2c0: i2c@80 { 585 #address-cells = <1>; 586 #size-cells = <0>; 587 #interrupt-cells = <1>; 588 589 reg = <0x80 0x80 0xC00 0x20>; 590 compatible = "aspeed,ast2600-i2c-bus"; 591 bus-frequency = <100000>; 592 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 593 clocks = <&scu ASPEED_CLK_APB>; 594 }; 595 596 i2c1: i2c@100 { 597 #address-cells = <1>; 598 #size-cells = <0>; 599 #interrupt-cells = <1>; 600 601 reg = <0x100 0x80 0xC20 0x20>; 602 compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 603 bus-frequency = <100000>; 604 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 605 clocks = <&scu ASPEED_CLK_APB>; 606 }; 607 608 i2c2: i2c@180 { 609 #address-cells = <1>; 610 #size-cells = <0>; 611 #interrupt-cells = <1>; 612 613 reg = <0x180 0x80 0xC40 0x20>; 614 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 615 bus-frequency = <100000>; 616 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 617 clocks = <&scu ASPEED_CLK_APB>; 618 }; 619 620 i2c3: i2c@200 { 621 #address-cells = <1>; 622 #size-cells = <0>; 623 #interrupt-cells = <1>; 624 625 reg = <0x200 0x40 0xC60 0x20>; 626 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 627 bus-frequency = <100000>; 628 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 629 clocks = <&scu ASPEED_CLK_APB>; 630 }; 631 632 i2c4: i2c@280 { 633 #address-cells = <1>; 634 #size-cells = <0>; 635 #interrupt-cells = <1>; 636 637 reg = <0x280 0x80 0xC80 0x20>; 638 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 639 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 640 bus-frequency = <100000>; 641 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&scu ASPEED_CLK_APB>; 643 }; 644 645 i2c5: i2c@300 { 646 #address-cells = <1>; 647 #size-cells = <0>; 648 #interrupt-cells = <1>; 649 650 reg = <0x300 0x40 0xCA0 0x20>; 651 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 652 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 653 bus-frequency = <100000>; 654 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 655 clocks = <&scu ASPEED_CLK_APB>; 656 }; 657 658 i2c6: i2c@380 { 659 #address-cells = <1>; 660 #size-cells = <0>; 661 #interrupt-cells = <1>; 662 663 reg = <0x380 0x80 0xCC0 0x20>; 664 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 665 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 666 bus-frequency = <100000>; 667 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 668 clocks = <&scu ASPEED_CLK_APB>; 669 }; 670 671 i2c7: i2c@400 { 672 #address-cells = <1>; 673 #size-cells = <0>; 674 #interrupt-cells = <1>; 675 676 reg = <0x400 0x80 0xCE0 0x20>; 677 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 678 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 679 bus-frequency = <100000>; 680 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 681 clocks = <&scu ASPEED_CLK_APB>; 682 }; 683 684 i2c8: i2c@480 { 685 #address-cells = <1>; 686 #size-cells = <0>; 687 #interrupt-cells = <1>; 688 689 reg = <0x480 0x80 0xD00 0x20>; 690 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 691 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 692 bus-frequency = <100000>; 693 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 694 clocks = <&scu ASPEED_CLK_APB>; 695 }; 696 697 i2c9: i2c@500 { 698 #address-cells = <1>; 699 #size-cells = <0>; 700 #interrupt-cells = <1>; 701 702 reg = <0x500 0x80 0xD20 0x20>; 703 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 704 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 705 bus-frequency = <100000>; 706 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 707 clocks = <&scu ASPEED_CLK_APB>; 708 status = "disabled"; 709 }; 710 711 i2c10: i2c@580 { 712 #address-cells = <1>; 713 #size-cells = <0>; 714 #interrupt-cells = <1>; 715 716 reg = <0x580 0x80 0xD40 0x20>; 717 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 718 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 719 bus-frequency = <100000>; 720 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&scu ASPEED_CLK_APB>; 722 status = "disabled"; 723 }; 724 725 i2c11: i2c@600 { 726 #address-cells = <1>; 727 #size-cells = <0>; 728 #interrupt-cells = <1>; 729 730 reg = <0x600 0x80 0xD60 0x20>; 731 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 732 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 733 bus-frequency = <100000>; 734 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 735 clocks = <&scu ASPEED_CLK_APB>; 736 status = "disabled"; 737 }; 738 739 i2c12: i2c@680 { 740 #address-cells = <1>; 741 #size-cells = <0>; 742 #interrupt-cells = <1>; 743 744 reg = <0x680 0x80 0xD80 0x20>; 745 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 746 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 747 bus-frequency = <100000>; 748 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&scu ASPEED_CLK_APB>; 750 status = "disabled"; 751 }; 752 753 i2c13: i2c@700 { 754 #address-cells = <1>; 755 #size-cells = <0>; 756 #interrupt-cells = <1>; 757 758 reg = <0x700 0x80 0xDA0 0x20>; 759 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 760 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 761 bus-frequency = <100000>; 762 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 763 clocks = <&scu ASPEED_CLK_APB>; 764 status = "disabled"; 765 }; 766 767 i2c14: i2c@780 { 768 #address-cells = <1>; 769 #size-cells = <0>; 770 #interrupt-cells = <1>; 771 772 reg = <0x780 0x80 0xDC0 0x20>; 773 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 774 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 775 bus-frequency = <100000>; 776 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 777 clocks = <&scu ASPEED_CLK_APB>; 778 status = "disabled"; 779 }; 780 781 i2c15: i2c@800 { 782 #address-cells = <1>; 783 #size-cells = <0>; 784 #interrupt-cells = <1>; 785 786 reg = <0x800 0x80 0xDE0 0x20>; 787 compatible = "aspeed,aspeed-i2c", "aspeed,ast-dma-i2c"; 788 #compatible = "aspeed,ast-g6-i2c", "aspeed,ast-dma-i2c"; 789 bus-frequency = <100000>; 790 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 791 clocks = <&scu ASPEED_CLK_APB>; 792 status = "disabled"; 793 }; 794 795}; 796 797&pinctrl { 798 pinctrl_acpi_default: acpi_default { 799 function = "ACPI"; 800 groups = "ACPI"; 801 }; 802 803 pinctrl_adc0_default: adc0_default { 804 function = "ADC0"; 805 groups = "ADC0"; 806 }; 807 808 pinctrl_adc1_default: adc1_default { 809 function = "ADC1"; 810 groups = "ADC1"; 811 }; 812 813 pinctrl_adc10_default: adc10_default { 814 function = "ADC10"; 815 groups = "ADC10"; 816 }; 817 818 pinctrl_adc11_default: adc11_default { 819 function = "ADC11"; 820 groups = "ADC11"; 821 }; 822 823 pinctrl_adc12_default: adc12_default { 824 function = "ADC12"; 825 groups = "ADC12"; 826 }; 827 828 pinctrl_adc13_default: adc13_default { 829 function = "ADC13"; 830 groups = "ADC13"; 831 }; 832 833 pinctrl_adc14_default: adc14_default { 834 function = "ADC14"; 835 groups = "ADC14"; 836 }; 837 838 pinctrl_adc15_default: adc15_default { 839 function = "ADC15"; 840 groups = "ADC15"; 841 }; 842 843 pinctrl_adc2_default: adc2_default { 844 function = "ADC2"; 845 groups = "ADC2"; 846 }; 847 848 pinctrl_adc3_default: adc3_default { 849 function = "ADC3"; 850 groups = "ADC3"; 851 }; 852 853 pinctrl_adc4_default: adc4_default { 854 function = "ADC4"; 855 groups = "ADC4"; 856 }; 857 858 pinctrl_adc5_default: adc5_default { 859 function = "ADC5"; 860 groups = "ADC5"; 861 }; 862 863 pinctrl_adc6_default: adc6_default { 864 function = "ADC6"; 865 groups = "ADC6"; 866 }; 867 868 pinctrl_adc7_default: adc7_default { 869 function = "ADC7"; 870 groups = "ADC7"; 871 }; 872 873 pinctrl_adc8_default: adc8_default { 874 function = "ADC8"; 875 groups = "ADC8"; 876 }; 877 878 pinctrl_adc9_default: adc9_default { 879 function = "ADC9"; 880 groups = "ADC9"; 881 }; 882 883 pinctrl_bmcint_default: bmcint_default { 884 function = "BMCINT"; 885 groups = "BMCINT"; 886 }; 887 888 pinctrl_ddcclk_default: ddcclk_default { 889 function = "DDCCLK"; 890 groups = "DDCCLK"; 891 }; 892 893 pinctrl_ddcdat_default: ddcdat_default { 894 function = "DDCDAT"; 895 groups = "DDCDAT"; 896 }; 897 898 pinctrl_espi_default: espi_default { 899 function = "ESPI"; 900 groups = "ESPI"; 901 }; 902 903 pinctrl_fwspics1_default: fwspics1_default { 904 function = "FWSPICS1"; 905 groups = "FWSPICS1"; 906 }; 907 908 pinctrl_fwspics2_default: fwspics2_default { 909 function = "FWSPICS2"; 910 groups = "FWSPICS2"; 911 }; 912 913 pinctrl_gpid0_default: gpid0_default { 914 function = "GPID0"; 915 groups = "GPID0"; 916 }; 917 918 pinctrl_gpid2_default: gpid2_default { 919 function = "GPID2"; 920 groups = "GPID2"; 921 }; 922 923 pinctrl_gpid4_default: gpid4_default { 924 function = "GPID4"; 925 groups = "GPID4"; 926 }; 927 928 pinctrl_gpid6_default: gpid6_default { 929 function = "GPID6"; 930 groups = "GPID6"; 931 }; 932 933 pinctrl_gpie0_default: gpie0_default { 934 function = "GPIE0"; 935 groups = "GPIE0"; 936 }; 937 938 pinctrl_gpie2_default: gpie2_default { 939 function = "GPIE2"; 940 groups = "GPIE2"; 941 }; 942 943 pinctrl_gpie4_default: gpie4_default { 944 function = "GPIE4"; 945 groups = "GPIE4"; 946 }; 947 948 pinctrl_gpie6_default: gpie6_default { 949 function = "GPIE6"; 950 groups = "GPIE6"; 951 }; 952 953 pinctrl_i2c10_default: i2c10_default { 954 function = "I2C10"; 955 groups = "I2C10"; 956 }; 957 958 pinctrl_i2c11_default: i2c11_default { 959 function = "I2C11"; 960 groups = "I2C11"; 961 }; 962 963 pinctrl_i2c12_default: i2c12_default { 964 function = "I2C12"; 965 groups = "I2C12"; 966 }; 967 968 pinctrl_i2c13_default: i2c13_default { 969 function = "I2C13"; 970 groups = "I2C13"; 971 }; 972 973 pinctrl_i2c14_default: i2c14_default { 974 function = "I2C14"; 975 groups = "I2C14"; 976 }; 977 978 pinctrl_i2c3_default: i2c3_default { 979 function = "I2C3"; 980 groups = "I2C3"; 981 }; 982 983 pinctrl_i2c4_default: i2c4_default { 984 function = "I2C4"; 985 groups = "I2C4"; 986 }; 987 988 pinctrl_i2c5_default: i2c5_default { 989 function = "I2C5"; 990 groups = "I2C5"; 991 }; 992 993 pinctrl_i2c6_default: i2c6_default { 994 function = "I2C6"; 995 groups = "I2C6"; 996 }; 997 998 pinctrl_i2c7_default: i2c7_default { 999 function = "I2C7"; 1000 groups = "I2C7"; 1001 }; 1002 1003 pinctrl_i2c8_default: i2c8_default { 1004 function = "I2C8"; 1005 groups = "I2C8"; 1006 }; 1007 1008 pinctrl_i2c9_default: i2c9_default { 1009 function = "I2C9"; 1010 groups = "I2C9"; 1011 }; 1012 1013 pinctrl_lad0_default: lad0_default { 1014 function = "LAD0"; 1015 groups = "LAD0"; 1016 }; 1017 1018 pinctrl_lad1_default: lad1_default { 1019 function = "LAD1"; 1020 groups = "LAD1"; 1021 }; 1022 1023 pinctrl_lad2_default: lad2_default { 1024 function = "LAD2"; 1025 groups = "LAD2"; 1026 }; 1027 1028 pinctrl_lad3_default: lad3_default { 1029 function = "LAD3"; 1030 groups = "LAD3"; 1031 }; 1032 1033 pinctrl_lclk_default: lclk_default { 1034 function = "LCLK"; 1035 groups = "LCLK"; 1036 }; 1037 1038 pinctrl_lframe_default: lframe_default { 1039 function = "LFRAME"; 1040 groups = "LFRAME"; 1041 }; 1042 1043 pinctrl_lpchc_default: lpchc_default { 1044 function = "LPCHC"; 1045 groups = "LPCHC"; 1046 }; 1047 1048 pinctrl_lpcpd_default: lpcpd_default { 1049 function = "LPCPD"; 1050 groups = "LPCPD"; 1051 }; 1052 1053 pinctrl_lpcplus_default: lpcplus_default { 1054 function = "LPCPLUS"; 1055 groups = "LPCPLUS"; 1056 }; 1057 1058 pinctrl_lpcpme_default: lpcpme_default { 1059 function = "LPCPME"; 1060 groups = "LPCPME"; 1061 }; 1062 1063 pinctrl_lpcrst_default: lpcrst_default { 1064 function = "LPCRST"; 1065 groups = "LPCRST"; 1066 }; 1067 1068 pinctrl_lpcsmi_default: lpcsmi_default { 1069 function = "LPCSMI"; 1070 groups = "LPCSMI"; 1071 }; 1072 1073 pinctrl_lsirq_default: lsirq_default { 1074 function = "LSIRQ"; 1075 groups = "LSIRQ"; 1076 }; 1077 1078 pinctrl_mac1link_default: mac1link_default { 1079 function = "MAC1LINK"; 1080 groups = "MAC1LINK"; 1081 }; 1082 1083 pinctrl_mac2link_default: mac2link_default { 1084 function = "MAC2LINK"; 1085 groups = "MAC2LINK"; 1086 }; 1087 1088 pinctrl_mac3link_default: mac3link_default { 1089 function = "MAC3LINK"; 1090 groups = "MAC3LINK"; 1091 }; 1092 1093 pinctrl_mac4link_default: mac4link_default { 1094 function = "MAC4LINK"; 1095 groups = "MAC4LINK"; 1096 }; 1097 1098 pinctrl_mdio1_default: mdio1_default { 1099 function = "MDIO1"; 1100 groups = "MDIO1"; 1101 }; 1102 1103 pinctrl_mdio2_default: mdio2_default { 1104 function = "MDIO2"; 1105 groups = "MDIO2"; 1106 }; 1107 1108 pinctrl_mdio3_default: mdio3_default { 1109 function = "MDIO3"; 1110 groups = "MDIO3"; 1111 }; 1112 1113 pinctrl_mdio4_default: mdio4_default { 1114 function = "MDIO4"; 1115 groups = "MDIO4"; 1116 }; 1117 1118 pinctrl_ncts1_default: ncts1_default { 1119 function = "NCTS1"; 1120 groups = "NCTS1"; 1121 }; 1122 1123 pinctrl_ncts2_default: ncts2_default { 1124 function = "NCTS2"; 1125 groups = "NCTS2"; 1126 }; 1127 1128 pinctrl_ncts3_default: ncts3_default { 1129 function = "NCTS3"; 1130 groups = "NCTS3"; 1131 }; 1132 1133 pinctrl_ncts4_default: ncts4_default { 1134 function = "NCTS4"; 1135 groups = "NCTS4"; 1136 }; 1137 1138 pinctrl_ndcd1_default: ndcd1_default { 1139 function = "NDCD1"; 1140 groups = "NDCD1"; 1141 }; 1142 1143 pinctrl_ndcd2_default: ndcd2_default { 1144 function = "NDCD2"; 1145 groups = "NDCD2"; 1146 }; 1147 1148 pinctrl_ndcd3_default: ndcd3_default { 1149 function = "NDCD3"; 1150 groups = "NDCD3"; 1151 }; 1152 1153 pinctrl_ndcd4_default: ndcd4_default { 1154 function = "NDCD4"; 1155 groups = "NDCD4"; 1156 }; 1157 1158 pinctrl_ndsr1_default: ndsr1_default { 1159 function = "NDSR1"; 1160 groups = "NDSR1"; 1161 }; 1162 1163 pinctrl_ndsr2_default: ndsr2_default { 1164 function = "NDSR2"; 1165 groups = "NDSR2"; 1166 }; 1167 1168 pinctrl_ndsr3_default: ndsr3_default { 1169 function = "NDSR3"; 1170 groups = "NDSR3"; 1171 }; 1172 1173 pinctrl_ndsr4_default: ndsr4_default { 1174 function = "NDSR4"; 1175 groups = "NDSR4"; 1176 }; 1177 1178 pinctrl_ndtr1_default: ndtr1_default { 1179 function = "NDTR1"; 1180 groups = "NDTR1"; 1181 }; 1182 1183 pinctrl_ndtr2_default: ndtr2_default { 1184 function = "NDTR2"; 1185 groups = "NDTR2"; 1186 }; 1187 1188 pinctrl_ndtr3_default: ndtr3_default { 1189 function = "NDTR3"; 1190 groups = "NDTR3"; 1191 }; 1192 1193 pinctrl_ndtr4_default: ndtr4_default { 1194 function = "NDTR4"; 1195 groups = "NDTR4"; 1196 }; 1197 1198 pinctrl_nri1_default: nri1_default { 1199 function = "NRI1"; 1200 groups = "NRI1"; 1201 }; 1202 1203 pinctrl_nri2_default: nri2_default { 1204 function = "NRI2"; 1205 groups = "NRI2"; 1206 }; 1207 1208 pinctrl_nri3_default: nri3_default { 1209 function = "NRI3"; 1210 groups = "NRI3"; 1211 }; 1212 1213 pinctrl_nri4_default: nri4_default { 1214 function = "NRI4"; 1215 groups = "NRI4"; 1216 }; 1217 1218 pinctrl_nrts1_default: nrts1_default { 1219 function = "NRTS1"; 1220 groups = "NRTS1"; 1221 }; 1222 1223 pinctrl_nrts2_default: nrts2_default { 1224 function = "NRTS2"; 1225 groups = "NRTS2"; 1226 }; 1227 1228 pinctrl_nrts3_default: nrts3_default { 1229 function = "NRTS3"; 1230 groups = "NRTS3"; 1231 }; 1232 1233 pinctrl_nrts4_default: nrts4_default { 1234 function = "NRTS4"; 1235 groups = "NRTS4"; 1236 }; 1237 1238 pinctrl_oscclk_default: oscclk_default { 1239 function = "OSCCLK"; 1240 groups = "OSCCLK"; 1241 }; 1242 1243 pinctrl_pewake_default: pewake_default { 1244 function = "PEWAKE"; 1245 groups = "PEWAKE"; 1246 }; 1247 1248 pinctrl_pnor_default: pnor_default { 1249 function = "PNOR"; 1250 groups = "PNOR"; 1251 }; 1252 1253 pinctrl_pwm0_default: pwm0_default { 1254 function = "PWM0"; 1255 groups = "PWM0"; 1256 }; 1257 1258 pinctrl_pwm1_default: pwm1_default { 1259 function = "PWM1"; 1260 groups = "PWM1"; 1261 }; 1262 1263 pinctrl_pwm2_default: pwm2_default { 1264 function = "PWM2"; 1265 groups = "PWM2"; 1266 }; 1267 1268 pinctrl_pwm3_default: pwm3_default { 1269 function = "PWM3"; 1270 groups = "PWM3"; 1271 }; 1272 1273 pinctrl_pwm4_default: pwm4_default { 1274 function = "PWM4"; 1275 groups = "PWM4"; 1276 }; 1277 1278 pinctrl_pwm5_default: pwm5_default { 1279 function = "PWM5"; 1280 groups = "PWM5"; 1281 }; 1282 1283 pinctrl_pwm6_default: pwm6_default { 1284 function = "PWM6"; 1285 groups = "PWM6"; 1286 }; 1287 1288 pinctrl_pwm7_default: pwm7_default { 1289 function = "PWM7"; 1290 groups = "PWM7"; 1291 }; 1292 1293 pinctrl_rgmii1_default: rgmii1_default { 1294 function = "RGMII1"; 1295 groups = "RGMII1"; 1296 }; 1297 1298 pinctrl_rgmii2_default: rgmii2_default { 1299 function = "RGMII2"; 1300 groups = "RGMII2"; 1301 }; 1302 1303 pinctrl_rmii1_default: rmii1_default { 1304 function = "RMII1"; 1305 groups = "RMII1"; 1306 }; 1307 1308 pinctrl_rmii2_default: rmii2_default { 1309 function = "RMII2"; 1310 groups = "RMII2"; 1311 }; 1312 1313 pinctrl_rxd1_default: rxd1_default { 1314 function = "RXD1"; 1315 groups = "RXD1"; 1316 }; 1317 1318 pinctrl_rxd2_default: rxd2_default { 1319 function = "RXD2"; 1320 groups = "RXD2"; 1321 }; 1322 1323 pinctrl_rxd3_default: rxd3_default { 1324 function = "RXD3"; 1325 groups = "RXD3"; 1326 }; 1327 1328 pinctrl_rxd4_default: rxd4_default { 1329 function = "RXD4"; 1330 groups = "RXD4"; 1331 }; 1332 1333 pinctrl_salt1_default: salt1_default { 1334 function = "SALT1"; 1335 groups = "SALT1"; 1336 }; 1337 1338 pinctrl_salt10_default: salt10_default { 1339 function = "SALT10"; 1340 groups = "SALT10"; 1341 }; 1342 1343 pinctrl_salt11_default: salt11_default { 1344 function = "SALT11"; 1345 groups = "SALT11"; 1346 }; 1347 1348 pinctrl_salt12_default: salt12_default { 1349 function = "SALT12"; 1350 groups = "SALT12"; 1351 }; 1352 1353 pinctrl_salt13_default: salt13_default { 1354 function = "SALT13"; 1355 groups = "SALT13"; 1356 }; 1357 1358 pinctrl_salt14_default: salt14_default { 1359 function = "SALT14"; 1360 groups = "SALT14"; 1361 }; 1362 1363 pinctrl_salt2_default: salt2_default { 1364 function = "SALT2"; 1365 groups = "SALT2"; 1366 }; 1367 1368 pinctrl_salt3_default: salt3_default { 1369 function = "SALT3"; 1370 groups = "SALT3"; 1371 }; 1372 1373 pinctrl_salt4_default: salt4_default { 1374 function = "SALT4"; 1375 groups = "SALT4"; 1376 }; 1377 1378 pinctrl_salt5_default: salt5_default { 1379 function = "SALT5"; 1380 groups = "SALT5"; 1381 }; 1382 1383 pinctrl_salt6_default: salt6_default { 1384 function = "SALT6"; 1385 groups = "SALT6"; 1386 }; 1387 1388 pinctrl_salt7_default: salt7_default { 1389 function = "SALT7"; 1390 groups = "SALT7"; 1391 }; 1392 1393 pinctrl_salt8_default: salt8_default { 1394 function = "SALT8"; 1395 groups = "SALT8"; 1396 }; 1397 1398 pinctrl_salt9_default: salt9_default { 1399 function = "SALT9"; 1400 groups = "SALT9"; 1401 }; 1402 1403 pinctrl_scl1_default: scl1_default { 1404 function = "SCL1"; 1405 groups = "SCL1"; 1406 }; 1407 1408 pinctrl_scl2_default: scl2_default { 1409 function = "SCL2"; 1410 groups = "SCL2"; 1411 }; 1412 1413 pinctrl_sd1_default: sd1_default { 1414 function = "SD1"; 1415 groups = "SD1"; 1416 }; 1417 1418 pinctrl_sd2_default: sd2_default { 1419 function = "SD2"; 1420 groups = "SD2"; 1421 }; 1422 1423 pinctrl_sda1_default: sda1_default { 1424 function = "SDA1"; 1425 groups = "SDA1"; 1426 }; 1427 1428 pinctrl_sda2_default: sda2_default { 1429 function = "SDA2"; 1430 groups = "SDA2"; 1431 }; 1432 1433 pinctrl_sgps1_default: sgps1_default { 1434 function = "SGPS1"; 1435 groups = "SGPS1"; 1436 }; 1437 1438 pinctrl_sgps2_default: sgps2_default { 1439 function = "SGPS2"; 1440 groups = "SGPS2"; 1441 }; 1442 1443 pinctrl_sioonctrl_default: sioonctrl_default { 1444 function = "SIOONCTRL"; 1445 groups = "SIOONCTRL"; 1446 }; 1447 1448 pinctrl_siopbi_default: siopbi_default { 1449 function = "SIOPBI"; 1450 groups = "SIOPBI"; 1451 }; 1452 1453 pinctrl_siopbo_default: siopbo_default { 1454 function = "SIOPBO"; 1455 groups = "SIOPBO"; 1456 }; 1457 1458 pinctrl_siopwreq_default: siopwreq_default { 1459 function = "SIOPWREQ"; 1460 groups = "SIOPWREQ"; 1461 }; 1462 1463 pinctrl_siopwrgd_default: siopwrgd_default { 1464 function = "SIOPWRGD"; 1465 groups = "SIOPWRGD"; 1466 }; 1467 1468 pinctrl_sios3_default: sios3_default { 1469 function = "SIOS3"; 1470 groups = "SIOS3"; 1471 }; 1472 1473 pinctrl_sios5_default: sios5_default { 1474 function = "SIOS5"; 1475 groups = "SIOS5"; 1476 }; 1477 1478 pinctrl_siosci_default: siosci_default { 1479 function = "SIOSCI"; 1480 groups = "SIOSCI"; 1481 }; 1482 1483 pinctrl_spi1_default: spi1_default { 1484 function = "SPI1"; 1485 groups = "SPI1"; 1486 }; 1487 1488 pinctrl_spi1cs1_default: spi1cs1_default { 1489 function = "SPI1CS1"; 1490 groups = "SPI1CS1"; 1491 }; 1492 1493 pinctrl_spi1debug_default: spi1debug_default { 1494 function = "SPI1DEBUG"; 1495 groups = "SPI1DEBUG"; 1496 }; 1497 1498 pinctrl_spi1passthru_default: spi1passthru_default { 1499 function = "SPI1PASSTHRU"; 1500 groups = "SPI1PASSTHRU"; 1501 }; 1502 1503 pinctrl_spi2ck_default: spi2ck_default { 1504 function = "SPI2CK"; 1505 groups = "SPI2CK"; 1506 }; 1507 1508 pinctrl_spi2cs0_default: spi2cs0_default { 1509 function = "SPI2CS0"; 1510 groups = "SPI2CS0"; 1511 }; 1512 1513 pinctrl_spi2cs1_default: spi2cs1_default { 1514 function = "SPI2CS1"; 1515 groups = "SPI2CS1"; 1516 }; 1517 1518 pinctrl_spi2miso_default: spi2miso_default { 1519 function = "SPI2MISO"; 1520 groups = "SPI2MISO"; 1521 }; 1522 1523 pinctrl_spi2mosi_default: spi2mosi_default { 1524 function = "SPI2MOSI"; 1525 groups = "SPI2MOSI"; 1526 }; 1527 1528 pinctrl_timer3_default: timer3_default { 1529 function = "TIMER3"; 1530 groups = "TIMER3"; 1531 }; 1532 1533 pinctrl_timer4_default: timer4_default { 1534 function = "TIMER4"; 1535 groups = "TIMER4"; 1536 }; 1537 1538 pinctrl_timer5_default: timer5_default { 1539 function = "TIMER5"; 1540 groups = "TIMER5"; 1541 }; 1542 1543 pinctrl_timer6_default: timer6_default { 1544 function = "TIMER6"; 1545 groups = "TIMER6"; 1546 }; 1547 1548 pinctrl_timer7_default: timer7_default { 1549 function = "TIMER7"; 1550 groups = "TIMER7"; 1551 }; 1552 1553 pinctrl_timer8_default: timer8_default { 1554 function = "TIMER8"; 1555 groups = "TIMER8"; 1556 }; 1557 1558 pinctrl_txd1_default: txd1_default { 1559 function = "TXD1"; 1560 groups = "TXD1"; 1561 }; 1562 1563 pinctrl_txd2_default: txd2_default { 1564 function = "TXD2"; 1565 groups = "TXD2"; 1566 }; 1567 1568 pinctrl_txd3_default: txd3_default { 1569 function = "TXD3"; 1570 groups = "TXD3"; 1571 }; 1572 1573 pinctrl_txd4_default: txd4_default { 1574 function = "TXD4"; 1575 groups = "TXD4"; 1576 }; 1577 1578 pinctrl_uart6_default: uart6_default { 1579 function = "UART6"; 1580 groups = "UART6"; 1581 }; 1582 1583 pinctrl_usbcki_default: usbcki_default { 1584 function = "USBCKI"; 1585 groups = "USBCKI"; 1586 }; 1587 1588 pinctrl_usb2ah_default: usb2ah_default { 1589 function = "USB2AH"; 1590 groups = "USB2AH"; 1591 }; 1592 1593 pinctrl_usb11bhid_default: usb11bhid_default { 1594 function = "USB11BHID"; 1595 groups = "USB11BHID"; 1596 }; 1597 1598 pinctrl_usb2bh_default: usb2bh_default { 1599 function = "USB2BH"; 1600 groups = "USB2BH"; 1601 }; 1602 1603 pinctrl_vgabiosrom_default: vgabiosrom_default { 1604 function = "VGABIOSROM"; 1605 groups = "VGABIOSROM"; 1606 }; 1607 1608 pinctrl_vgahs_default: vgahs_default { 1609 function = "VGAHS"; 1610 groups = "VGAHS"; 1611 }; 1612 1613 pinctrl_vgavs_default: vgavs_default { 1614 function = "VGAVS"; 1615 groups = "VGAVS"; 1616 }; 1617 1618 pinctrl_vpi24_default: vpi24_default { 1619 function = "VPI24"; 1620 groups = "VPI24"; 1621 }; 1622 1623 pinctrl_vpo_default: vpo_default { 1624 function = "VPO"; 1625 groups = "VPO"; 1626 }; 1627 1628 pinctrl_wdtrst1_default: wdtrst1_default { 1629 function = "WDTRST1"; 1630 groups = "WDTRST1"; 1631 }; 1632 1633 pinctrl_wdtrst2_default: wdtrst2_default { 1634 function = "WDTRST2"; 1635 groups = "WDTRST2"; 1636 }; 1637}; 1638