1/* 2 * This program is distributed in the hope that it will be useful, 3 * but WITHOUT ANY WARRANTY; without even the implied warranty of 4 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 5 * GNU General Public License for more details. 6 * 7 * You should have received a copy of the GNU General Public License 8 * along with this program; if not, write to the Free Software 9 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 10 */ 11/* 12 * Board specific setup info 13 * 14 ****************************************************************************** 15 * ASPEED Technology Inc. 16 * AST26x0 DDR3/DDR4 SDRAM controller initialization sequence for FPGA 17 * 18 * Version : 2 19 * Release date: 2019.02.19 20 * 21 * Priority of fix item: 22 * [P1] = critical 23 * [P2] = nice to have 24 * [P3] = minor 25 * 26 * Change List : 27 * V0 |2018.03.28 : 1.[P1] Initial release for simulation 28 * 29 * Optional define variable 30 * 1. ECC Function enable 31 * ASTMMC_DRAM_ECC // define to enable ECC function 32 * ASTMMC_DRAM_ECC_SIZE // define the ECC protected memory size 33 * 2. UART5 message output // 34 * ASTMMC_UART_BASE // select UART port base 35 * 3. DRAM Type 36 * ASTMMC_DDR4_8GX8 // DDR4 (16Gb) 8Gbit X8 stacked part 37 ****************************************************************************** 38 */ 39 40#include <config.h> 41#include <version.h> 42#include <asm/secure.h> 43#include <asm/armv7.h> 44 45#ifdef CONFIG_CPU_ARM1176 46#define ASTMMC_DDR_DDR3 47#else 48#define ASTMMC_READ_TRAINING 49#endif 50 51/****************************************************************************** 52 Calibration Macro Start 53 Usable registers: 54 r0, r1, r2, r3, r5, r6, r7, r8, r9, r10, r11 55 ******************************************************************************/ 56#define ASTMMC_INIT_VER 0x02 // 8bit verison number 57#define ASTMMC_INIT_DATE 0x20190219 // Release date 58 59/* PATTERN_TABLE, 60 init_delay_timer, 61 check_delay_timer, 62 clear_delay_timer, 63 print_hex_char, 64 print_hex_byte, 65 print_hex_word, 66 print_hex_dword, 67 are for DRAM calibration */ 68 69#define ASTMMC_UART_BASE 0x1E784000 70 71#ifdef CONFIG_DRAM_ECC 72#define ASTMMC_DRAM_ECC 73#define ASTMMC_DRAM_ECC_SIZE CONFIG_DRAM_ECC_SIZE 74#else 75#define ASTMMC_DRAM_ECC_SIZE 0x0 76#endif 77 78#define ASTMMC_REG_MCR10 0x00 79#define ASTMMC_REG_MCR14 0x04 80#define ASTMMC_REG_MCR18 0x08 81#define ASTMMC_REG_MCR1C 0x0C 82#define ASTMMC_REG_MCR20 0x10 83#define ASTMMC_REG_MCR24 0x14 84#define ASTMMC_REG_MCR28 0x18 85#define ASTMMC_REG_MCR2C 0x1C 86#define ASTMMC_REG_RFC 0x20 87 88TIME_TABLE_DDR3: 89 .word 0x02070306 // MCR10 90 .word 0x05021133 // MCR14 91 .word 0x06010200 // MCR18 92 .word 0x00000020 // MCR1C 93 .word 0x00071320 // MCR20 94 .word 0x00000200 // MCR24 95 .word 0x00000000 // MCR28 96 .word 0x00000000 // MCR2C 97 .word 0x17263434 // MCRFC 98TIME_TABLE_DDR4: 99 .word 0x030C0207 // MCR10 100 .word 0x04451133 // MCR14 101 .word 0x0E010200 // MCR18 102 .word 0x00000140 // MCR1C 103 .word 0x03010100 // MCR20 104 .word 0x00000000 // MCR24 105 .word 0x04C00000 // MCR28 106 .word 0x00000050 // MCR2C 107 .word 0x17263434 // MCRFC 108 109PATTERN_TABLE: 110 .word 0xff00ff00 111 .word 0xcc33cc33 112 .word 0xaa55aa55 113 .word 0x88778877 114 .word 0x92cc4d6e // 5 115 .word 0x543d3cde 116 .word 0xf1e843c7 117 .word 0x7c61d253 118 .word 0x00000000 // 8 119 120 .macro init_delay_timer 121 ldr r0, =0x1e782024 // Set Timer3 Reload 122 str r2, [r0] 123 124 ldr r0, =0x1e782034 // Clear Timer3 ISR 125 ldr r1, =0x00000004 126 str r1, [r0] 127 128 ldr r0, =0x1e782030 // Enable Timer3 129 mov r2, #7 130 mov r1, r2, lsl #8 131 str r1, [r0] 132 133 ldr r0, =0x1e782034 // Check ISR for Timer3 timeout 134 .endm 135 136 .macro check_delay_timer 137 ldr r1, [r0] 138 bic r1, r1, #0xFFFFFFFB 139 mov r2, r1, lsr #2 140 cmp r2, #0x01 141 .endm 142 143 .macro clear_delay_timer 144 ldr r0, =0x1e78203C // Disable Timer3 145 mov r2, #0xF 146 mov r1, r2, lsl #8 147 str r1, [r0] 148 149 ldr r0, =0x1e782034 // Clear Timer3 ISR 150 ldr r1, =0x00000004 151 str r1, [r0] 152 .endm 153 154 .macro print_hex_char 155 and r1, r1, #0xF 156 cmp r1, #9 157 addgt r1, r1, #0x37 158 addle r1, r1, #0x30 159 str r1, [r0] 160 .endm 161 162 .macro print_hex_byte 163 ldr r0, =ASTMMC_UART_BASE 164 mov r1, r2, lsr #4 165 print_hex_char 166 mov r1, r2 167 print_hex_char 168 .endm 169 170 .macro print_hex_word 171 ldr r0, =ASTMMC_UART_BASE 172 mov r1, r2, lsr #12 173 print_hex_char 174 mov r1, r2, lsr #8 175 print_hex_char 176 mov r1, r2, lsr #4 177 print_hex_char 178 mov r1, r2 179 print_hex_char 180 .endm 181 182 .macro print_hex_dword 183 ldr r0, =ASTMMC_UART_BASE 184 mov r1, r2, lsr #28 185 print_hex_char 186 mov r1, r2, lsr #24 187 print_hex_char 188 mov r1, r2, lsr #20 189 print_hex_char 190 mov r1, r2, lsr #16 191 print_hex_char 192 mov r1, r2, lsr #12 193 print_hex_char 194 mov r1, r2, lsr #8 195 print_hex_char 196 mov r1, r2, lsr #4 197 print_hex_char 198 mov r1, r2 199 print_hex_char 200 .endm 201 202/****************************************************************************** 203 Calibration Macro End 204 ******************************************************************************/ 205 206.globl lowlevel_init 207lowlevel_init: 208 209#ifndef CONFIG_CPU_ARM1176 210 /* Put secondary core to sleep */ 211 mrc p15, 0, r0, c0, c0, 5 @; Read CPU ID register 212 ands r0, r0, #0x03 @; Mask off, leaving the CPU ID field 213#ifdef CONFIG_ASPEED_NONSECUR_MODE 214 blne secondary_cpu_init 215#else 216 blne relocate 217 @blne wait_for_kickup 218 b init_uart 219#endif 220 221#if 1 222relocate: 223 adrl r0, wait_for_kickup 224 ldr r1, =0x1000f000 // ; r1 = pointer to destination block 225 mov r2, #0x20 // ; r2 = number of words to copy 226wordcopy: 227 ldr r3, [r0], #4 // ; load a word from the source and 228 str r3, [r1], #4 // ; store it to the destination 229 subs r2, r2, #1 // ; decrement the counter 230 bne wordcopy //1 ; ... copy more 231 232 ldr r0, =0x1E6E2180 233 LDR r1, =0x1e784000 234 ldr r4, =0xABBAADDA 235 ldr r3, =0x1E6E2184 236 237 ldr r5, =0x10000000 238 ldr r6, =0x1000f000 239 str r6, [r5] 240 mov lr, r6 241 mov pc, lr 242#endif 243#endif 244 245init_uart: 246 /* save lr */ 247 mov r4, lr 248 249 /*Initialize the Debug UART here*/ 250 ldr r0, =(ASTMMC_UART_BASE | 0x0c) 251 mov r1, #0x83 252 str r1, [r0] 253 254 ldr r0, =(ASTMMC_UART_BASE | 0x00) 255 mov r1, #0x01 256 str r1, [r0] 257 258 ldr r0, =(ASTMMC_UART_BASE | 0x04) 259 mov r1, #0x00 260 str r1, [r0] 261 262 ldr r0, =(ASTMMC_UART_BASE | 0x0c) 263 mov r1, #0x03 264 str r1, [r0] 265 266 ldr r0, =(ASTMMC_UART_BASE | 0x08) 267 mov r1, #0x07 268 str r1, [r0] 269 270init_dram: 271 272/* Test - DRAM initial time */ 273 ldr r0, =0x1e78203c 274 ldr r1, =0x0000F000 275 str r1, [r0] 276 277 ldr r0, =0x1e782044 278 ldr r1, =0xFFFFFFFF 279 str r1, [r0] 280 281 ldr r0, =0x1e782030 282 ldr r1, =0x00003000 283 str r1, [r0] 284/* Test - DRAM initial time */ 285 286 /*Set Scratch register Bit 7 before initialize*/ 287 ldr r0, =0x1e6e2000 288 ldr r1, =0x1688a8a8 289 str r1, [r0] 290 ldr r0, =0x1e6e2010 291 str r1, [r0] 292 293/* ldr r0, =0x1e6e2100 294 ldr r1, [r0] 295 orr r1, r1, #0x80 296 str r1, [r0] 297*/ 298/****************************************************************************** 299 Disable WDT for SPI Address mode detection function 300 ******************************************************************************/ 301 ldr r0, =0x1e620060 302 mov r1, #0 303 str r1, [r0] 304 305 ldr r0, =0x1e620064 306 mov r1, #0 307 str r1, [r0] 308 309 ldr r0, =0x1e78500c 310 mov r1, #0 311 str r1, [r0] 312 ldr r0, =0x1e78504c 313 str r1, [r0] 314 ldr r0, =0x1e78508c 315 str r1, [r0] 316 ldr r0, =0x1e7850cc 317 str r1, [r0] 318 319#ifdef CONFIG_CPU_ARM1176 320 /* Enable AXI_P */ 321/* ldr r0, =0x00000016 322 mrc p15, 0, r1, c15, c2, 4 323 mcr p15, 0, r0, c15, c2, 4 324*/ 325init_arm11: 326 /* Start of ES40004A PLL init */ 327 /* Step 1. Program PLL_config and keep power down */ 328 ldr r0, =0x33000000 329 ldr r1, =0x01000000 330 str r1, [r0] 331 ldr r1, =0x0102001A @ 324 MHz 332 str r1, [r0] 333 334 /* Step 2. Wait 1us for PLL initialization */ 335 ldr r2, =0x00000100 336delay_ES40004A_pll_init: 337 subs r2, r2, #1 338 bne delay_ES40004A_pll_init 339 340 /* Step 3. Program PLL_config to exit Power down */ 341 ldr r1, =0x0002001A 342 str r1, [r0] 343 344 /* Step 4. Check pll_ld = 1?. Read PLL_config, check bit 27. */ 345 ldr r2, =0x08000000 @ bit[27] PLL lock detection 346check_pll_ld: 347 ldr r1, [r0] 348 tst r1, r2 349 beq check_pll_ld 350 351 /* Step 5. Program aclk_div */ 352 ldr r0, =0x33000004 353 ldr r1, =0x00000007 @ CPU/AXI = 8/1 354 str r1, [r0] 355 356 /* Step 6. Program set_pll */ 357 ldr r1, =0x00010007 358 str r1, [r0] 359 /* End of ES40004A PLL init */ 360#endif 361 362 /* Check Scratch Register Bit 6 */ 363 ldr r0, =0x1e6e2100 364 ldr r1, [r0] 365 bic r1, r1, #0xFFFFFFBF 366 mov r2, r1, lsr #6 367 cmp r2, #0x01 368 beq platform_exit 369 370ddr_init_start: 371 372/* Debug - UART console message */ 373 ldr r0, =ASTMMC_UART_BASE 374 mov r1, #'\r' // '\r' 375 str r1, [r0] 376 mov r1, #'\n' // '\n' 377 str r1, [r0] 378 mov r1, #'D' // 'D' 379 str r1, [r0] 380 mov r1, #'R' // 'R' 381 str r1, [r0] 382 mov r1, #'A' // 'A' 383 str r1, [r0] 384 mov r1, #'M' // 'M' 385 str r1, [r0] 386 mov r1, #' ' // ' ' 387 str r1, [r0] 388 mov r1, #'I' // 'I' 389 str r1, [r0] 390 mov r1, #'n' // 'n' 391 str r1, [r0] 392 mov r1, #'i' // 'i' 393 str r1, [r0] 394 mov r1, #'t' // 't' 395 str r1, [r0] 396 mov r1, #'-' // '-' 397 str r1, [r0] 398 mov r1, #'V' // 'V' 399 str r1, [r0] 400 mov r2, #ASTMMC_INIT_VER 401 print_hex_byte 402 ldr r0, =(ASTMMC_UART_BASE | 0x14) 403wait_print: 404 ldr r1, [r0] 405 tst r1, #0x40 406 beq wait_print 407 ldr r0, =ASTMMC_UART_BASE 408 mov r1, #'-' // '-' 409 str r1, [r0] 410 mov r1, #'D' // 'D' 411 str r1, [r0] 412 mov r1, #'D' // 'D' 413 str r1, [r0] 414 mov r1, #'R' // 'R' 415 str r1, [r0] 416/* Debug - UART console message */ 417 418 clear_delay_timer 419 420 /* Delay about 5us */ 421 ldr r2, =0x00000005 // Set Timer3 Reload = 5 us 422 init_delay_timer 423delay_0: 424 check_delay_timer 425 bne delay_0 426 clear_delay_timer 427 /* end delay 5us */ 428 429/****************************************************************************** 430 Init DRAM common registers 431 ******************************************************************************/ 432 ldr r0, =0x1e6e0000 433 ldr r1, =0xFC600309 434 str r1, [r0] 435 436 ldr r0, =0x1e6e0034 // disable SDRAM reset 437 ldr r1, =0x000000C0 438 str r1, [r0] 439 440 ldr r0, =0x1e6e0008 441 ldr r1, =0x0044000B /* VGA */ 442 str r1, [r0] 443 444 ldr r0, =0x1e6e0038 445 ldr r1, =0x00100000 446 str r1, [r0] 447 448 ldr r0, =0x1e6e003c 449 ldr r1, =0xFFFFFFFF 450 str r1, [r0] 451 452 ldr r0, =0x1e6e0040 453 ldr r1, =0x88888888 454 str r1, [r0] 455 456 ldr r0, =0x1e6e0044 457 ldr r1, =0x88888888 458 str r1, [r0] 459 460 ldr r0, =0x1e6e0048 461 ldr r1, =0x88888888 462 str r1, [r0] 463 464 ldr r0, =0x1e6e004c 465 ldr r1, =0x88888888 466 str r1, [r0] 467 468 ldr r0, =0x1e6e0050 469 ldr r1, =0x80000000 470 str r1, [r0] 471 472 ldr r0, =0x1e6e0054 473 ldr r1, =ASTMMC_DRAM_ECC_SIZE 474 str r1, [r0] 475 476 ldr r0, =0x1e6e0070 477 ldr r1, =0x00000000 478 str r1, [r0] 479 add r0, #0x4 480 str r1, [r0] 481 add r0, #0x4 482 str r1, [r0] 483 add r0, #0x4 484 str r1, [r0] 485 486 ldr r0, =0x1e6e0080 487 ldr r1, =0xFFFFFFFF 488 str r1, [r0] 489 490 ldr r0, =0x1e6e0084 491 ldr r1, =0x00000000 492 str r1, [r0] 493 494 ldr r0, =0x1e6e0100 495 ldr r1, =0x000000FF 496 str r1, [r0] 497 498 /* Delay about 500us */ 499 ldr r2, =0x000001F4 // Set Timer3 Reload = 500 us 500 init_delay_timer 501ddr3_delay_poweron: 502 check_delay_timer 503 bne ddr3_delay_poweron 504 clear_delay_timer 505 /* end delay 500us */ 506 507 /* Check DRAM Type by H/W Trapping */ 508#ifdef ASTMMC_DDR_DDR3 509 b ddr3_init 510#else 511 ldr r0, =0x1e6e2500 512 ldr r1, [r0] 513 tst r1, #0x20 // bit[5]=1 => DDR3 514 beq ddr4_init 515 b ddr3_init 516#endif 517.LTORG 518 519/****************************************************************************** 520 DDR3 Init 521 ******************************************************************************/ 522ddr3_init: 523/* Debug - UART console message */ 524 ldr r0, =ASTMMC_UART_BASE 525 mov r1, #'3' // '3' 526 str r1, [r0] 527 mov r1, #'\r' // '\r' 528 str r1, [r0] 529 mov r1, #'\n' // '\n' 530 str r1, [r0] 531/* Debug - UART console message */ 532 533 adrl r5, TIME_TABLE_DDR3 // Init DRAM parameter table 534 535 ldr r0, =0x1e6e0004 536 ldr r1, =0x00000006 // 8Gb 537 str r1, [r0] 538 539 ldr r0, =0x1e6e0010 540 mov r2, #0x0 // init loop counter 541 mov r3, r5 542ddr3_init_param: 543 ldr r1, [r3] 544 str r1, [r0] 545 add r0, #0x4 546 add r3, #0x4 547 add r2, #0x1 548 cmp r2, #0x8 549 blt ddr3_init_param 550 551 ldr r0, =0x1e6e0034 // PWRCTL, first time enable CKE, wait at least 200 us 552 ldr r1, =0x000000C1 553 str r1, [r0] 554 555 /* Delay about 500us */ 556 ldr r2, =0x000001F4 // Set Timer3 Reload = 500 us 557 init_delay_timer 558ddr3_delay_cke_on: 559 check_delay_timer 560 bne ddr3_delay_cke_on 561 clear_delay_timer 562 /* end delay 500us */ 563 564 ldr r0, =0x1e6e000c 565 ldr r1, =0x00000040 566 str r1, [r0] 567 568 ldr r0, =0x1e6e0030 569 ldr r1, =0x00000005 // MR2 570 str r1, [r0] 571 ldr r1, =0x00000007 // MR3 572 str r1, [r0] 573 ldr r1, =0x00000003 // MR1 574 str r1, [r0] 575 ldr r1, =0x00000011 // MR0 + DLL_RESET 576 str r1, [r0] 577 578 ldr r0, =0x1e6e000c // REFSET 579 ldr r1, =0x00005D41 580 str r1, [r0] 581 582 ldr r0, =0x1e6e0034 583 ldr r2, =0x70000000 584ddr3_check_dllrdy: 585 ldr r1, [r0] 586 tst r1, r2 587 bne ddr3_check_dllrdy 588 589 ldr r0, =0x1e6e000c 590 ldr r1, =0x40005DA1 591 str r1, [r0] 592 593 ldr r0, =0x1e6e0034 594 ldr r1, =0x000001A3 595 str r1, [r0] 596 597 b Calibration_End 598.LTORG 599/****************************************************************************** 600 End DDR3 Init 601 ******************************************************************************/ 602/****************************************************************************** 603 DDR4 Init 604 ******************************************************************************/ 605ddr4_init: 606/* Debug - UART console message */ 607 ldr r0, =ASTMMC_UART_BASE 608 mov r1, #'4' // '4' 609 str r1, [r0] 610 mov r1, #'\r' // '\r' 611 str r1, [r0] 612 mov r1, #'\n' // '\n' 613 str r1, [r0] 614/* Debug - UART console message */ 615 616 adrl r5, TIME_TABLE_DDR4 // Init DRAM parameter table 617 618 ldr r0, =0x1e6e0004 619#ifdef ASTMMC_DDR4_8GX8 620 ldr r1, =0x00000037 // Init to 16GB 621#else 622 ldr r1, =0x00000017 // Init to 16GB 623#endif 624 str r1, [r0] 625 626 ldr r0, =0x1e6e0010 627 mov r2, #0x0 // init loop counter 628 mov r3, r5 629ddr4_init_param: 630 ldr r1, [r3] 631 str r1, [r0] 632 add r0, #0x4 633 add r3, #0x4 634 add r2, #0x1 635 cmp r2, #0x8 636 blt ddr4_init_param 637 638 ldr r0, =0x1e6e0034 // PWRCTL, 1st enable CKE, wait at least 200 us 639 ldr r1, =0x000000C1 640 str r1, [r0] 641 642 /* Delay about 500us */ 643 ldr r2, =0x000001F4 // Set Timer3 Reload = 500 us 644 init_delay_timer 645ddr4_delay_cke_on: 646 check_delay_timer 647 bne ddr4_delay_cke_on 648 clear_delay_timer 649 /* end delay 500us */ 650 651 ldr r0, =0x1e6e000c 652 ldr r1, =0x00000040 653 str r1, [r0] 654 655 ldr r0, =0x1e6e0030 656 ldr r1, =0x00000007 // MR3 657 str r1, [r0] 658 ldr r1, =0x0000000D // MR6 659 str r1, [r0] 660 ldr r1, =0x0000000B // MR5 661 str r1, [r0] 662 ldr r1, =0x00000009 // MR4 663 str r1, [r0] 664 ldr r1, =0x00000005 // MR2 665 str r1, [r0] 666 ldr r1, =0x00000003 // MR1 667 str r1, [r0] 668 ldr r1, =0x00000011 // MR0 + DLL_RESET 669 str r1, [r0] 670 671 ldr r0, =0x1e6e000c // REFSET 672 ldr r1, =0x00005D41 673 str r1, [r0] 674 675 ldr r0, =0x1e6e0034 676 ldr r2, =0x70000000 677ddr4_check_dllrdy: 678 ldr r1, [r0] 679 tst r1, r2 680 bne ddr4_check_dllrdy 681 682 ldr r0, =0x1e6e000c 683 ldr r1, =0x40005DA1 684 str r1, [r0] 685 686 ldr r0, =0x1e6e0034 687 ldr r1, =0x000001A3 688 str r1, [r0] 689 690 /* Set DDR Vref */ 691 ldr r0, =0x1e6e002c 692 ldr r2, [r0] 693 orr r1, r2, #0x80 694 str r1, [r0] 695 ldr r0, =0x1e6e0030 696 mov r1, #0x1d 697 str r1, [r0] 698 ldr r0, =0x1e6e002c 699 str r2, [r0] 700 ldr r0, =0x1e6e0030 701 mov r1, #0x1d 702 str r1, [r0] 703 704 b Calibration_End 705.LTORG 706/****************************************************************************** 707 Common Process 708 *****************************************************************************/ 709 710/****************************************************************************** 711 Other features configuration 712 *****************************************************************************/ 713Calibration_End: 714 715 mov r10,#0x0 // jump indication 716 717#ifdef ASTMMC_READ_TRAINING 718 /*************************************** 719 Finetune PLL to search the read window 720 Use register r0, r1, r2, r3, r6, r7, r8 721 r9, r10,r11 722 ****************************************/ 723 ldr r0, =0x80000000 724 ldr r1, =0x12345678 725 str r1, [r0] 726 ldr r0, =0x80000004 727 ldr r1, =0xaabbccdd 728 str r1, [r0] 729 730 mov r9, #0x3 // win 731 mov r10,#0x0 // gwin 732 mov r11,#0x0 // gwin PLL margin 733ddr_gate_win_main: 734 tst r9, #0x80 735 bne ddr_gate_win_end 736 ldr r0, =0x1e6e0100 737 str r9, [r0] 738/* Debug - UART console message */ 739 ldr r0, =ASTMMC_UART_BASE 740 mov r1, #'\r' // '\r' 741 str r1, [r0] 742 mov r1, #'\n' // '\n' 743 str r1, [r0] 744 mov r2, r9 745 print_hex_byte 746 mov r1, #'-' // '-' 747 str r1, [r0] 748/* Debug - UART console message */ 749 b search_read_bypass_head 750 751ddr_gate_win_next: 752 mov r9, r9, lsl #1 753 cmp r10,#0x0 754 beq ddr_gate_win_main 755 cmp r7, #0x0 756 bne ddr_gate_win_main 757 758ddr_gate_win_end: 759 mov r9, #0x7 // big win 760 cmp r10,#0x0 761 beq ddr_gate_win_main 762 ldr r0, =0x1e6e0100 763 str r10,[r0] 764 mov r2, r10 765/* Debug - UART console message */ 766 ldr r0, =ASTMMC_UART_BASE 767 mov r1, #'\r' // '\r' 768 str r1, [r0] 769 mov r1, #'\n' // '\n' 770 str r1, [r0] 771 mov r1, #'G' // 'G' 772 str r1, [r0] 773 mov r1, #'W' // 'W' 774 str r1, [r0] 775 mov r1, #'i' // 'i' 776 str r1, [r0] 777 mov r1, #'n' // 'n' 778 str r1, [r0] 779 mov r1, #'=' // '=' 780 str r1, [r0] 781 print_hex_byte 782 mov r1, #'\r' // '\r' 783 str r1, [r0] 784 mov r1, #'\n' // '\n' 785 str r1, [r0] 786 ldr r0, =(ASTMMC_UART_BASE | 0x14) 787wait_print_6: 788 ldr r1, [r0] 789 tst r1, #0x40 790 beq wait_print_6 791/* Debug - UART console message */ 792 793 mov r9, #0x0 // jump indication 794 795search_read_bypass_head: 796 ldr r0, =0x80000000 797 ldr r1, [r0] 798 add r0, r0, #0x4 799 ldr r2, [r0] 800 add r2, r1, r2 801 ldr r1, =0xBCF02355 802 cmp r1, r2 803 bne search_read_bypass_end 804 ldr r0, =0x1e6e2400 805 ldr r1, =0x303 806 str r1, [r0] 807 ldr r0, =0x1e6e2004 808 ldr r2, =0x00000100 809check_mpll_done_0: 810 ldr r1, [r0] 811 tst r1, r2 812 beq check_mpll_done_0 813 ldr r0, =0x1e6e2400 814 ldr r1, =0x103 815 str r1, [r0] 816 b search_read_bypass_head 817 818search_read_bypass_end: 819 820 ldr r6, =0xFFF // PLL_min 821 ldr r7, =0x0 // PLL_max 822 ldr r3, =0x0 // pll counter 823search_read_main: 824 ldr r0, =0x1e6e2400 825 ldr r1, =0x301 826 str r1, [r0] 827 ldr r0, =0x1e6e2004 828 ldr r2, =0x00000100 829check_mpll_done_1: 830 ldr r1, [r0] 831 tst r1, r2 832 beq check_mpll_done_1 833 ldr r0, =0x1e6e2400 834 ldr r1, =0x101 835 str r1, [r0] 836 837 add r3, r3, #0x1 838 ldr r0, =0x80000000 839 ldr r1, [r0] 840 add r0, r0, #0x4 841 ldr r2, [r0] 842 add r2, r1, r2 843 ldr r1, =0xBCF02355 844 cmp r1, r2 845 bne search_read_main_fail 846 cmp r6, r3 847 movgt r6, r3 848 cmp r7, r3 849 movlt r7, r3 850/* Debug - UART console message */ 851 ldr r0, =(ASTMMC_UART_BASE | 0x14) 852wait_print_3: 853 ldr r1, [r0] 854 tst r1, #0x40 855 beq wait_print_3 856 ldr r0, =ASTMMC_UART_BASE 857 mov r1, #'*' // '*' 858 str r1, [r0] 859/* Debug - UART console message */ 860 b search_read_main 861 862search_read_main_fail: 863 cmp r9, #0x0 864 bne search_read_main_fail_for_gatewin 865 cmp r7, #0x0 866 beq search_read_main 867 sub r2, r7, r6 868/* Debug - UART console message */ 869 ldr r0, =ASTMMC_UART_BASE 870 mov r1, #'E' // 'E' 871 str r1, [r0] 872 print_hex_byte 873 mov r1, #'\r' // '\r' 874 str r1, [r0] 875 mov r1, #'\n' // '\n' 876 str r1, [r0] 877/* Debug - UART console message */ 878 cmp r2, #30 879 bgt search_read_main_pass 880 ldr r6, =0xFFF 881 ldr r7, =0x0 882 b search_read_main 883 884search_read_main_fail_for_gatewin: 885 add r0, r7, #0xFF 886 cmp r3, r0 887 bge ddr_gate_win_next 888 cmp r7, #0x0 889 beq search_read_main 890 sub r2, r7, r6 891 cmp r2, r11 892 movgt r11,r2 893 movgt r10,r9 894 orreq r10,r9, r10 895/* Debug - UART console message */ 896 ldr r0, =ASTMMC_UART_BASE 897 mov r1, #'M' // 'M' 898 str r1, [r0] 899 print_hex_byte 900/* Debug - UART console message */ 901 b ddr_gate_win_next 902 903search_read_main_pass: 904 sub r8, r7, r6 905 mov r8, r8, lsr #1 906 907 ldr r6, =0xFFF // PLL_min 908 ldr r7, =0x0 // PLL_max 909 ldr r3, =0x0 // pll counter 910search_read_main2: 911 add r1, r6, r8 912 cmp r3, r1 913 bge search_read_end 914 ldr r0, =0x1e6e2400 915 ldr r1, =0x301 916 str r1, [r0] 917 ldr r0, =0x1e6e2004 918 ldr r2, =0x00000100 919check_mpll_done_2: 920 ldr r1, [r0] 921 tst r1, r2 922 beq check_mpll_done_2 923 ldr r0, =0x1e6e2400 924 ldr r1, =0x101 925 str r1, [r0] 926 927 add r3, r3, #0x1 928 ldr r0, =0x80000000 929 ldr r1, [r0] 930 add r0, r0, #0x4 931 ldr r2, [r0] 932 add r2, r1, r2 933 ldr r1, =0xBCF02355 934 cmp r1, r2 935 bne search_read_main2_fail 936 cmp r6, r3 937 movgt r6, r3 938 cmp r7, r3 939 movlt r7, r3 940/* Debug - UART console message */ 941 ldr r0, =(ASTMMC_UART_BASE | 0x14) 942wait_print_4: 943 ldr r1, [r0] 944 tst r1, #0x40 945 beq wait_print_4 946 ldr r0, =ASTMMC_UART_BASE 947 mov r1, #'#' // '#' 948 str r1, [r0] 949/* Debug - UART console message */ 950 b search_read_main2 951 952search_read_main2_fail: 953 cmp r7, #0x0 954 beq search_read_main2 955/* Debug - UART console message */ 956 ldr r0, =ASTMMC_UART_BASE 957 mov r1, #'E' // 'E' 958 str r1, [r0] 959 mov r1, #'\r' // '\r' 960 str r1, [r0] 961 mov r1, #'\n' // '\n' 962 str r1, [r0] 963/* Debug - UART console message */ 964 ldr r6, =0xFFF 965 ldr r7, =0x0 966 b search_read_main2 967 968search_read_end: 969/* Debug - UART console message */ 970 ldr r0, =ASTMMC_UART_BASE 971 mov r1, #'\r' // '\r' 972 str r1, [r0] 973 mov r1, #'\n' // '\n' 974 str r1, [r0] 975/* Debug - UART console message */ 976#endif 977 978 /******************************* 979 Check DRAM Size 980 2Gb : 0x80000000 ~ 0x8FFFFFFF 981 4Gb : 0x80000000 ~ 0x9FFFFFFF 982 8Gb : 0x80000000 ~ 0xBFFFFFFF 983 16Gb: 0x80000000 ~ 0xFFFFFFFF 984 *******************************/ 985 ldr r0, =0x1e6e0004 986 ldr r6, [r0] 987 bic r6, r6, #0x00000003 // record MCR04 988 ldr r7, [r5, #ASTMMC_REG_RFC] 989 990check_dram_size: 991 ldr r0, =0xC0100000 992 ldr r1, =0xC1C2C3C4 993 str r1, [r0] 994 ldr r0, =0xA0100000 995 ldr r1, =0xA1A2A3A4 996 str r1, [r0] 997 ldr r0, =0x90100000 998 ldr r1, =0x91929394 999 str r1, [r0] 1000 ldr r0, =0x80100000 1001 ldr r1, =0x81828384 1002 str r1, [r0] 1003 ldr r0, =0xC0100000 1004 ldr r1, =0xC1C2C3C4 1005 ldr r2, [r0] 1006 mov r3, #0x16 // '16' 1007 cmp r2, r1 // == 16Gbit 1008 orreq r6, r6, #0x03 1009 beq check_dram_size_end 1010 mov r7, r7, lsr #8 1011 ldr r0, =0xA0100000 1012 ldr r1, =0xA1A2A3A4 1013 ldr r2, [r0] 1014 mov r3, #0x08 // '8' 1015 cmp r2, r1 // == 8Gbit 1016 orreq r6, r6, #0x02 1017 beq check_dram_size_end 1018 mov r7, r7, lsr #8 1019 ldr r0, =0x90100000 1020 ldr r1, =0x91929394 1021 ldr r2, [r0] 1022 mov r3, #0x04 // '4' 1023 cmp r2, r1 // == 4Gbit 1024 orreq r6, r6, #0x01 1025 beq check_dram_size_end 1026 mov r7, r7, lsr #8 // == 2Gbit 1027 mov r3, #0x02 // '2' 1028 1029check_dram_size_end: 1030 ldr r0, =0x1e6e0004 1031 str r6, [r0] 1032 ldr r0, =0x1e6e0014 1033 ldr r1, [r0] 1034 bic r1, r1, #0x000000FF 1035 and r7, r7, #0xFF 1036 orr r1, r1, r7 1037 str r1, [r0] 1038 1039 /* Version Number */ 1040 ldr r0, =0x1e6e0004 1041 ldr r1, [r0] 1042 mov r2, #ASTMMC_INIT_VER 1043 orr r1, r1, r2, lsl #20 1044 str r1, [r0] 1045 1046 ldr r0, =0x1e6e0088 1047 ldr r1, =ASTMMC_INIT_DATE 1048 str r1, [r0] 1049 1050/* Debug - UART console message */ 1051 ldr r0, =ASTMMC_UART_BASE 1052 mov r1, #'S' // 'S' 1053 str r1, [r0] 1054 mov r1, #'i' // 'i' 1055 str r1, [r0] 1056 mov r1, #'z' // 'z' 1057 str r1, [r0] 1058 mov r1, #'e' // 'e' 1059 str r1, [r0] 1060 mov r1, #'-' // '-' 1061 str r1, [r0] 1062 mov r2, r3 1063 print_hex_byte 1064 mov r1, #'G' // 'G' 1065 str r1, [r0] 1066 mov r1, #'b' // 'b' 1067 str r1, [r0] 1068 mov r1, #'\r' // '\r' 1069 str r1, [r0] 1070 mov r1, #'\n' // '\n' 1071 str r1, [r0] 1072 ldr r0, =(ASTMMC_UART_BASE | 0x14) 1073wait_print_2: 1074 ldr r1, [r0] 1075 tst r1, #0x40 1076 beq wait_print_2 1077/* Debug - UART console message */ 1078 1079 mov r9, #0x1 // jump indication 1080 /*************************************** 1081 Search read gating window 1082 Use r7, r8, r9 1083 ****************************************/ 1084 mov r7, #0x3 // win 1085 mov r8, #0x0 // gwin 1086 mov r9, #0x0 // jump indication 1087 1088ddr_gate_train_main: 1089 tst r7, #0x80 1090 bne ddr_gate_train_end 1091 ldr r0, =0x1e6e0100 1092 str r7, [r0] 1093/* Debug - UART console message */ 1094 ldr r0, =ASTMMC_UART_BASE 1095 mov r2, r7 1096 print_hex_byte 1097 mov r1, #'-' // '-' 1098 str r1, [r0] 1099/* Debug - UART console message */ 1100 b ddr_test_start 1101 1102ddr_gate_train_pass: 1103/* Debug - UART console message */ 1104 ldr r0, =ASTMMC_UART_BASE 1105 mov r1, #'P' // 'P' 1106 str r1, [r0] 1107 mov r1, #'a' // 'a' 1108 str r1, [r0] 1109 mov r1, #'s' // 's' 1110 str r1, [r0] 1111 mov r1, #'s' // 's' 1112 str r1, [r0] 1113 mov r1, #'\r' // '\r' 1114 str r1, [r0] 1115 mov r1, #'\n' // '\n' 1116 str r1, [r0] 1117 ldr r0, =(ASTMMC_UART_BASE | 0x14) 1118wait_print_5: 1119 ldr r1, [r0] 1120 tst r1, #0x40 1121 beq wait_print_5 1122/* Debug - UART console message */ 1123 orr r8, r7, r8 1124 mov r7, r7, lsl #1 1125 b ddr_gate_train_main 1126 1127ddr_gate_train_fail: 1128 mov r7, r7, lsl #1 1129 cmp r8, #0x0 1130 beq ddr_gate_train_main 1131 1132ddr_gate_train_end: 1133 mov r7, #0x7 // big win 1134 cmp r8, #0x0 1135 beq ddr_gate_train_main 1136 ldr r0, =0x1e6e0100 1137 str r8, [r0] 1138 1139 /******************************************** 1140 DDRTest 1141 Use r0, r1, r2, r3, r6, r11 1142 ********************************************/ 1143 mov r9, #0x1 // jump indication 1144ddr_test_start: 1145 ldr r0, =0x1e6e0074 1146 ldr r1, =0x0000FFFF // test size = 64KB 1147 str r1, [r0] 1148 ldr r0, =0x1e6e007c 1149 ldr r1, =0xFF00FF00 1150 str r1, [r0] 1151 1152ddr_test_single: 1153 mov r6, #0x00 // initialize loop index, r1 is loop index 1154ddr_test_single_loop: 1155/* Debug - UART console message */ 1156 ldr r0, =ASTMMC_UART_BASE 1157 mov r1, r6 1158 print_hex_char 1159/* Debug - UART console message */ 1160 ldr r0, =0x1e6e0070 1161 ldr r2, =0x00000000 1162 str r2, [r0] 1163 mov r2, r6, lsl #3 1164 orr r2, r2, #0x85 // test command = 0x85 | (datagen << 3) 1165 str r2, [r0] 1166 ldr r3, =0x3000 1167 ldr r11, =0x500000 1168ddr_wait_engine_idle_0: 1169 subs r11, r11, #1 1170 beq ddr_test_fail 1171 ldr r2, [r0] 1172 tst r2, r3 // D[12] = idle bit 1173 beq ddr_wait_engine_idle_0 1174 1175 ldr r0, =0x1e6e0070 // read fail bit status 1176 ldr r3, =0x2000 1177 ldr r2, [r0] 1178 tst r2, r3 // D[13] = fail bit 1179 bne ddr_test_fail 1180 1181 add r6, r6, #1 // increase the test mode index 1182 cmp r6, #0x08 // test 8 modes 1183 bne ddr_test_single_loop 1184 1185ddr_test_burst: 1186 mov r6, #0x00 // initialize loop index, r1 is loop index 1187ddr_test_burst_loop: 1188/* Debug - UART console message */ 1189 ldr r0, =ASTMMC_UART_BASE 1190 mov r1, r6 1191 print_hex_char 1192/* Debug - UART console message */ 1193 ldr r0, =0x1e6e0070 1194 ldr r2, =0x00000000 1195 str r2, [r0] 1196 mov r2, r6, lsl #3 1197 orr r2, r2, #0xC1 // test command = 0xC1 | (datagen << 3) 1198 str r2, [r0] 1199 ldr r3, =0x3000 1200 ldr r11, =0x500000 1201ddr_wait_engine_idle_1: 1202 subs r11, r11, #1 1203 beq ddr_test_fail 1204 ldr r2, [r0] 1205 tst r2, r3 // D[12] = idle bit 1206 beq ddr_wait_engine_idle_1 1207 1208 ldr r0, =0x1e6e0070 // read fail bit status 1209 ldr r3, =0x2000 1210 ldr r2, [r0] 1211 tst r2, r3 // D[13] = fail bit 1212 bne ddr_test_fail 1213 1214 add r6, r6, #1 // increase the test mode index 1215 cmp r6, #0x08 // test 8 modes 1216 bne ddr_test_burst_loop 1217 1218 ldr r0, =0x1e6e0070 1219 ldr r1, =0x00000000 1220 str r1, [r0] 1221 1222 cmp r9, #0x0 1223 beq ddr_gate_train_pass 1224 b set_scratch // CBRTest() return(1) 1225 1226ddr_test_fail: 1227/* Debug - UART console message */ 1228 ldr r0, =ASTMMC_UART_BASE 1229 mov r1, #'F' // 'F' 1230 str r1, [r0] 1231 mov r1, #'a' // 'a' 1232 str r1, [r0] 1233 mov r1, #'i' // 'i' 1234 str r1, [r0] 1235 mov r1, #'l' // 'l' 1236 str r1, [r0] 1237 mov r1, #'\r' // '\r' 1238 str r1, [r0] 1239 mov r1, #'\n' // '\n' 1240 str r1, [r0] 1241 ldr r0, =(ASTMMC_UART_BASE | 0x14) 1242wait_print_1: 1243 ldr r1, [r0] 1244 tst r1, #0x40 1245 beq wait_print_1 1246/* Debug - UART console message */ 1247 cmp r9, #0x0 1248 beq ddr_gate_train_fail 1249 b ddr_init_start 1250 1251set_scratch: 1252 /*Set Scratch register Bit 6 after ddr initial finished */ 1253/* ldr r0, =0x1e6e2100 1254 ldr r1, [r0] 1255 orr r1, r1, #0x41 1256 str r1, [r0] 1257*/ 1258 1259/* Debug - UART console message */ 1260 ldr r0, =ASTMMC_UART_BASE 1261 mov r1, #'D' // 'D' 1262 str r1, [r0] 1263 mov r1, #'o' // 'o' 1264 str r1, [r0] 1265 mov r1, #'n' // 'n' 1266 str r1, [r0] 1267 mov r1, #'e' // 'e' 1268 str r1, [r0] 1269 mov r1, #'\r' // '\r' 1270 str r1, [r0] 1271 mov r1, #'\n' // '\n' 1272 str r1, [r0] 1273/* Debug - UART console message */ 1274 1275#ifdef CONFIG_ASPEED_NONSECUR_MODE 1276 mov r6,pc 1277 bl start_sec 1278#endif 1279 1280platform_exit: 1281 1282#ifdef ASTMMC_DRAM_ECC 1283 ldr r0, =0x1e6e0004 1284 ldr r2, =0x00000280 1285 ldr r1, [r0] 1286 orr r1, r1, r2 1287 str r1, [r0] 1288 1289 ldr r0, =0x1e6e007C 1290 ldr r1, =0x00000000 1291 str r1, [r0] 1292 ldr r0, =0x1e6e0074 1293 str r1, [r0] 1294 1295 ldr r0, =0x1e6e0070 1296 ldr r1, =0x00000221 1297 str r1, [r0] 1298 1299 ldr r2, =0x00001000 1300ECC_Init_Flag: 1301 ldr r1, [r0] 1302 tst r1, r2 @ D[12] = 1, Done 1303 beq ECC_Init_Flag 1304 1305 ldr r1, =0x00000000 1306 str r1, [r0] 1307 1308 ldr r0, =0x1e6e0050 1309 ldr r1, =0x80000000 1310 str r1, [r0] 1311 1312 ldr r0, =0x1e6e0050 1313 ldr r1, =0x40000000 1314 str r1, [r0] 1315#endif 1316 1317 /* restore lr */ 1318 mov lr, r4 1319 1320 /* back to arch calling code */ 1321 mov pc, lr 1322 1323secondary_cpu_init: 1324#ifdef CONFIG_ASPEED_NONSECUR_MODE 1325 mov r6,pc 1326 bl start_sec 1327#endif 1328wait_for_kickup: 1329 wfe 1330 ldr r2,[r3] 1331 cmp r2,r4 1332 bne wait_for_kickup 1333 1334 MOV r2,#'[' 1335 STR r2,[r1] 1336 MOV r2,#'1' 1337 STR r2,[r1] 1338 MOV r2,#'C' 1339 STR r2,[r1] 1340 MOV r2,#'P' 1341 STR r2,[r1] 1342 MOV r2,#'U' 1343 STR r2,[r1] 1344 MOV r2,#']' 1345 STR r2,[r1] 1346 MOV r2,#'\n' 1347 STR r2,[r1] 1348 MOV r2,#'\r' 1349 STR r2,[r1] 1350 ldr pc, [r0] 1351 ldr pc, [r0] 1352 b wait_for_kickup 1353