1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (c) 2016 Google, Inc 4 */ 5 #ifndef _ASM_ARCH_SCU_AST2600_H 6 #define _ASM_ARCH_SCU_AST2600_H 7 8 #define SCU_UNLOCK_VALUE 0x1688a8a8 9 10 #define SCU_HWSTRAP_VGAMEM_SHIFT 2 11 #define SCU_HWSTRAP_VGAMEM_MASK (3 << SCU_HWSTRAP_VGAMEM_SHIFT) 12 #define SCU_HWSTRAP_MAC1_RGMII (1 << 6) 13 #define SCU_HWSTRAP_MAC2_RGMII (1 << 7) 14 #define SCU_HWSTRAP_DDR4 (1 << 24) 15 #define SCU_HWSTRAP_CLKIN_25MHZ (1 << 23) 16 17 #define SCU_MPLL_DENUM_SHIFT 0 18 #define SCU_MPLL_DENUM_MASK 0x1f 19 #define SCU_MPLL_NUM_SHIFT 5 20 #define SCU_MPLL_NUM_MASK (0xff << SCU_MPLL_NUM_SHIFT) 21 #define SCU_MPLL_POST_SHIFT 13 22 #define SCU_MPLL_POST_MASK (0x3f << SCU_MPLL_POST_SHIFT) 23 #define SCU_PCLK_DIV_SHIFT 23 24 #define SCU_PCLK_DIV_MASK (7 << SCU_PCLK_DIV_SHIFT) 25 #define SCU_HPLL_DENUM_SHIFT 0 26 #define SCU_HPLL_DENUM_MASK 0x1f 27 #define SCU_HPLL_NUM_SHIFT 5 28 #define SCU_HPLL_NUM_MASK (0xff << SCU_HPLL_NUM_SHIFT) 29 #define SCU_HPLL_POST_SHIFT 13 30 #define SCU_HPLL_POST_MASK (0x3f << SCU_HPLL_POST_SHIFT) 31 32 #define SCU_MACCLK_SHIFT 16 33 #define SCU_MACCLK_MASK (7 << SCU_MACCLK_SHIFT) 34 35 #define SCU_MISC2_RGMII_HPLL (1 << 23) 36 #define SCU_MISC2_RGMII_CLKDIV_SHIFT 20 37 #define SCU_MISC2_RGMII_CLKDIV_MASK (3 << SCU_MISC2_RGMII_CLKDIV_SHIFT) 38 #define SCU_MISC2_RMII_MPLL (1 << 19) 39 #define SCU_MISC2_RMII_CLKDIV_SHIFT 16 40 #define SCU_MISC2_RMII_CLKDIV_MASK (3 << SCU_MISC2_RMII_CLKDIV_SHIFT) 41 #define SCU_MISC2_UARTCLK_SHIFT 24 42 43 #define SCU_MISC_D2PLL_OFF (1 << 4) 44 #define SCU_MISC_UARTCLK_DIV13 (1 << 12) 45 #define SCU_MISC_GCRT_USB20CLK (1 << 21) 46 47 #define SCU_MICDS_MAC1RGMII_TXDLY_SHIFT 0 48 #define SCU_MICDS_MAC1RGMII_TXDLY_MASK (0x3f\ 49 << SCU_MICDS_MAC1RGMII_TXDLY_SHIFT) 50 #define SCU_MICDS_MAC2RGMII_TXDLY_SHIFT 6 51 #define SCU_MICDS_MAC2RGMII_TXDLY_MASK (0x3f\ 52 << SCU_MICDS_MAC2RGMII_TXDLY_SHIFT) 53 #define SCU_MICDS_MAC1RMII_RDLY_SHIFT 12 54 #define SCU_MICDS_MAC1RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC1RMII_RDLY_SHIFT) 55 #define SCU_MICDS_MAC2RMII_RDLY_SHIFT 18 56 #define SCU_MICDS_MAC2RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC2RMII_RDLY_SHIFT) 57 #define SCU_MICDS_MAC1RMII_TXFALL (1 << 24) 58 #define SCU_MICDS_MAC2RMII_TXFALL (1 << 25) 59 #define SCU_MICDS_RMII1_RCLKEN (1 << 29) 60 #define SCU_MICDS_RMII2_RCLKEN (1 << 30) 61 #define SCU_MICDS_RGMIIPLL (1 << 31) 62 63 /* 64 * SYSRESET is actually more like a Power register, 65 * except that corresponding bit set to 1 means that 66 * the peripheral is off. 67 */ 68 #define SCU_SYSRESET_XDMA (1 << 25) 69 #define SCU_SYSRESET_MCTP (1 << 24) 70 #define SCU_SYSRESET_ADC (1 << 23) 71 #define SCU_SYSRESET_JTAG (1 << 22) 72 #define SCU_SYSRESET_MIC (1 << 18) 73 #define SCU_SYSRESET_SDIO (1 << 16) 74 #define SCU_SYSRESET_USB11HOST (1 << 15) 75 #define SCU_SYSRESET_USBHUB (1 << 14) 76 #define SCU_SYSRESET_CRT (1 << 13) 77 #define SCU_SYSRESET_MAC2 (1 << 12) 78 #define SCU_SYSRESET_MAC1 (1 << 11) 79 #define SCU_SYSRESET_PECI (1 << 10) 80 #define SCU_SYSRESET_PWM (1 << 9) 81 #define SCU_SYSRESET_PCI_VGA (1 << 8) 82 #define SCU_SYSRESET_2D (1 << 7) 83 #define SCU_SYSRESET_VIDEO (1 << 6) 84 #define SCU_SYSRESET_LPC (1 << 5) 85 #define SCU_SYSRESET_HAC (1 << 4) 86 #define SCU_SYSRESET_USBHID (1 << 3) 87 #define SCU_SYSRESET_I2C (1 << 2) 88 #define SCU_SYSRESET_AHB (1 << 1) 89 #define SCU_SYSRESET_SDRAM_WDT (1 << 0) 90 91 /* Bits 16-27 in the register control pin functions for I2C devices 3-14 */ 92 #define SCU_PINMUX_CTRL5_I2C (1 << 16) 93 94 /* 95 * The values are grouped by function, not by register. 96 * They are actually scattered across multiple loosely related registers. 97 */ 98 #define SCU_PIN_FUN_MAC1_MDC (1 << 30) 99 #define SCU_PIN_FUN_MAC1_MDIO (1 << 31) 100 #define SCU_PIN_FUN_MAC1_PHY_LINK (1 << 0) 101 #define SCU_PIN_FUN_MAC2_MDIO (1 << 2) 102 #define SCU_PIN_FUN_MAC2_PHY_LINK (1 << 1) 103 #define SCU_PIN_FUN_SCL1 (1 << 12) 104 #define SCU_PIN_FUN_SCL2 (1 << 14) 105 #define SCU_PIN_FUN_SDA1 (1 << 13) 106 #define SCU_PIN_FUN_SDA2 (1 << 15) 107 108 #define SCU_CLKSTOP_MAC1 (1 << 20) 109 #define SCU_CLKSTOP_MAC2 (1 << 21) 110 111 #define SCU_D2PLL_EXT1_OFF (1 << 0) 112 #define SCU_D2PLL_EXT1_BYPASS (1 << 1) 113 #define SCU_D2PLL_EXT1_RESET (1 << 2) 114 #define SCU_D2PLL_EXT1_MODE_SHIFT 3 115 #define SCU_D2PLL_EXT1_MODE_MASK (3 << SCU_D2PLL_EXT1_MODE_SHIFT) 116 #define SCU_D2PLL_EXT1_PARAM_SHIFT 5 117 #define SCU_D2PLL_EXT1_PARAM_MASK (0x1ff << SCU_D2PLL_EXT1_PARAM_SHIFT) 118 119 #define SCU_D2PLL_NUM_SHIFT 0 120 #define SCU_D2PLL_NUM_MASK (0xff << SCU_D2PLL_NUM_SHIFT) 121 #define SCU_D2PLL_DENUM_SHIFT 8 122 #define SCU_D2PLL_DENUM_MASK (0x1f << SCU_D2PLL_DENUM_SHIFT) 123 #define SCU_D2PLL_POST_SHIFT 13 124 #define SCU_D2PLL_POST_MASK (0x3f << SCU_D2PLL_POST_SHIFT) 125 #define SCU_D2PLL_ODIV_SHIFT 19 126 #define SCU_D2PLL_ODIV_MASK (7 << SCU_D2PLL_ODIV_SHIFT) 127 #define SCU_D2PLL_SIC_SHIFT 22 128 #define SCU_D2PLL_SIC_MASK (0x1f << SCU_D2PLL_SIC_SHIFT) 129 #define SCU_D2PLL_SIP_SHIFT 27 130 #define SCU_D2PLL_SIP_MASK (0x1f << SCU_D2PLL_SIP_SHIFT) 131 132 #define SCU_CLKDUTY_DCLK_SHIFT 0 133 #define SCU_CLKDUTY_DCLK_MASK (0x3f << SCU_CLKDUTY_DCLK_SHIFT) 134 #define SCU_CLKDUTY_RGMII1TXCK_SHIFT 8 135 #define SCU_CLKDUTY_RGMII1TXCK_MASK (0x7f << SCU_CLKDUTY_RGMII1TXCK_SHIFT) 136 #define SCU_CLKDUTY_RGMII2TXCK_SHIFT 16 137 #define SCU_CLKDUTY_RGMII2TXCK_MASK (0x7f << SCU_CLKDUTY_RGMII2TXCK_SHIFT) 138 139 #ifndef __ASSEMBLY__ 140 141 struct ast2600_clk_priv { 142 struct ast2600_scu *scu; 143 }; 144 145 /** 146 * ast_get_clk() - get a pointer to Clock Driver 147 * 148 * @devp, OUT - pointer to Clock Driver 149 * @return zero on success, error code (< 0) otherwise. 150 */ 151 int ast_get_clk(struct udevice **devp); 152 153 /** 154 * ast_get_scu() - get a pointer to SCU registers 155 * 156 * @return pointer to struct ast2600_scu on success, ERR_PTR otherwise 157 */ 158 void *ast_get_scu(void); 159 160 #endif /* __ASSEMBLY__ */ 161 162 #endif /* _ASM_ARCH_SCU_AST2600_H */ 163