1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 * Ryan Chen <ryan_chen@aspeedtech.com> 5 */ 6 7 #include <common.h> 8 #include <clk-uclass.h> 9 #include <dm.h> 10 #include <asm/io.h> 11 #include <dm/lists.h> 12 #include <asm/arch/scu_ast2600.h> 13 #include <dt-bindings/clock/ast2600-clock.h> 14 15 /* register */ 16 #define ASPEED_STRAP 0x70 17 #define SCU_HWSTRAP_VGAMEM_SHIFT 2 18 #define SCU_HWSTRAP_VGAMEM_MASK (3 << SCU_HWSTRAP_VGAMEM_SHIFT) 19 #define SCU_HWSTRAP_MAC1_RGMII (1 << 6) 20 #define SCU_HWSTRAP_MAC2_RGMII (1 << 7) 21 #define SCU_HWSTRAP_DDR4 (1 << 24) 22 #define SCU_HWSTRAP_CLKIN_25MHZ (1 << 23) 23 24 #define ASPEED_CLK_SELECT 0x08 25 #define SCU_PCLK_DIV_SHIFT 23 26 #define SCU_PCLK_DIV_MASK (7 << SCU_PCLK_DIV_SHIFT) 27 28 #define ASPEED_MSIC2 0x4C 29 #define SCU_MISC2_RGMII_HPLL (1 << 23) 30 #define SCU_MISC2_RGMII_CLKDIV_SHIFT 20 31 #define SCU_MISC2_RGMII_CLKDIV_MASK (3 << SCU_MISC2_RGMII_CLKDIV_SHIFT) 32 #define SCU_MISC2_RMII_MPLL (1 << 19) 33 #define SCU_MISC2_RMII_CLKDIV_SHIFT 16 34 #define SCU_MISC2_RMII_CLKDIV_MASK (3 << SCU_MISC2_RMII_CLKDIV_SHIFT) 35 #define SCU_MISC2_UARTCLK_SHIFT 24 36 37 #define ASPEED_MPLL_PARAMETER 0x20 38 #define SCU_MPLL_DENUM_SHIFT 0 39 #define SCU_MPLL_DENUM_MASK 0x1f 40 #define SCU_MPLL_NUM_SHIFT 5 41 #define SCU_MPLL_NUM_MASK (0xff << SCU_MPLL_NUM_SHIFT) 42 #define SCU_MPLL_POST_SHIFT 13 43 #define SCU_MPLL_POST_MASK (0x3f << SCU_MPLL_POST_SHIFT) 44 45 #define ASPEED_HPLL_PARAMETER 0x24 46 #define SCU_HPLL_DENUM_SHIFT 0 47 #define SCU_HPLL_DENUM_MASK 0x1f 48 #define SCU_HPLL_NUM_SHIFT 5 49 #define SCU_HPLL_NUM_MASK (0xff << SCU_HPLL_NUM_SHIFT) 50 #define SCU_HPLL_POST_SHIFT 13 51 #define SCU_HPLL_POST_MASK (0x3f << SCU_HPLL_POST_SHIFT) 52 53 54 /* 55 * MAC Clock Delay settings, taken from Aspeed SDK 56 */ 57 #define RGMII_TXCLK_ODLY 8 58 #define RMII_RXCLK_IDLY 2 59 60 /* 61 * TGMII Clock Duty constants, taken from Aspeed SDK 62 */ 63 #define RGMII2_TXCK_DUTY 0x66 64 #define RGMII1_TXCK_DUTY 0x64 65 66 #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000) 67 68 DECLARE_GLOBAL_DATA_PTR; 69 70 /* 71 * Clock divider/multiplier configuration struct. 72 * For H-PLL and M-PLL the formula is 73 * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) 74 * M - Numerator 75 * N - Denumerator 76 * P - Post Divider 77 * They have the same layout in their control register. 78 * 79 * D-PLL and D2-PLL have extra divider (OD + 1), which is not 80 * yet needed and ignored by clock configurations. 81 */ 82 struct aspeed_div_config { 83 unsigned int num; 84 unsigned int denum; 85 unsigned int post_div; 86 }; 87 88 #define AST2600_CLK_IN 25000000 89 90 /* 91 * Get the rate of the M-PLL clock from input clock frequency and 92 * the value of the M-PLL Parameter Register. 93 */ 94 static u32 aspeed_get_mpll_rate(struct ast2600_clk_priv *priv) 95 { 96 u32 clkin = AST2600_CLK_IN; 97 u32 mpll_reg = readl(&priv->scu->m_pll_param); 98 99 printf("&priv->scu->m_pll_param %x \n", (u32) &priv->scu->m_pll_param); 100 const ulong num = (mpll_reg & SCU_MPLL_NUM_MASK) >> SCU_MPLL_NUM_SHIFT; 101 const ulong denum = (mpll_reg & SCU_MPLL_DENUM_MASK) 102 >> SCU_MPLL_DENUM_SHIFT; 103 const ulong post_div = (mpll_reg & SCU_MPLL_POST_MASK) 104 >> SCU_MPLL_POST_SHIFT; 105 106 return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1); 107 } 108 109 /* 110 * Get the rate of the H-PLL clock from input clock frequency and 111 * the value of the H-PLL Parameter Register. 112 */ 113 static ulong ast2600_get_hpll_rate(struct ast2600_clk_priv *priv) 114 { 115 ulong clkin = AST2600_CLK_IN; 116 u32 hpll_reg = readl(&priv->scu->h_pll_param); 117 118 printf("&priv->scu->h_pll_param %x \n", (u32) &priv->scu->h_pll_param); 119 120 const ulong num = (hpll_reg & SCU_HPLL_NUM_MASK) >> SCU_HPLL_NUM_SHIFT; 121 const ulong denum = (hpll_reg & SCU_HPLL_DENUM_MASK) 122 >> SCU_HPLL_DENUM_SHIFT; 123 const ulong post_div = (hpll_reg & SCU_HPLL_POST_MASK) 124 >> SCU_HPLL_POST_SHIFT; 125 126 return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1); 127 } 128 129 130 #define ASPEED_G6_APLL_PARAMETER 0x210 131 #define APLL_BYPASS_EN BIT(20) 132 133 static ulong ast2600_get_apll_clk_rate(struct ast2600_clk_priv *priv) 134 { 135 u32 clk_in = 25000000; 136 u32 val = readl(&priv->scu->a_pll_param); 137 unsigned int mult, div; 138 139 printf("&priv->scu->h_pll_param %x \n", (u32) &priv->scu->a_pll_param); 140 141 if (val & APLL_BYPASS_EN) { 142 /* Pass through mode */ 143 mult = div = 1; 144 } else { 145 /* F = 25Mhz * (2-OD) * [(M + 2) / (n + 1)] */ 146 u32 m = (val >> 5) & 0x3f; 147 u32 od = (val >> 4) & 0x1; 148 u32 n = val & 0xf; 149 150 mult = (2 - od) * (m + 2); 151 div = n + 1; 152 } 153 return (clk_in * mult)/div; 154 155 156 157 } 158 159 //#define ASPEED_G6_CLK_SELECT4 0x314 160 161 static ulong ast2600_get_uart_clk_rate(struct ast2600_clk_priv *priv, int uart_index) 162 { 163 ulong uart_clkin; 164 165 printf("ast2600_get_uart_clk_rate source %ld \n\n", ast2600_get_apll_clk_rate(priv)); 166 return (24000000/13); 167 168 if (readl(&priv->scu->misc_ctrl2) & 169 (1 << (uart_index - 1 + SCU_MISC2_UARTCLK_SHIFT))) 170 uart_clkin = 192 * 1000 * 1000; 171 else 172 uart_clkin = 24 * 1000 * 1000; 173 174 if (readl(&priv->scu->misc_ctrl2) & SCU_MISC_UARTCLK_DIV13) 175 uart_clkin /= 13; 176 177 return uart_clkin; 178 } 179 180 struct aspeed_clock_config { 181 ulong input_rate; 182 ulong rate; 183 struct aspeed_div_config cfg; 184 }; 185 186 static const struct aspeed_clock_config aspeed_clock_config_defaults[] = { 187 { 24000000, 250000000, { .num = 124, .denum = 1, .post_div = 5 } }, 188 }; 189 190 static bool aspeed_get_clock_config_default(ulong input_rate, 191 ulong requested_rate, 192 struct aspeed_div_config *cfg) 193 { 194 int i; 195 196 for (i = 0; i < ARRAY_SIZE(aspeed_clock_config_defaults); i++) { 197 const struct aspeed_clock_config *default_cfg = 198 &aspeed_clock_config_defaults[i]; 199 if (default_cfg->input_rate == input_rate && 200 default_cfg->rate == requested_rate) { 201 *cfg = default_cfg->cfg; 202 return true; 203 } 204 } 205 206 return false; 207 } 208 209 /* 210 * @input_rate - the rate of input clock in Hz 211 * @requested_rate - desired output rate in Hz 212 * @div - this is an IN/OUT parameter, at input all fields of the config 213 * need to be set to their maximum allowed values. 214 * The result (the best config we could find), would also be returned 215 * in this structure. 216 * 217 * @return The clock rate, when the resulting div_config is used. 218 */ 219 static ulong aspeed_calc_clock_config(ulong input_rate, ulong requested_rate, 220 struct aspeed_div_config *cfg) 221 { 222 /* 223 * The assumption is that kHz precision is good enough and 224 * also enough to avoid overflow when multiplying. 225 */ 226 const ulong input_rate_khz = input_rate / 1000; 227 const ulong rate_khz = requested_rate / 1000; 228 const struct aspeed_div_config max_vals = *cfg; 229 struct aspeed_div_config it = { 0, 0, 0 }; 230 ulong delta = rate_khz; 231 ulong new_rate_khz = 0; 232 233 /* 234 * Look for a well known frequency first. 235 */ 236 if (aspeed_get_clock_config_default(input_rate, requested_rate, cfg)) 237 return requested_rate; 238 239 for (; it.denum <= max_vals.denum; ++it.denum) { 240 for (it.post_div = 0; it.post_div <= max_vals.post_div; 241 ++it.post_div) { 242 it.num = (rate_khz * (it.post_div + 1) / input_rate_khz) 243 * (it.denum + 1); 244 if (it.num > max_vals.num) 245 continue; 246 247 new_rate_khz = (input_rate_khz 248 * ((it.num + 1) / (it.denum + 1))) 249 / (it.post_div + 1); 250 251 /* Keep the rate below requested one. */ 252 if (new_rate_khz > rate_khz) 253 continue; 254 255 if (new_rate_khz - rate_khz < delta) { 256 delta = new_rate_khz - rate_khz; 257 *cfg = it; 258 if (delta == 0) 259 return new_rate_khz * 1000; 260 } 261 } 262 } 263 264 return new_rate_khz * 1000; 265 } 266 267 static u32 aspeed_configure_ddr(struct ast2600_clk_priv *priv, ulong rate) 268 { 269 u32 clkin = AST2600_CLK_IN; 270 u32 mpll_reg; 271 struct aspeed_div_config div_cfg = { 272 .num = (SCU_MPLL_NUM_MASK >> SCU_MPLL_NUM_SHIFT), 273 .denum = (SCU_MPLL_DENUM_MASK >> SCU_MPLL_DENUM_SHIFT), 274 .post_div = (SCU_MPLL_POST_MASK >> SCU_MPLL_POST_SHIFT), 275 }; 276 277 aspeed_calc_clock_config(clkin, rate, &div_cfg); 278 279 mpll_reg = readl(&priv->scu->m_pll_param); 280 mpll_reg &= ~(SCU_MPLL_POST_MASK | SCU_MPLL_NUM_MASK 281 | SCU_MPLL_DENUM_MASK); 282 mpll_reg |= (div_cfg.post_div << SCU_MPLL_POST_SHIFT) 283 | (div_cfg.num << SCU_MPLL_NUM_SHIFT) 284 | (div_cfg.denum << SCU_MPLL_DENUM_SHIFT); 285 286 writel(mpll_reg, &priv->scu->m_pll_param); 287 288 return aspeed_get_mpll_rate(priv); 289 } 290 291 static u32 aspeed_configure_mac(struct ast2600_clk_priv *priv, int index) 292 { 293 #if 0 294 295 u32 clkin = AST2600_CLK_IN; 296 u32 hpll_rate = ast2600_get_hpll_rate(priv); 297 ulong required_rate; 298 u32 hwstrap; 299 u32 divisor; 300 u32 reset_bit; 301 u32 clkstop_bit; 302 303 /* 304 * According to data sheet, for 10/100 mode the MAC clock frequency 305 * should be at least 25MHz and for 1000 mode at least 100MHz 306 */ 307 hwstrap = readl(priv->regs + ASPEED_STRAP); 308 if (hwstrap & (SCU_HWSTRAP_MAC1_RGMII | SCU_HWSTRAP_MAC2_RGMII)) 309 required_rate = 100 * 1000 * 1000; 310 else 311 required_rate = 25 * 1000 * 1000; 312 313 divisor = hpll_rate / required_rate; 314 315 if (divisor < 4) { 316 /* Clock can't run fast enough, but let's try anyway */ 317 debug("MAC clock too slow\n"); 318 divisor = 4; 319 } else if (divisor > 16) { 320 /* Can't slow down the clock enough, but let's try anyway */ 321 debug("MAC clock too fast\n"); 322 divisor = 16; 323 } 324 325 switch (index) { 326 case 1: 327 reset_bit = SCU_SYSRESET_MAC1; 328 clkstop_bit = SCU_CLKSTOP_MAC1; 329 break; 330 case 2: 331 reset_bit = SCU_SYSRESET_MAC2; 332 clkstop_bit = SCU_CLKSTOP_MAC2; 333 break; 334 default: 335 return -EINVAL; 336 } 337 338 clrsetbits_le32(priv->regs + ASPEED_CLK_SELECT, SCU_MACCLK_MASK, 339 ((divisor - 2) / 2) << SCU_MACCLK_SHIFT); 340 341 /* 342 * Disable MAC, start its clock and re-enable it. 343 * The procedure and the delays (100us & 10ms) are 344 * specified in the datasheet. 345 */ 346 setbits_le32(&scu->sysreset_ctrl1, reset_bit); 347 udelay(100); 348 clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit); 349 mdelay(10); 350 clrbits_le32(&scu->sysreset_ctrl1, reset_bit); 351 352 writel((RGMII2_TXCK_DUTY << SCU_CLKDUTY_RGMII2TXCK_SHIFT) 353 | (RGMII1_TXCK_DUTY << SCU_CLKDUTY_RGMII1TXCK_SHIFT), 354 &scu->clk_duty_sel); 355 356 return required_rate; 357 #endif 358 } 359 360 static ulong aspeed_configure_d2pll(struct ast2600_clk_priv *priv, ulong rate) 361 { 362 /* 363 * The values and the meaning of the next three 364 * parameters are undocumented. Taken from Aspeed SDK. 365 * 366 * TODO(clg@kaod.org): the SIP and SIC values depend on the 367 * Numerator value 368 */ 369 370 const u32 d2_pll_ext_param = 0x2c; 371 const u32 d2_pll_sip = 0x11; 372 const u32 d2_pll_sic = 0x18; 373 u32 clk_delay_settings = 374 (RMII_RXCLK_IDLY << SCU_MICDS_MAC1RMII_RDLY_SHIFT) 375 | (RMII_RXCLK_IDLY << SCU_MICDS_MAC2RMII_RDLY_SHIFT) 376 | (RGMII_TXCLK_ODLY << SCU_MICDS_MAC1RGMII_TXDLY_SHIFT) 377 | (RGMII_TXCLK_ODLY << SCU_MICDS_MAC2RGMII_TXDLY_SHIFT); 378 struct aspeed_div_config div_cfg = { 379 .num = SCU_D2PLL_NUM_MASK >> SCU_D2PLL_NUM_SHIFT, 380 .denum = SCU_D2PLL_DENUM_MASK >> SCU_D2PLL_DENUM_SHIFT, 381 .post_div = SCU_D2PLL_POST_MASK >> SCU_D2PLL_POST_SHIFT, 382 }; 383 ulong clkin = AST2600_CLK_IN; 384 ulong new_rate; 385 #if 0 386 writel((d2_pll_ext_param << SCU_D2PLL_EXT1_PARAM_SHIFT) 387 | SCU_D2PLL_EXT1_OFF 388 | SCU_D2PLL_EXT1_RESET, &scu->d2_pll_ext_param[0]); 389 390 /* 391 * Select USB2.0 port1 PHY clock as a clock source for GCRT. 392 * This would disconnect it from D2-PLL. 393 */ 394 clrsetbits_le32(&scu->misc_ctrl1, SCU_MISC_D2PLL_OFF, 395 SCU_MISC_GCRT_USB20CLK); 396 397 new_rate = aspeed_calc_clock_config(clkin, rate, &div_cfg); 398 writel((d2_pll_sip << SCU_D2PLL_SIP_SHIFT) 399 | (d2_pll_sic << SCU_D2PLL_SIC_SHIFT) 400 | (div_cfg.num << SCU_D2PLL_NUM_SHIFT) 401 | (div_cfg.denum << SCU_D2PLL_DENUM_SHIFT) 402 | (div_cfg.post_div << SCU_D2PLL_POST_SHIFT), 403 &scu->d2_pll_param); 404 405 clrbits_le32(&scu->d2_pll_ext_param[0], 406 SCU_D2PLL_EXT1_OFF | SCU_D2PLL_EXT1_RESET); 407 408 clrsetbits_le32(&scu->misc_ctrl2, 409 SCU_MISC2_RGMII_HPLL | SCU_MISC2_RMII_MPLL 410 | SCU_MISC2_RGMII_CLKDIV_MASK | 411 SCU_MISC2_RMII_CLKDIV_MASK, 412 (4 << SCU_MISC2_RMII_CLKDIV_SHIFT)); 413 414 writel(clk_delay_settings | SCU_MICDS_RGMIIPLL, &scu->mac_clk_delay); 415 writel(clk_delay_settings, &scu->mac_clk_delay_100M); 416 writel(clk_delay_settings, &scu->mac_clk_delay_10M); 417 #endif 418 return new_rate; 419 } 420 421 static u32 ast2600_a0_axi_ahb_div_table[] = { 422 2, 2, 3, 5, 423 }; 424 425 static u32 ast2600_a1_axi_ahb_div_table[] = { 426 4, 6, 2, 4, 427 }; 428 429 static u32 ast2600_hpll_pclk_div_table[] = { 430 4, 8, 12, 16, 20, 24, 28, 32, 431 }; 432 static ulong ast2600_clk_get_rate(struct clk *clk) 433 { 434 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 435 ulong rate; 436 437 switch (clk->id) { 438 //HPLL 439 case ASPEED_CLK_HPLL: 440 rate = ast2600_get_hpll_rate(priv); 441 break; 442 //HCLK 443 case ASPEED_CLK_AHB: 444 { 445 u32 hw_rev = readl(&priv->scu->chip_id0); 446 u32 hwstrap1 = readl(&priv->scu->hwstrap1); 447 u32 axi_div = 1; 448 u32 ahb_div = 0; 449 if((hwstrap1 >> 16) & 0x1) 450 axi_div = 1; 451 else 452 axi_div = 2; 453 454 if (hw_rev & BIT(16)) 455 ahb_div = ast2600_a1_axi_ahb_div_table[(hwstrap1 >> 11) & 0x3]; 456 else 457 ahb_div = ast2600_a0_axi_ahb_div_table[(hwstrap1 >> 11) & 0x3]; 458 459 rate = ast2600_get_hpll_rate(priv); 460 rate = rate / axi_div / ahb_div; 461 } 462 break; 463 464 case ASPEED_CLK_MPLL: 465 rate = aspeed_get_mpll_rate(priv); 466 break; 467 case BCLK_PCLK: 468 { 469 u32 clk_sel1 = readl(&priv->scu->clk_sel1); 470 u32 apb_div = ast2600_hpll_pclk_div_table[((clk_sel1 >> 23) & 0x7)]; 471 rate = ast2600_get_hpll_rate(priv); 472 rate = rate / apb_div; 473 } 474 break; 475 case PCLK_UART1: 476 rate = ast2600_get_uart_clk_rate(priv, 1); 477 break; 478 case PCLK_UART2: 479 rate = ast2600_get_uart_clk_rate(priv, 2); 480 break; 481 case PCLK_UART3: 482 rate = ast2600_get_uart_clk_rate(priv, 3); 483 break; 484 case PCLK_UART4: 485 rate = ast2600_get_uart_clk_rate(priv, 4); 486 break; 487 case ASPEED_CLK_GATE_UART5CLK: 488 rate = ast2600_get_uart_clk_rate(priv, 5); 489 break; 490 default: 491 return -ENOENT; 492 } 493 494 return rate; 495 } 496 497 static ulong ast2600_clk_set_rate(struct clk *clk, ulong rate) 498 { 499 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 500 501 ulong new_rate; 502 switch (clk->id) { 503 case ASPEED_CLK_MPLL: 504 new_rate = aspeed_configure_ddr(priv, rate); 505 break; 506 case PLL_D2PLL: 507 new_rate = aspeed_configure_d2pll(priv, rate); 508 break; 509 default: 510 return -ENOENT; 511 } 512 513 return new_rate; 514 } 515 516 static int ast2600_clk_enable(struct clk *clk) 517 { 518 struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); 519 520 switch (clk->id) { 521 /* 522 * For MAC clocks the clock rate is 523 * configured based on whether RGMII or RMII mode has been selected 524 * through hardware strapping. 525 */ 526 case PCLK_MAC1: 527 aspeed_configure_mac(priv, 1); 528 break; 529 case PCLK_MAC2: 530 aspeed_configure_mac(priv, 2); 531 break; 532 case PLL_D2PLL: 533 aspeed_configure_d2pll(priv, D2PLL_DEFAULT_RATE); 534 break; 535 default: 536 return -ENOENT; 537 } 538 539 return 0; 540 } 541 542 struct clk_ops aspeed_clk_ops = { 543 .get_rate = ast2600_clk_get_rate, 544 .set_rate = ast2600_clk_set_rate, 545 .enable = ast2600_clk_enable, 546 }; 547 548 static int ast2600_clk_probe(struct udevice *dev) 549 { 550 struct ast2600_clk_priv *priv = dev_get_priv(dev); 551 552 priv->scu = devfdt_get_addr_ptr(dev); 553 if (IS_ERR(priv->scu)) 554 return PTR_ERR(priv->scu); 555 556 return 0; 557 } 558 559 static int ast2600_clk_bind(struct udevice *dev) 560 { 561 int ret; 562 563 /* The reset driver does not have a device node, so bind it here */ 564 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); 565 if (ret) 566 debug("Warning: No reset driver: ret=%d\n", ret); 567 568 return 0; 569 } 570 571 static const struct udevice_id ast2600_clk_ids[] = { 572 { .compatible = "aspeed,ast2600-scu", }, 573 { } 574 }; 575 576 U_BOOT_DRIVER(aspeed_scu) = { 577 .name = "aspeed_scu", 578 .id = UCLASS_CLK, 579 .of_match = ast2600_clk_ids, 580 .priv_auto_alloc_size = sizeof(struct ast2600_clk_priv), 581 .ops = &aspeed_clk_ops, 582 .bind = ast2600_clk_bind, 583 .probe = ast2600_clk_probe, 584 }; 585