| 51dd4923 | 25-Sep-2019 |
Cédric Le Goater <clg@kaod.org> |
aspeed/i2c: Add AST2600 support
The I2C controller of the AST2400 and AST2500 SoCs have one IRQ shared
by all I2C busses. The AST2600 SoC I2C controller has one IRQ per bus
and 16 busses.
Signed-of
aspeed/i2c: Add AST2600 support
The I2C controller of the AST2400 and AST2500 SoCs have one IRQ shared
by all I2C busses. The AST2600 SoC I2C controller has one IRQ per bus
and 16 busses.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id: 20190925143248.10000-17-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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| 547db24a | 07-Dec-2017 |
Corey Minyard <cminyard@mvista.com> |
i2c:smbus_slave: Add an SMBus vmstate structure
There is no vmstate handling for SMBus, so no device sitting on SMBus
can have a state transfer that works reliably. So add it.
Signed-off-by: Corey
i2c:smbus_slave: Add an SMBus vmstate structure
There is no vmstate handling for SMBus, so no device sitting on SMBus
can have a state transfer that works reliably. So add it.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Dr. David Alan Gilbert <dgilbert@redhat.com>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
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| 52cc6a49 | 14-Nov-2018 |
Corey Minyard <cminyard@mvista.com> |
i2c:pm_smbus: Fix pm_smbus handling of I2C block read
The I2C block read function of pm_smbus was completely broken. It
required doing some direct I2C handling because it didn't have a
defined size
i2c:pm_smbus: Fix pm_smbus handling of I2C block read
The I2C block read function of pm_smbus was completely broken. It
required doing some direct I2C handling because it didn't have a
defined size, the OS code just reads bytes until it marks the
transaction finished.
This also required adjusting how the AMIBIOS workaround code worked,
the I2C block mode was setting STS_HOST_BUSY during a transaction,
so that bit could no longer be used to inform the host status read
code to start the transaction. Create a explicit bool for that
operation.
Also, don't read the next byte from the device in byte-by-byte
mode unless the OS is actually clearing the byte done bit. Just
assuming that's what the OS is doing is a bad idea.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
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| 031ac498 | 30-Nov-2018 |
Corey Minyard <cminyard@mvista.com> |
i2c:smbus: Simplify read handling
There were two different read functions, and with the removal of
the command passed in there is no functional difference. So remove
one of them. With that you don
i2c:smbus: Simplify read handling
There were two different read functions, and with the removal of
the command passed in there is no functional difference. So remove
one of them. With that you don't need one of the states, so that
can be removed, too.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
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| 9cf27d74 | 30-Nov-2018 |
Corey Minyard <cminyard@mvista.com> |
i2c:smbus: Simplify write operation
There were two different write functions and the SMBus code kept
track of the command.
Keeping track of the command wasn't useful, in fact it wasn't quite
correc
i2c:smbus: Simplify write operation
There were two different write functions and the SMBus code kept
track of the command.
Keeping track of the command wasn't useful, in fact it wasn't quite
correct for the eeprom_smbus code. And there is no need for two write
functions. Just have one write function and the first byte in the
buffer is the command.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
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| 905cec6d | 30-Nov-2018 |
Corey Minyard <cminyard@mvista.com> |
i2c:smbus: Correct the working of quick commands
The logic of handling quick SMBus commands was wrong. If you get a
finish event with no data, that's a quick command.
Document the quick command wh
i2c:smbus: Correct the working of quick commands
The logic of handling quick SMBus commands was wrong. If you get a
finish event with no data, that's a quick command.
Document the quick command while we are at it.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
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| 45726b6e | 20-Aug-2018 |
Corey Minyard <cminyard@mvista.com> |
i2c: pm_smbus: Add the ability to force block transfer enable
The PIIX4 hardware has block transfer buffer always enabled in
the hardware, but the i801 does not. Add a parameter to pm_smbus_init
to
i2c: pm_smbus: Add the ability to force block transfer enable
The PIIX4 hardware has block transfer buffer always enabled in
the hardware, but the i801 does not. Add a parameter to pm_smbus_init
to force on the block transfer so the PIIX4 handler can enable this
by default, as it was disabled by default before.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <1534796770-10295-9-git-send-email-minyard@acm.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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| e724385a | 20-Aug-2018 |
Corey Minyard <cminyard@mvista.com> |
i2c: pm_smbus: Add interrupt handling
Add the necessary code so that interrupts actually work from
the pm_smbus device.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
Cc: Michael S. Tsirkin <ms
i2c: pm_smbus: Add interrupt handling
Add the necessary code so that interrupts actually work from
the pm_smbus device.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <1534796770-10295-7-git-send-email-minyard@acm.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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