1 /* 2 * Copyright (c) 2006-2008 Openedhand Ltd. 3 * Written by Andrzej Zaborowski <balrog@zabor.org> 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 or 8 * (at your option) version 3 of the License. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "hw/hw.h" 21 #include "hw/irq.h" 22 #include "hw/arm/sharpsl.h" 23 #include "hw/sysbus.h" 24 #include "migration/vmstate.h" 25 #include "qemu/module.h" 26 27 #undef REG_FMT 28 #define REG_FMT "0x%02lx" 29 30 /* SCOOP devices */ 31 32 #define TYPE_SCOOP "scoop" 33 #define SCOOP(obj) OBJECT_CHECK(ScoopInfo, (obj), TYPE_SCOOP) 34 35 typedef struct ScoopInfo ScoopInfo; 36 struct ScoopInfo { 37 SysBusDevice parent_obj; 38 39 qemu_irq handler[16]; 40 MemoryRegion iomem; 41 uint16_t status; 42 uint16_t power; 43 uint32_t gpio_level; 44 uint32_t gpio_dir; 45 uint32_t prev_level; 46 47 uint16_t mcr; 48 uint16_t cdr; 49 uint16_t ccr; 50 uint16_t irr; 51 uint16_t imr; 52 uint16_t isr; 53 }; 54 55 #define SCOOP_MCR 0x00 56 #define SCOOP_CDR 0x04 57 #define SCOOP_CSR 0x08 58 #define SCOOP_CPR 0x0c 59 #define SCOOP_CCR 0x10 60 #define SCOOP_IRR_IRM 0x14 61 #define SCOOP_IMR 0x18 62 #define SCOOP_ISR 0x1c 63 #define SCOOP_GPCR 0x20 64 #define SCOOP_GPWR 0x24 65 #define SCOOP_GPRR 0x28 66 67 static inline void scoop_gpio_handler_update(ScoopInfo *s) { 68 uint32_t level, diff; 69 int bit; 70 level = s->gpio_level & s->gpio_dir; 71 72 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { 73 bit = ctz32(diff); 74 qemu_set_irq(s->handler[bit], (level >> bit) & 1); 75 } 76 77 s->prev_level = level; 78 } 79 80 static uint64_t scoop_read(void *opaque, hwaddr addr, 81 unsigned size) 82 { 83 ScoopInfo *s = (ScoopInfo *) opaque; 84 85 switch (addr & 0x3f) { 86 case SCOOP_MCR: 87 return s->mcr; 88 case SCOOP_CDR: 89 return s->cdr; 90 case SCOOP_CSR: 91 return s->status; 92 case SCOOP_CPR: 93 return s->power; 94 case SCOOP_CCR: 95 return s->ccr; 96 case SCOOP_IRR_IRM: 97 return s->irr; 98 case SCOOP_IMR: 99 return s->imr; 100 case SCOOP_ISR: 101 return s->isr; 102 case SCOOP_GPCR: 103 return s->gpio_dir; 104 case SCOOP_GPWR: 105 case SCOOP_GPRR: 106 return s->gpio_level; 107 default: 108 zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr); 109 } 110 111 return 0; 112 } 113 114 static void scoop_write(void *opaque, hwaddr addr, 115 uint64_t value, unsigned size) 116 { 117 ScoopInfo *s = (ScoopInfo *) opaque; 118 value &= 0xffff; 119 120 switch (addr & 0x3f) { 121 case SCOOP_MCR: 122 s->mcr = value; 123 break; 124 case SCOOP_CDR: 125 s->cdr = value; 126 break; 127 case SCOOP_CPR: 128 s->power = value; 129 if (value & 0x80) 130 s->power |= 0x8040; 131 break; 132 case SCOOP_CCR: 133 s->ccr = value; 134 break; 135 case SCOOP_IRR_IRM: 136 s->irr = value; 137 break; 138 case SCOOP_IMR: 139 s->imr = value; 140 break; 141 case SCOOP_ISR: 142 s->isr = value; 143 break; 144 case SCOOP_GPCR: 145 s->gpio_dir = value; 146 scoop_gpio_handler_update(s); 147 break; 148 case SCOOP_GPWR: 149 case SCOOP_GPRR: /* GPRR is probably R/O in real HW */ 150 s->gpio_level = value & s->gpio_dir; 151 scoop_gpio_handler_update(s); 152 break; 153 default: 154 zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr); 155 } 156 } 157 158 static const MemoryRegionOps scoop_ops = { 159 .read = scoop_read, 160 .write = scoop_write, 161 .endianness = DEVICE_NATIVE_ENDIAN, 162 }; 163 164 static void scoop_gpio_set(void *opaque, int line, int level) 165 { 166 ScoopInfo *s = (ScoopInfo *) opaque; 167 168 if (level) 169 s->gpio_level |= (1 << line); 170 else 171 s->gpio_level &= ~(1 << line); 172 } 173 174 static void scoop_init(Object *obj) 175 { 176 DeviceState *dev = DEVICE(obj); 177 ScoopInfo *s = SCOOP(obj); 178 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 179 180 s->status = 0x02; 181 qdev_init_gpio_out(dev, s->handler, 16); 182 qdev_init_gpio_in(dev, scoop_gpio_set, 16); 183 memory_region_init_io(&s->iomem, obj, &scoop_ops, s, "scoop", 0x1000); 184 185 sysbus_init_mmio(sbd, &s->iomem); 186 } 187 188 static int scoop_post_load(void *opaque, int version_id) 189 { 190 ScoopInfo *s = (ScoopInfo *) opaque; 191 int i; 192 uint32_t level; 193 194 level = s->gpio_level & s->gpio_dir; 195 196 for (i = 0; i < 16; i++) { 197 qemu_set_irq(s->handler[i], (level >> i) & 1); 198 } 199 200 s->prev_level = level; 201 202 return 0; 203 } 204 205 static bool is_version_0 (void *opaque, int version_id) 206 { 207 return version_id == 0; 208 } 209 210 static bool vmstate_scoop_validate(void *opaque, int version_id) 211 { 212 ScoopInfo *s = opaque; 213 214 return !(s->prev_level & 0xffff0000) && 215 !(s->gpio_level & 0xffff0000) && 216 !(s->gpio_dir & 0xffff0000); 217 } 218 219 static const VMStateDescription vmstate_scoop_regs = { 220 .name = "scoop", 221 .version_id = 1, 222 .minimum_version_id = 0, 223 .post_load = scoop_post_load, 224 .fields = (VMStateField[]) { 225 VMSTATE_UINT16(status, ScoopInfo), 226 VMSTATE_UINT16(power, ScoopInfo), 227 VMSTATE_UINT32(gpio_level, ScoopInfo), 228 VMSTATE_UINT32(gpio_dir, ScoopInfo), 229 VMSTATE_UINT32(prev_level, ScoopInfo), 230 VMSTATE_VALIDATE("irq levels are 16 bit", vmstate_scoop_validate), 231 VMSTATE_UINT16(mcr, ScoopInfo), 232 VMSTATE_UINT16(cdr, ScoopInfo), 233 VMSTATE_UINT16(ccr, ScoopInfo), 234 VMSTATE_UINT16(irr, ScoopInfo), 235 VMSTATE_UINT16(imr, ScoopInfo), 236 VMSTATE_UINT16(isr, ScoopInfo), 237 VMSTATE_UNUSED_TEST(is_version_0, 2), 238 VMSTATE_END_OF_LIST(), 239 }, 240 }; 241 242 static void scoop_sysbus_class_init(ObjectClass *klass, void *data) 243 { 244 DeviceClass *dc = DEVICE_CLASS(klass); 245 246 dc->desc = "Scoop2 Sharp custom ASIC"; 247 dc->vmsd = &vmstate_scoop_regs; 248 } 249 250 static const TypeInfo scoop_sysbus_info = { 251 .name = TYPE_SCOOP, 252 .parent = TYPE_SYS_BUS_DEVICE, 253 .instance_size = sizeof(ScoopInfo), 254 .instance_init = scoop_init, 255 .class_init = scoop_sysbus_class_init, 256 }; 257 258 static void scoop_register_types(void) 259 { 260 type_register_static(&scoop_sysbus_info); 261 } 262 263 type_init(scoop_register_types) 264 265 /* Write the bootloader parameters memory area. */ 266 267 #define MAGIC_CHG(a, b, c, d) ((d << 24) | (c << 16) | (b << 8) | a) 268 269 static struct QEMU_PACKED sl_param_info { 270 uint32_t comadj_keyword; 271 int32_t comadj; 272 273 uint32_t uuid_keyword; 274 char uuid[16]; 275 276 uint32_t touch_keyword; 277 int32_t touch_xp; 278 int32_t touch_yp; 279 int32_t touch_xd; 280 int32_t touch_yd; 281 282 uint32_t adadj_keyword; 283 int32_t adadj; 284 285 uint32_t phad_keyword; 286 int32_t phadadj; 287 } zaurus_bootparam = { 288 .comadj_keyword = MAGIC_CHG('C', 'M', 'A', 'D'), 289 .comadj = 125, 290 .uuid_keyword = MAGIC_CHG('U', 'U', 'I', 'D'), 291 .uuid = { -1 }, 292 .touch_keyword = MAGIC_CHG('T', 'U', 'C', 'H'), 293 .touch_xp = -1, 294 .adadj_keyword = MAGIC_CHG('B', 'V', 'A', 'D'), 295 .adadj = -1, 296 .phad_keyword = MAGIC_CHG('P', 'H', 'A', 'D'), 297 .phadadj = 0x01, 298 }; 299 300 void sl_bootparam_write(hwaddr ptr) 301 { 302 cpu_physical_memory_write(ptr, &zaurus_bootparam, 303 sizeof(struct sl_param_info)); 304 } 305