1 /* 2 * PC SMBus implementation 3 * splitted from acpi.c 4 * 5 * Copyright (c) 2006 Fabrice Bellard 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License version 2 as published by the Free Software Foundation. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/>. 19 */ 20 #include "qemu/osdep.h" 21 #include "hw/hw.h" 22 #include "hw/i2c/pm_smbus.h" 23 #include "hw/i2c/smbus_master.h" 24 25 #define SMBHSTSTS 0x00 26 #define SMBHSTCNT 0x02 27 #define SMBHSTCMD 0x03 28 #define SMBHSTADD 0x04 29 #define SMBHSTDAT0 0x05 30 #define SMBHSTDAT1 0x06 31 #define SMBBLKDAT 0x07 32 #define SMBAUXCTL 0x0d 33 34 #define STS_HOST_BUSY (1 << 0) 35 #define STS_INTR (1 << 1) 36 #define STS_DEV_ERR (1 << 2) 37 #define STS_BUS_ERR (1 << 3) 38 #define STS_FAILED (1 << 4) 39 #define STS_SMBALERT (1 << 5) 40 #define STS_INUSE_STS (1 << 6) 41 #define STS_BYTE_DONE (1 << 7) 42 /* Signs of successfully transaction end : 43 * ByteDoneStatus = 1 (STS_BYTE_DONE) and INTR = 1 (STS_INTR ) 44 */ 45 46 #define CTL_INTREN (1 << 0) 47 #define CTL_KILL (1 << 1) 48 #define CTL_LAST_BYTE (1 << 5) 49 #define CTL_START (1 << 6) 50 #define CTL_PEC_EN (1 << 7) 51 #define CTL_RETURN_MASK 0x1f 52 53 #define PROT_QUICK 0 54 #define PROT_BYTE 1 55 #define PROT_BYTE_DATA 2 56 #define PROT_WORD_DATA 3 57 #define PROT_PROC_CALL 4 58 #define PROT_BLOCK_DATA 5 59 #define PROT_I2C_BLOCK_READ 6 60 61 #define AUX_PEC (1 << 0) 62 #define AUX_BLK (1 << 1) 63 #define AUX_MASK 0x3 64 65 /*#define DEBUG*/ 66 67 #ifdef DEBUG 68 # define SMBUS_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 69 #else 70 # define SMBUS_DPRINTF(format, ...) do { } while (0) 71 #endif 72 73 74 static void smb_transaction(PMSMBus *s) 75 { 76 uint8_t prot = (s->smb_ctl >> 2) & 0x07; 77 uint8_t read = s->smb_addr & 0x01; 78 uint8_t cmd = s->smb_cmd; 79 uint8_t addr = s->smb_addr >> 1; 80 I2CBus *bus = s->smbus; 81 int ret; 82 83 SMBUS_DPRINTF("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot); 84 /* Transaction isn't exec if STS_DEV_ERR bit set */ 85 if ((s->smb_stat & STS_DEV_ERR) != 0) { 86 goto error; 87 } 88 89 switch(prot) { 90 case PROT_QUICK: 91 ret = smbus_quick_command(bus, addr, read); 92 goto done; 93 case PROT_BYTE: 94 if (read) { 95 ret = smbus_receive_byte(bus, addr); 96 goto data8; 97 } else { 98 ret = smbus_send_byte(bus, addr, cmd); 99 goto done; 100 } 101 case PROT_BYTE_DATA: 102 if (read) { 103 ret = smbus_read_byte(bus, addr, cmd); 104 goto data8; 105 } else { 106 ret = smbus_write_byte(bus, addr, cmd, s->smb_data0); 107 goto done; 108 } 109 break; 110 case PROT_WORD_DATA: 111 if (read) { 112 ret = smbus_read_word(bus, addr, cmd); 113 goto data16; 114 } else { 115 ret = smbus_write_word(bus, addr, cmd, 116 (s->smb_data1 << 8) | s->smb_data0); 117 goto done; 118 } 119 break; 120 case PROT_I2C_BLOCK_READ: 121 /* According to the Linux i2c-i801 driver: 122 * NB: page 240 of ICH5 datasheet shows that the R/#W 123 * bit should be cleared here, even when reading. 124 * However if SPD Write Disable is set (Lynx Point and later), 125 * the read will fail if we don't set the R/#W bit. 126 * So at least Linux may or may not set the read bit here. 127 * So just ignore the read bit for this command. 128 */ 129 if (i2c_start_transfer(bus, addr, 0)) { 130 goto error; 131 } 132 ret = i2c_send(bus, s->smb_data1); 133 if (ret) { 134 goto error; 135 } 136 if (i2c_start_transfer(bus, addr, 1)) { 137 goto error; 138 } 139 s->in_i2c_block_read = true; 140 s->smb_blkdata = i2c_recv(s->smbus); 141 s->op_done = false; 142 s->smb_stat |= STS_HOST_BUSY | STS_BYTE_DONE; 143 goto out; 144 145 case PROT_BLOCK_DATA: 146 if (read) { 147 ret = smbus_read_block(bus, addr, cmd, s->smb_data, 148 sizeof(s->smb_data), !s->i2c_enable, 149 !s->i2c_enable); 150 if (ret < 0) { 151 goto error; 152 } 153 s->smb_index = 0; 154 s->op_done = false; 155 if (s->smb_auxctl & AUX_BLK) { 156 s->smb_stat |= STS_INTR; 157 } else { 158 s->smb_blkdata = s->smb_data[0]; 159 s->smb_stat |= STS_HOST_BUSY | STS_BYTE_DONE; 160 } 161 s->smb_data0 = ret; 162 goto out; 163 } else { 164 if (s->smb_auxctl & AUX_BLK) { 165 if (s->smb_index != s->smb_data0) { 166 s->smb_index = 0; 167 goto error; 168 } 169 /* Data is already all written to the queue, just do 170 the operation. */ 171 s->smb_index = 0; 172 ret = smbus_write_block(bus, addr, cmd, s->smb_data, 173 s->smb_data0, !s->i2c_enable); 174 if (ret < 0) { 175 goto error; 176 } 177 s->op_done = true; 178 s->smb_stat |= STS_INTR; 179 s->smb_stat &= ~STS_HOST_BUSY; 180 } else { 181 s->op_done = false; 182 s->smb_stat |= STS_HOST_BUSY | STS_BYTE_DONE; 183 s->smb_data[0] = s->smb_blkdata; 184 s->smb_index = 0; 185 ret = 0; 186 } 187 goto out; 188 } 189 break; 190 default: 191 goto error; 192 } 193 abort(); 194 195 data16: 196 if (ret < 0) { 197 goto error; 198 } 199 s->smb_data1 = ret >> 8; 200 data8: 201 if (ret < 0) { 202 goto error; 203 } 204 s->smb_data0 = ret; 205 done: 206 if (ret < 0) { 207 goto error; 208 } 209 s->smb_stat |= STS_INTR; 210 out: 211 return; 212 213 error: 214 s->smb_stat |= STS_DEV_ERR; 215 return; 216 } 217 218 static void smb_transaction_start(PMSMBus *s) 219 { 220 if (s->smb_ctl & CTL_INTREN) { 221 smb_transaction(s); 222 s->start_transaction_on_status_read = false; 223 } else { 224 /* Do not execute immediately the command; it will be 225 * executed when guest will read SMB_STAT register. This 226 * is to work around a bug in AMIBIOS (that is working 227 * around another bug in some specific hardware) where 228 * it waits for STS_HOST_BUSY to be set before waiting 229 * checking for status. If STS_HOST_BUSY doesn't get 230 * set, it gets stuck. */ 231 s->smb_stat |= STS_HOST_BUSY; 232 s->start_transaction_on_status_read = true; 233 } 234 } 235 236 static bool 237 smb_irq_value(PMSMBus *s) 238 { 239 return ((s->smb_stat & ~STS_HOST_BUSY) != 0) && (s->smb_ctl & CTL_INTREN); 240 } 241 242 static bool 243 smb_byte_by_byte(PMSMBus *s) 244 { 245 if (s->op_done) { 246 return false; 247 } 248 if (s->in_i2c_block_read) { 249 return true; 250 } 251 return !(s->smb_auxctl & AUX_BLK); 252 } 253 254 static void smb_ioport_writeb(void *opaque, hwaddr addr, uint64_t val, 255 unsigned width) 256 { 257 PMSMBus *s = opaque; 258 uint8_t clear_byte_done; 259 260 SMBUS_DPRINTF("SMB writeb port=0x%04" HWADDR_PRIx 261 " val=0x%02" PRIx64 "\n", addr, val); 262 switch(addr) { 263 case SMBHSTSTS: 264 clear_byte_done = s->smb_stat & val & STS_BYTE_DONE; 265 s->smb_stat &= ~(val & ~STS_HOST_BUSY); 266 if (clear_byte_done && smb_byte_by_byte(s)) { 267 uint8_t read = s->smb_addr & 0x01; 268 269 if (s->in_i2c_block_read) { 270 /* See comment below PROT_I2C_BLOCK_READ above. */ 271 read = 1; 272 } 273 274 s->smb_index++; 275 if (s->smb_index >= PM_SMBUS_MAX_MSG_SIZE) { 276 s->smb_index = 0; 277 } 278 if (!read && s->smb_index == s->smb_data0) { 279 uint8_t prot = (s->smb_ctl >> 2) & 0x07; 280 uint8_t cmd = s->smb_cmd; 281 uint8_t addr = s->smb_addr >> 1; 282 int ret; 283 284 if (prot == PROT_I2C_BLOCK_READ) { 285 s->smb_stat |= STS_DEV_ERR; 286 goto out; 287 } 288 289 ret = smbus_write_block(s->smbus, addr, cmd, s->smb_data, 290 s->smb_data0, !s->i2c_enable); 291 if (ret < 0) { 292 s->smb_stat |= STS_DEV_ERR; 293 goto out; 294 } 295 s->op_done = true; 296 s->smb_stat |= STS_INTR; 297 s->smb_stat &= ~STS_HOST_BUSY; 298 } else if (!read) { 299 s->smb_data[s->smb_index] = s->smb_blkdata; 300 s->smb_stat |= STS_BYTE_DONE; 301 } else if (s->smb_ctl & CTL_LAST_BYTE) { 302 s->op_done = true; 303 if (s->in_i2c_block_read) { 304 s->in_i2c_block_read = false; 305 s->smb_blkdata = i2c_recv(s->smbus); 306 i2c_nack(s->smbus); 307 i2c_end_transfer(s->smbus); 308 } else { 309 s->smb_blkdata = s->smb_data[s->smb_index]; 310 } 311 s->smb_index = 0; 312 s->smb_stat |= STS_INTR; 313 s->smb_stat &= ~STS_HOST_BUSY; 314 } else { 315 if (s->in_i2c_block_read) { 316 s->smb_blkdata = i2c_recv(s->smbus); 317 } else { 318 s->smb_blkdata = s->smb_data[s->smb_index]; 319 } 320 s->smb_stat |= STS_BYTE_DONE; 321 } 322 } 323 break; 324 case SMBHSTCNT: 325 s->smb_ctl = val & ~CTL_START; /* CTL_START always reads 0 */ 326 if (val & CTL_START) { 327 if (!s->op_done) { 328 s->smb_index = 0; 329 s->op_done = true; 330 if (s->in_i2c_block_read) { 331 s->in_i2c_block_read = false; 332 i2c_end_transfer(s->smbus); 333 } 334 } 335 smb_transaction_start(s); 336 } 337 if (s->smb_ctl & CTL_KILL) { 338 s->op_done = true; 339 s->smb_index = 0; 340 s->smb_stat |= STS_FAILED; 341 s->smb_stat &= ~STS_HOST_BUSY; 342 } 343 break; 344 case SMBHSTCMD: 345 s->smb_cmd = val; 346 break; 347 case SMBHSTADD: 348 s->smb_addr = val; 349 break; 350 case SMBHSTDAT0: 351 s->smb_data0 = val; 352 break; 353 case SMBHSTDAT1: 354 s->smb_data1 = val; 355 break; 356 case SMBBLKDAT: 357 if (s->smb_index >= PM_SMBUS_MAX_MSG_SIZE) { 358 s->smb_index = 0; 359 } 360 if (s->smb_auxctl & AUX_BLK) { 361 s->smb_data[s->smb_index++] = val; 362 } else { 363 s->smb_blkdata = val; 364 } 365 break; 366 case SMBAUXCTL: 367 s->smb_auxctl = val & AUX_MASK; 368 break; 369 default: 370 break; 371 } 372 373 out: 374 if (s->set_irq) { 375 s->set_irq(s, smb_irq_value(s)); 376 } 377 } 378 379 static uint64_t smb_ioport_readb(void *opaque, hwaddr addr, unsigned width) 380 { 381 PMSMBus *s = opaque; 382 uint32_t val; 383 384 switch(addr) { 385 case SMBHSTSTS: 386 val = s->smb_stat; 387 if (s->start_transaction_on_status_read) { 388 /* execute command now */ 389 s->start_transaction_on_status_read = false; 390 s->smb_stat &= ~STS_HOST_BUSY; 391 smb_transaction(s); 392 } 393 break; 394 case SMBHSTCNT: 395 val = s->smb_ctl & CTL_RETURN_MASK; 396 break; 397 case SMBHSTCMD: 398 val = s->smb_cmd; 399 break; 400 case SMBHSTADD: 401 val = s->smb_addr; 402 break; 403 case SMBHSTDAT0: 404 val = s->smb_data0; 405 break; 406 case SMBHSTDAT1: 407 val = s->smb_data1; 408 break; 409 case SMBBLKDAT: 410 if (s->smb_auxctl & AUX_BLK && !s->in_i2c_block_read) { 411 if (s->smb_index >= PM_SMBUS_MAX_MSG_SIZE) { 412 s->smb_index = 0; 413 } 414 val = s->smb_data[s->smb_index++]; 415 if (!s->op_done && s->smb_index == s->smb_data0) { 416 s->op_done = true; 417 s->smb_index = 0; 418 s->smb_stat &= ~STS_HOST_BUSY; 419 } 420 } else { 421 val = s->smb_blkdata; 422 } 423 break; 424 case SMBAUXCTL: 425 val = s->smb_auxctl; 426 break; 427 default: 428 val = 0; 429 break; 430 } 431 SMBUS_DPRINTF("SMB readb port=0x%04" HWADDR_PRIx " val=0x%02x\n", 432 addr, val); 433 434 if (s->set_irq) { 435 s->set_irq(s, smb_irq_value(s)); 436 } 437 438 return val; 439 } 440 441 static void pm_smbus_reset(PMSMBus *s) 442 { 443 s->op_done = true; 444 s->smb_index = 0; 445 s->smb_stat = 0; 446 } 447 448 static const MemoryRegionOps pm_smbus_ops = { 449 .read = smb_ioport_readb, 450 .write = smb_ioport_writeb, 451 .valid.min_access_size = 1, 452 .valid.max_access_size = 1, 453 .endianness = DEVICE_LITTLE_ENDIAN, 454 }; 455 456 void pm_smbus_init(DeviceState *parent, PMSMBus *smb, bool force_aux_blk) 457 { 458 smb->op_done = true; 459 smb->reset = pm_smbus_reset; 460 smb->smbus = i2c_init_bus(parent, "i2c"); 461 if (force_aux_blk) { 462 smb->smb_auxctl |= AUX_BLK; 463 } 464 memory_region_init_io(&smb->io, OBJECT(parent), &pm_smbus_ops, smb, 465 "pm-smbus", 64); 466 } 467