1 /* 2 * ARM Integrator CP System emulation. 3 * 4 * Copyright (c) 2005-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qapi/error.h" 12 #include "cpu.h" 13 #include "hw/sysbus.h" 14 #include "migration/vmstate.h" 15 #include "hw/boards.h" 16 #include "hw/arm/boot.h" 17 #include "hw/misc/arm_integrator_debug.h" 18 #include "hw/net/smc91c111.h" 19 #include "net/net.h" 20 #include "exec/address-spaces.h" 21 #include "sysemu/sysemu.h" 22 #include "qemu/error-report.h" 23 #include "hw/char/pl011.h" 24 #include "hw/irq.h" 25 26 #define TYPE_INTEGRATOR_CM "integrator_core" 27 #define INTEGRATOR_CM(obj) \ 28 OBJECT_CHECK(IntegratorCMState, (obj), TYPE_INTEGRATOR_CM) 29 30 typedef struct IntegratorCMState { 31 /*< private >*/ 32 SysBusDevice parent_obj; 33 /*< public >*/ 34 35 MemoryRegion iomem; 36 uint32_t memsz; 37 MemoryRegion flash; 38 uint32_t cm_osc; 39 uint32_t cm_ctrl; 40 uint32_t cm_lock; 41 uint32_t cm_auxosc; 42 uint32_t cm_sdram; 43 uint32_t cm_init; 44 uint32_t cm_flags; 45 uint32_t cm_nvflags; 46 uint32_t cm_refcnt_offset; 47 uint32_t int_level; 48 uint32_t irq_enabled; 49 uint32_t fiq_enabled; 50 } IntegratorCMState; 51 52 static uint8_t integrator_spd[128] = { 53 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1, 54 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40 55 }; 56 57 static const VMStateDescription vmstate_integratorcm = { 58 .name = "integratorcm", 59 .version_id = 1, 60 .minimum_version_id = 1, 61 .fields = (VMStateField[]) { 62 VMSTATE_UINT32(cm_osc, IntegratorCMState), 63 VMSTATE_UINT32(cm_ctrl, IntegratorCMState), 64 VMSTATE_UINT32(cm_lock, IntegratorCMState), 65 VMSTATE_UINT32(cm_auxosc, IntegratorCMState), 66 VMSTATE_UINT32(cm_sdram, IntegratorCMState), 67 VMSTATE_UINT32(cm_init, IntegratorCMState), 68 VMSTATE_UINT32(cm_flags, IntegratorCMState), 69 VMSTATE_UINT32(cm_nvflags, IntegratorCMState), 70 VMSTATE_UINT32(int_level, IntegratorCMState), 71 VMSTATE_UINT32(irq_enabled, IntegratorCMState), 72 VMSTATE_UINT32(fiq_enabled, IntegratorCMState), 73 VMSTATE_END_OF_LIST() 74 } 75 }; 76 77 static uint64_t integratorcm_read(void *opaque, hwaddr offset, 78 unsigned size) 79 { 80 IntegratorCMState *s = opaque; 81 if (offset >= 0x100 && offset < 0x200) { 82 /* CM_SPD */ 83 if (offset >= 0x180) 84 return 0; 85 return integrator_spd[offset >> 2]; 86 } 87 switch (offset >> 2) { 88 case 0: /* CM_ID */ 89 return 0x411a3001; 90 case 1: /* CM_PROC */ 91 return 0; 92 case 2: /* CM_OSC */ 93 return s->cm_osc; 94 case 3: /* CM_CTRL */ 95 return s->cm_ctrl; 96 case 4: /* CM_STAT */ 97 return 0x00100000; 98 case 5: /* CM_LOCK */ 99 if (s->cm_lock == 0xa05f) { 100 return 0x1a05f; 101 } else { 102 return s->cm_lock; 103 } 104 case 6: /* CM_LMBUSCNT */ 105 /* ??? High frequency timer. */ 106 hw_error("integratorcm_read: CM_LMBUSCNT"); 107 case 7: /* CM_AUXOSC */ 108 return s->cm_auxosc; 109 case 8: /* CM_SDRAM */ 110 return s->cm_sdram; 111 case 9: /* CM_INIT */ 112 return s->cm_init; 113 case 10: /* CM_REFCNT */ 114 /* This register, CM_REFCNT, provides a 32-bit count value. 115 * The count increments at the fixed reference clock frequency of 24MHz 116 * and can be used as a real-time counter. 117 */ 118 return (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24, 119 1000) - s->cm_refcnt_offset; 120 case 12: /* CM_FLAGS */ 121 return s->cm_flags; 122 case 14: /* CM_NVFLAGS */ 123 return s->cm_nvflags; 124 case 16: /* CM_IRQ_STAT */ 125 return s->int_level & s->irq_enabled; 126 case 17: /* CM_IRQ_RSTAT */ 127 return s->int_level; 128 case 18: /* CM_IRQ_ENSET */ 129 return s->irq_enabled; 130 case 20: /* CM_SOFT_INTSET */ 131 return s->int_level & 1; 132 case 24: /* CM_FIQ_STAT */ 133 return s->int_level & s->fiq_enabled; 134 case 25: /* CM_FIQ_RSTAT */ 135 return s->int_level; 136 case 26: /* CM_FIQ_ENSET */ 137 return s->fiq_enabled; 138 case 32: /* CM_VOLTAGE_CTL0 */ 139 case 33: /* CM_VOLTAGE_CTL1 */ 140 case 34: /* CM_VOLTAGE_CTL2 */ 141 case 35: /* CM_VOLTAGE_CTL3 */ 142 /* ??? Voltage control unimplemented. */ 143 return 0; 144 default: 145 hw_error("integratorcm_read: Unimplemented offset 0x%x\n", 146 (int)offset); 147 return 0; 148 } 149 } 150 151 static void integratorcm_do_remap(IntegratorCMState *s) 152 { 153 /* Sync memory region state with CM_CTRL REMAP bit: 154 * bit 0 => flash at address 0; bit 1 => RAM 155 */ 156 memory_region_set_enabled(&s->flash, !(s->cm_ctrl & 4)); 157 } 158 159 static void integratorcm_set_ctrl(IntegratorCMState *s, uint32_t value) 160 { 161 if (value & 8) { 162 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 163 } 164 if ((s->cm_ctrl ^ value) & 1) { 165 /* (value & 1) != 0 means the green "MISC LED" is lit. 166 * We don't have any nice place to display LEDs. printf is a bad 167 * idea because Linux uses the LED as a heartbeat and the output 168 * will swamp anything else on the terminal. 169 */ 170 } 171 /* Note that the RESET bit [3] always reads as zero */ 172 s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5); 173 integratorcm_do_remap(s); 174 } 175 176 static void integratorcm_update(IntegratorCMState *s) 177 { 178 /* ??? The CPU irq/fiq is raised when either the core module or base PIC 179 are active. */ 180 if (s->int_level & (s->irq_enabled | s->fiq_enabled)) 181 hw_error("Core module interrupt\n"); 182 } 183 184 static void integratorcm_write(void *opaque, hwaddr offset, 185 uint64_t value, unsigned size) 186 { 187 IntegratorCMState *s = opaque; 188 switch (offset >> 2) { 189 case 2: /* CM_OSC */ 190 if (s->cm_lock == 0xa05f) 191 s->cm_osc = value; 192 break; 193 case 3: /* CM_CTRL */ 194 integratorcm_set_ctrl(s, value); 195 break; 196 case 5: /* CM_LOCK */ 197 s->cm_lock = value & 0xffff; 198 break; 199 case 7: /* CM_AUXOSC */ 200 if (s->cm_lock == 0xa05f) 201 s->cm_auxosc = value; 202 break; 203 case 8: /* CM_SDRAM */ 204 s->cm_sdram = value; 205 break; 206 case 9: /* CM_INIT */ 207 /* ??? This can change the memory bus frequency. */ 208 s->cm_init = value; 209 break; 210 case 12: /* CM_FLAGSS */ 211 s->cm_flags |= value; 212 break; 213 case 13: /* CM_FLAGSC */ 214 s->cm_flags &= ~value; 215 break; 216 case 14: /* CM_NVFLAGSS */ 217 s->cm_nvflags |= value; 218 break; 219 case 15: /* CM_NVFLAGSS */ 220 s->cm_nvflags &= ~value; 221 break; 222 case 18: /* CM_IRQ_ENSET */ 223 s->irq_enabled |= value; 224 integratorcm_update(s); 225 break; 226 case 19: /* CM_IRQ_ENCLR */ 227 s->irq_enabled &= ~value; 228 integratorcm_update(s); 229 break; 230 case 20: /* CM_SOFT_INTSET */ 231 s->int_level |= (value & 1); 232 integratorcm_update(s); 233 break; 234 case 21: /* CM_SOFT_INTCLR */ 235 s->int_level &= ~(value & 1); 236 integratorcm_update(s); 237 break; 238 case 26: /* CM_FIQ_ENSET */ 239 s->fiq_enabled |= value; 240 integratorcm_update(s); 241 break; 242 case 27: /* CM_FIQ_ENCLR */ 243 s->fiq_enabled &= ~value; 244 integratorcm_update(s); 245 break; 246 case 32: /* CM_VOLTAGE_CTL0 */ 247 case 33: /* CM_VOLTAGE_CTL1 */ 248 case 34: /* CM_VOLTAGE_CTL2 */ 249 case 35: /* CM_VOLTAGE_CTL3 */ 250 /* ??? Voltage control unimplemented. */ 251 break; 252 default: 253 hw_error("integratorcm_write: Unimplemented offset 0x%x\n", 254 (int)offset); 255 break; 256 } 257 } 258 259 /* Integrator/CM control registers. */ 260 261 static const MemoryRegionOps integratorcm_ops = { 262 .read = integratorcm_read, 263 .write = integratorcm_write, 264 .endianness = DEVICE_NATIVE_ENDIAN, 265 }; 266 267 static void integratorcm_init(Object *obj) 268 { 269 IntegratorCMState *s = INTEGRATOR_CM(obj); 270 271 s->cm_osc = 0x01000048; 272 /* ??? What should the high bits of this value be? */ 273 s->cm_auxosc = 0x0007feff; 274 s->cm_sdram = 0x00011122; 275 memcpy(integrator_spd + 73, "QEMU-MEMORY", 11); 276 s->cm_init = 0x00000112; 277 s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24, 278 1000); 279 280 /* ??? Save/restore. */ 281 } 282 283 static void integratorcm_realize(DeviceState *d, Error **errp) 284 { 285 IntegratorCMState *s = INTEGRATOR_CM(d); 286 SysBusDevice *dev = SYS_BUS_DEVICE(d); 287 Error *local_err = NULL; 288 289 memory_region_init_ram(&s->flash, OBJECT(d), "integrator.flash", 0x100000, 290 &local_err); 291 if (local_err) { 292 error_propagate(errp, local_err); 293 return; 294 } 295 296 memory_region_init_io(&s->iomem, OBJECT(d), &integratorcm_ops, s, 297 "integratorcm", 0x00800000); 298 sysbus_init_mmio(dev, &s->iomem); 299 300 integratorcm_do_remap(s); 301 302 if (s->memsz >= 256) { 303 integrator_spd[31] = 64; 304 s->cm_sdram |= 0x10; 305 } else if (s->memsz >= 128) { 306 integrator_spd[31] = 32; 307 s->cm_sdram |= 0x0c; 308 } else if (s->memsz >= 64) { 309 integrator_spd[31] = 16; 310 s->cm_sdram |= 0x08; 311 } else if (s->memsz >= 32) { 312 integrator_spd[31] = 4; 313 s->cm_sdram |= 0x04; 314 } else { 315 integrator_spd[31] = 2; 316 } 317 } 318 319 /* Integrator/CP hardware emulation. */ 320 /* Primary interrupt controller. */ 321 322 #define TYPE_INTEGRATOR_PIC "integrator_pic" 323 #define INTEGRATOR_PIC(obj) \ 324 OBJECT_CHECK(icp_pic_state, (obj), TYPE_INTEGRATOR_PIC) 325 326 typedef struct icp_pic_state { 327 /*< private >*/ 328 SysBusDevice parent_obj; 329 /*< public >*/ 330 331 MemoryRegion iomem; 332 uint32_t level; 333 uint32_t irq_enabled; 334 uint32_t fiq_enabled; 335 qemu_irq parent_irq; 336 qemu_irq parent_fiq; 337 } icp_pic_state; 338 339 static const VMStateDescription vmstate_icp_pic = { 340 .name = "icp_pic", 341 .version_id = 1, 342 .minimum_version_id = 1, 343 .fields = (VMStateField[]) { 344 VMSTATE_UINT32(level, icp_pic_state), 345 VMSTATE_UINT32(irq_enabled, icp_pic_state), 346 VMSTATE_UINT32(fiq_enabled, icp_pic_state), 347 VMSTATE_END_OF_LIST() 348 } 349 }; 350 351 static void icp_pic_update(icp_pic_state *s) 352 { 353 uint32_t flags; 354 355 flags = (s->level & s->irq_enabled); 356 qemu_set_irq(s->parent_irq, flags != 0); 357 flags = (s->level & s->fiq_enabled); 358 qemu_set_irq(s->parent_fiq, flags != 0); 359 } 360 361 static void icp_pic_set_irq(void *opaque, int irq, int level) 362 { 363 icp_pic_state *s = (icp_pic_state *)opaque; 364 if (level) 365 s->level |= 1 << irq; 366 else 367 s->level &= ~(1 << irq); 368 icp_pic_update(s); 369 } 370 371 static uint64_t icp_pic_read(void *opaque, hwaddr offset, 372 unsigned size) 373 { 374 icp_pic_state *s = (icp_pic_state *)opaque; 375 376 switch (offset >> 2) { 377 case 0: /* IRQ_STATUS */ 378 return s->level & s->irq_enabled; 379 case 1: /* IRQ_RAWSTAT */ 380 return s->level; 381 case 2: /* IRQ_ENABLESET */ 382 return s->irq_enabled; 383 case 4: /* INT_SOFTSET */ 384 return s->level & 1; 385 case 8: /* FRQ_STATUS */ 386 return s->level & s->fiq_enabled; 387 case 9: /* FRQ_RAWSTAT */ 388 return s->level; 389 case 10: /* FRQ_ENABLESET */ 390 return s->fiq_enabled; 391 case 3: /* IRQ_ENABLECLR */ 392 case 5: /* INT_SOFTCLR */ 393 case 11: /* FRQ_ENABLECLR */ 394 default: 395 printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset); 396 return 0; 397 } 398 } 399 400 static void icp_pic_write(void *opaque, hwaddr offset, 401 uint64_t value, unsigned size) 402 { 403 icp_pic_state *s = (icp_pic_state *)opaque; 404 405 switch (offset >> 2) { 406 case 2: /* IRQ_ENABLESET */ 407 s->irq_enabled |= value; 408 break; 409 case 3: /* IRQ_ENABLECLR */ 410 s->irq_enabled &= ~value; 411 break; 412 case 4: /* INT_SOFTSET */ 413 if (value & 1) 414 icp_pic_set_irq(s, 0, 1); 415 break; 416 case 5: /* INT_SOFTCLR */ 417 if (value & 1) 418 icp_pic_set_irq(s, 0, 0); 419 break; 420 case 10: /* FRQ_ENABLESET */ 421 s->fiq_enabled |= value; 422 break; 423 case 11: /* FRQ_ENABLECLR */ 424 s->fiq_enabled &= ~value; 425 break; 426 case 0: /* IRQ_STATUS */ 427 case 1: /* IRQ_RAWSTAT */ 428 case 8: /* FRQ_STATUS */ 429 case 9: /* FRQ_RAWSTAT */ 430 default: 431 printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset); 432 return; 433 } 434 icp_pic_update(s); 435 } 436 437 static const MemoryRegionOps icp_pic_ops = { 438 .read = icp_pic_read, 439 .write = icp_pic_write, 440 .endianness = DEVICE_NATIVE_ENDIAN, 441 }; 442 443 static void icp_pic_init(Object *obj) 444 { 445 DeviceState *dev = DEVICE(obj); 446 icp_pic_state *s = INTEGRATOR_PIC(obj); 447 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 448 449 qdev_init_gpio_in(dev, icp_pic_set_irq, 32); 450 sysbus_init_irq(sbd, &s->parent_irq); 451 sysbus_init_irq(sbd, &s->parent_fiq); 452 memory_region_init_io(&s->iomem, obj, &icp_pic_ops, s, 453 "icp-pic", 0x00800000); 454 sysbus_init_mmio(sbd, &s->iomem); 455 } 456 457 /* CP control registers. */ 458 459 #define TYPE_ICP_CONTROL_REGS "icp-ctrl-regs" 460 #define ICP_CONTROL_REGS(obj) \ 461 OBJECT_CHECK(ICPCtrlRegsState, (obj), TYPE_ICP_CONTROL_REGS) 462 463 typedef struct ICPCtrlRegsState { 464 /*< private >*/ 465 SysBusDevice parent_obj; 466 /*< public >*/ 467 468 MemoryRegion iomem; 469 470 qemu_irq mmc_irq; 471 uint32_t intreg_state; 472 } ICPCtrlRegsState; 473 474 #define ICP_GPIO_MMC_WPROT "mmc-wprot" 475 #define ICP_GPIO_MMC_CARDIN "mmc-cardin" 476 477 #define ICP_INTREG_WPROT (1 << 0) 478 #define ICP_INTREG_CARDIN (1 << 3) 479 480 static const VMStateDescription vmstate_icp_control = { 481 .name = "icp_control", 482 .version_id = 1, 483 .minimum_version_id = 1, 484 .fields = (VMStateField[]) { 485 VMSTATE_UINT32(intreg_state, ICPCtrlRegsState), 486 VMSTATE_END_OF_LIST() 487 } 488 }; 489 490 static uint64_t icp_control_read(void *opaque, hwaddr offset, 491 unsigned size) 492 { 493 ICPCtrlRegsState *s = opaque; 494 495 switch (offset >> 2) { 496 case 0: /* CP_IDFIELD */ 497 return 0x41034003; 498 case 1: /* CP_FLASHPROG */ 499 return 0; 500 case 2: /* CP_INTREG */ 501 return s->intreg_state; 502 case 3: /* CP_DECODE */ 503 return 0x11; 504 default: 505 hw_error("icp_control_read: Bad offset %x\n", (int)offset); 506 return 0; 507 } 508 } 509 510 static void icp_control_write(void *opaque, hwaddr offset, 511 uint64_t value, unsigned size) 512 { 513 ICPCtrlRegsState *s = opaque; 514 515 switch (offset >> 2) { 516 case 2: /* CP_INTREG */ 517 s->intreg_state &= ~(value & ICP_INTREG_CARDIN); 518 qemu_set_irq(s->mmc_irq, !!(s->intreg_state & ICP_INTREG_CARDIN)); 519 break; 520 case 1: /* CP_FLASHPROG */ 521 case 3: /* CP_DECODE */ 522 /* Nothing interesting implemented yet. */ 523 break; 524 default: 525 hw_error("icp_control_write: Bad offset %x\n", (int)offset); 526 } 527 } 528 529 static const MemoryRegionOps icp_control_ops = { 530 .read = icp_control_read, 531 .write = icp_control_write, 532 .endianness = DEVICE_NATIVE_ENDIAN, 533 }; 534 535 static void icp_control_mmc_wprot(void *opaque, int line, int level) 536 { 537 ICPCtrlRegsState *s = opaque; 538 539 s->intreg_state &= ~ICP_INTREG_WPROT; 540 if (level) { 541 s->intreg_state |= ICP_INTREG_WPROT; 542 } 543 } 544 545 static void icp_control_mmc_cardin(void *opaque, int line, int level) 546 { 547 ICPCtrlRegsState *s = opaque; 548 549 /* line is released by writing to CP_INTREG */ 550 if (level) { 551 s->intreg_state |= ICP_INTREG_CARDIN; 552 qemu_set_irq(s->mmc_irq, 1); 553 } 554 } 555 556 static void icp_control_init(Object *obj) 557 { 558 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 559 ICPCtrlRegsState *s = ICP_CONTROL_REGS(obj); 560 DeviceState *dev = DEVICE(obj); 561 562 memory_region_init_io(&s->iomem, OBJECT(s), &icp_control_ops, s, 563 "icp_ctrl_regs", 0x00800000); 564 sysbus_init_mmio(sbd, &s->iomem); 565 566 qdev_init_gpio_in_named(dev, icp_control_mmc_wprot, ICP_GPIO_MMC_WPROT, 1); 567 qdev_init_gpio_in_named(dev, icp_control_mmc_cardin, 568 ICP_GPIO_MMC_CARDIN, 1); 569 sysbus_init_irq(sbd, &s->mmc_irq); 570 } 571 572 573 /* Board init. */ 574 575 static struct arm_boot_info integrator_binfo = { 576 .loader_start = 0x0, 577 .board_id = 0x113, 578 }; 579 580 static void integratorcp_init(MachineState *machine) 581 { 582 ram_addr_t ram_size = machine->ram_size; 583 const char *kernel_filename = machine->kernel_filename; 584 const char *kernel_cmdline = machine->kernel_cmdline; 585 const char *initrd_filename = machine->initrd_filename; 586 Object *cpuobj; 587 ARMCPU *cpu; 588 MemoryRegion *address_space_mem = get_system_memory(); 589 MemoryRegion *ram = g_new(MemoryRegion, 1); 590 MemoryRegion *ram_alias = g_new(MemoryRegion, 1); 591 qemu_irq pic[32]; 592 DeviceState *dev, *sic, *icp; 593 int i; 594 595 cpuobj = object_new(machine->cpu_type); 596 597 /* By default ARM1176 CPUs have EL3 enabled. This board does not 598 * currently support EL3 so the CPU EL3 property is disabled before 599 * realization. 600 */ 601 if (object_property_find(cpuobj, "has_el3", NULL)) { 602 object_property_set_bool(cpuobj, false, "has_el3", &error_fatal); 603 } 604 605 object_property_set_bool(cpuobj, true, "realized", &error_fatal); 606 607 cpu = ARM_CPU(cpuobj); 608 609 memory_region_allocate_system_memory(ram, NULL, "integrator.ram", 610 ram_size); 611 /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */ 612 /* ??? RAM should repeat to fill physical memory space. */ 613 /* SDRAM at address zero*/ 614 memory_region_add_subregion(address_space_mem, 0, ram); 615 /* And again at address 0x80000000 */ 616 memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size); 617 memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias); 618 619 dev = qdev_create(NULL, TYPE_INTEGRATOR_CM); 620 qdev_prop_set_uint32(dev, "memsz", ram_size >> 20); 621 qdev_init_nofail(dev); 622 sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000); 623 624 dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000, 625 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ), 626 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ), 627 NULL); 628 for (i = 0; i < 32; i++) { 629 pic[i] = qdev_get_gpio_in(dev, i); 630 } 631 sic = sysbus_create_simple(TYPE_INTEGRATOR_PIC, 0xca000000, pic[26]); 632 sysbus_create_varargs("integrator_pit", 0x13000000, 633 pic[5], pic[6], pic[7], NULL); 634 sysbus_create_simple("pl031", 0x15000000, pic[8]); 635 pl011_create(0x16000000, pic[1], serial_hd(0)); 636 pl011_create(0x17000000, pic[2], serial_hd(1)); 637 icp = sysbus_create_simple(TYPE_ICP_CONTROL_REGS, 0xcb000000, 638 qdev_get_gpio_in(sic, 3)); 639 sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]); 640 sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]); 641 sysbus_create_simple(TYPE_INTEGRATOR_DEBUG, 0x1a000000, 0); 642 643 dev = sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL); 644 qdev_connect_gpio_out(dev, 0, 645 qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0)); 646 qdev_connect_gpio_out(dev, 1, 647 qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0)); 648 649 if (nd_table[0].used) 650 smc91c111_init(&nd_table[0], 0xc8000000, pic[27]); 651 652 sysbus_create_simple("pl110", 0xc0000000, pic[22]); 653 654 integrator_binfo.ram_size = ram_size; 655 integrator_binfo.kernel_filename = kernel_filename; 656 integrator_binfo.kernel_cmdline = kernel_cmdline; 657 integrator_binfo.initrd_filename = initrd_filename; 658 arm_load_kernel(cpu, &integrator_binfo); 659 } 660 661 static void integratorcp_machine_init(MachineClass *mc) 662 { 663 mc->desc = "ARM Integrator/CP (ARM926EJ-S)"; 664 mc->init = integratorcp_init; 665 mc->ignore_memory_transaction_failures = true; 666 mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); 667 } 668 669 DEFINE_MACHINE("integratorcp", integratorcp_machine_init) 670 671 static Property core_properties[] = { 672 DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0), 673 DEFINE_PROP_END_OF_LIST(), 674 }; 675 676 static void core_class_init(ObjectClass *klass, void *data) 677 { 678 DeviceClass *dc = DEVICE_CLASS(klass); 679 680 dc->props = core_properties; 681 dc->realize = integratorcm_realize; 682 dc->vmsd = &vmstate_integratorcm; 683 } 684 685 static void icp_pic_class_init(ObjectClass *klass, void *data) 686 { 687 DeviceClass *dc = DEVICE_CLASS(klass); 688 689 dc->vmsd = &vmstate_icp_pic; 690 } 691 692 static void icp_control_class_init(ObjectClass *klass, void *data) 693 { 694 DeviceClass *dc = DEVICE_CLASS(klass); 695 696 dc->vmsd = &vmstate_icp_control; 697 } 698 699 static const TypeInfo core_info = { 700 .name = TYPE_INTEGRATOR_CM, 701 .parent = TYPE_SYS_BUS_DEVICE, 702 .instance_size = sizeof(IntegratorCMState), 703 .instance_init = integratorcm_init, 704 .class_init = core_class_init, 705 }; 706 707 static const TypeInfo icp_pic_info = { 708 .name = TYPE_INTEGRATOR_PIC, 709 .parent = TYPE_SYS_BUS_DEVICE, 710 .instance_size = sizeof(icp_pic_state), 711 .instance_init = icp_pic_init, 712 .class_init = icp_pic_class_init, 713 }; 714 715 static const TypeInfo icp_ctrl_regs_info = { 716 .name = TYPE_ICP_CONTROL_REGS, 717 .parent = TYPE_SYS_BUS_DEVICE, 718 .instance_size = sizeof(ICPCtrlRegsState), 719 .instance_init = icp_control_init, 720 .class_init = icp_control_class_init, 721 }; 722 723 static void integratorcp_register_types(void) 724 { 725 type_register_static(&icp_pic_info); 726 type_register_static(&core_info); 727 type_register_static(&icp_ctrl_regs_info); 728 } 729 730 type_init(integratorcp_register_types) 731