1 /* 2 * Status and system control registers for Xilinx Zynq Platform 3 * 4 * Copyright (c) 2011 Michal Simek <monstr@monstr.eu> 5 * Copyright (c) 2012 PetaLogix Pty Ltd. 6 * Based on hw/arm_sysctl.c, written by Paul Brook 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 * 13 * You should have received a copy of the GNU General Public License along 14 * with this program; if not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include "qemu/osdep.h" 18 #include "hw/hw.h" 19 #include "qemu/timer.h" 20 #include "hw/sysbus.h" 21 #include "migration/vmstate.h" 22 #include "sysemu/sysemu.h" 23 #include "qemu/log.h" 24 #include "qemu/module.h" 25 26 #ifndef ZYNQ_SLCR_ERR_DEBUG 27 #define ZYNQ_SLCR_ERR_DEBUG 0 28 #endif 29 30 #define DB_PRINT(...) do { \ 31 if (ZYNQ_SLCR_ERR_DEBUG) { \ 32 fprintf(stderr, ": %s: ", __func__); \ 33 fprintf(stderr, ## __VA_ARGS__); \ 34 } \ 35 } while (0) 36 37 #define XILINX_LOCK_KEY 0x767b 38 #define XILINX_UNLOCK_KEY 0xdf0d 39 40 #define R_PSS_RST_CTRL_SOFT_RST 0x1 41 42 enum { 43 SCL = 0x000 / 4, 44 LOCK, 45 UNLOCK, 46 LOCKSTA, 47 48 ARM_PLL_CTRL = 0x100 / 4, 49 DDR_PLL_CTRL, 50 IO_PLL_CTRL, 51 PLL_STATUS, 52 ARM_PLL_CFG, 53 DDR_PLL_CFG, 54 IO_PLL_CFG, 55 56 ARM_CLK_CTRL = 0x120 / 4, 57 DDR_CLK_CTRL, 58 DCI_CLK_CTRL, 59 APER_CLK_CTRL, 60 USB0_CLK_CTRL, 61 USB1_CLK_CTRL, 62 GEM0_RCLK_CTRL, 63 GEM1_RCLK_CTRL, 64 GEM0_CLK_CTRL, 65 GEM1_CLK_CTRL, 66 SMC_CLK_CTRL, 67 LQSPI_CLK_CTRL, 68 SDIO_CLK_CTRL, 69 UART_CLK_CTRL, 70 SPI_CLK_CTRL, 71 CAN_CLK_CTRL, 72 CAN_MIOCLK_CTRL, 73 DBG_CLK_CTRL, 74 PCAP_CLK_CTRL, 75 TOPSW_CLK_CTRL, 76 77 #define FPGA_CTRL_REGS(n, start) \ 78 FPGA ## n ## _CLK_CTRL = (start) / 4, \ 79 FPGA ## n ## _THR_CTRL, \ 80 FPGA ## n ## _THR_CNT, \ 81 FPGA ## n ## _THR_STA, 82 FPGA_CTRL_REGS(0, 0x170) 83 FPGA_CTRL_REGS(1, 0x180) 84 FPGA_CTRL_REGS(2, 0x190) 85 FPGA_CTRL_REGS(3, 0x1a0) 86 87 BANDGAP_TRIP = 0x1b8 / 4, 88 PLL_PREDIVISOR = 0x1c0 / 4, 89 CLK_621_TRUE, 90 91 PSS_RST_CTRL = 0x200 / 4, 92 DDR_RST_CTRL, 93 TOPSW_RESET_CTRL, 94 DMAC_RST_CTRL, 95 USB_RST_CTRL, 96 GEM_RST_CTRL, 97 SDIO_RST_CTRL, 98 SPI_RST_CTRL, 99 CAN_RST_CTRL, 100 I2C_RST_CTRL, 101 UART_RST_CTRL, 102 GPIO_RST_CTRL, 103 LQSPI_RST_CTRL, 104 SMC_RST_CTRL, 105 OCM_RST_CTRL, 106 FPGA_RST_CTRL = 0x240 / 4, 107 A9_CPU_RST_CTRL, 108 109 RS_AWDT_CTRL = 0x24c / 4, 110 RST_REASON, 111 112 REBOOT_STATUS = 0x258 / 4, 113 BOOT_MODE, 114 115 APU_CTRL = 0x300 / 4, 116 WDT_CLK_SEL, 117 118 TZ_DMA_NS = 0x440 / 4, 119 TZ_DMA_IRQ_NS, 120 TZ_DMA_PERIPH_NS, 121 122 PSS_IDCODE = 0x530 / 4, 123 124 DDR_URGENT = 0x600 / 4, 125 DDR_CAL_START = 0x60c / 4, 126 DDR_REF_START = 0x614 / 4, 127 DDR_CMD_STA, 128 DDR_URGENT_SEL, 129 DDR_DFI_STATUS, 130 131 MIO = 0x700 / 4, 132 #define MIO_LENGTH 54 133 134 MIO_LOOPBACK = 0x804 / 4, 135 MIO_MST_TRI0, 136 MIO_MST_TRI1, 137 138 SD0_WP_CD_SEL = 0x830 / 4, 139 SD1_WP_CD_SEL, 140 141 LVL_SHFTR_EN = 0x900 / 4, 142 OCM_CFG = 0x910 / 4, 143 144 CPU_RAM = 0xa00 / 4, 145 146 IOU = 0xa30 / 4, 147 148 DMAC_RAM = 0xa50 / 4, 149 150 AFI0 = 0xa60 / 4, 151 AFI1 = AFI0 + 3, 152 AFI2 = AFI1 + 3, 153 AFI3 = AFI2 + 3, 154 #define AFI_LENGTH 3 155 156 OCM = 0xa90 / 4, 157 158 DEVCI_RAM = 0xaa0 / 4, 159 160 CSG_RAM = 0xab0 / 4, 161 162 GPIOB_CTRL = 0xb00 / 4, 163 GPIOB_CFG_CMOS18, 164 GPIOB_CFG_CMOS25, 165 GPIOB_CFG_CMOS33, 166 GPIOB_CFG_HSTL = 0xb14 / 4, 167 GPIOB_DRVR_BIAS_CTRL, 168 169 DDRIOB = 0xb40 / 4, 170 #define DDRIOB_LENGTH 14 171 }; 172 173 #define ZYNQ_SLCR_MMIO_SIZE 0x1000 174 #define ZYNQ_SLCR_NUM_REGS (ZYNQ_SLCR_MMIO_SIZE / 4) 175 176 #define TYPE_ZYNQ_SLCR "xilinx,zynq_slcr" 177 #define ZYNQ_SLCR(obj) OBJECT_CHECK(ZynqSLCRState, (obj), TYPE_ZYNQ_SLCR) 178 179 typedef struct ZynqSLCRState { 180 SysBusDevice parent_obj; 181 182 MemoryRegion iomem; 183 184 uint32_t regs[ZYNQ_SLCR_NUM_REGS]; 185 } ZynqSLCRState; 186 187 static void zynq_slcr_reset(DeviceState *d) 188 { 189 ZynqSLCRState *s = ZYNQ_SLCR(d); 190 int i; 191 192 DB_PRINT("RESET\n"); 193 194 s->regs[LOCKSTA] = 1; 195 /* 0x100 - 0x11C */ 196 s->regs[ARM_PLL_CTRL] = 0x0001A008; 197 s->regs[DDR_PLL_CTRL] = 0x0001A008; 198 s->regs[IO_PLL_CTRL] = 0x0001A008; 199 s->regs[PLL_STATUS] = 0x0000003F; 200 s->regs[ARM_PLL_CFG] = 0x00014000; 201 s->regs[DDR_PLL_CFG] = 0x00014000; 202 s->regs[IO_PLL_CFG] = 0x00014000; 203 204 /* 0x120 - 0x16C */ 205 s->regs[ARM_CLK_CTRL] = 0x1F000400; 206 s->regs[DDR_CLK_CTRL] = 0x18400003; 207 s->regs[DCI_CLK_CTRL] = 0x01E03201; 208 s->regs[APER_CLK_CTRL] = 0x01FFCCCD; 209 s->regs[USB0_CLK_CTRL] = s->regs[USB1_CLK_CTRL] = 0x00101941; 210 s->regs[GEM0_RCLK_CTRL] = s->regs[GEM1_RCLK_CTRL] = 0x00000001; 211 s->regs[GEM0_CLK_CTRL] = s->regs[GEM1_CLK_CTRL] = 0x00003C01; 212 s->regs[SMC_CLK_CTRL] = 0x00003C01; 213 s->regs[LQSPI_CLK_CTRL] = 0x00002821; 214 s->regs[SDIO_CLK_CTRL] = 0x00001E03; 215 s->regs[UART_CLK_CTRL] = 0x00003F03; 216 s->regs[SPI_CLK_CTRL] = 0x00003F03; 217 s->regs[CAN_CLK_CTRL] = 0x00501903; 218 s->regs[DBG_CLK_CTRL] = 0x00000F03; 219 s->regs[PCAP_CLK_CTRL] = 0x00000F01; 220 221 /* 0x170 - 0x1AC */ 222 s->regs[FPGA0_CLK_CTRL] = s->regs[FPGA1_CLK_CTRL] = s->regs[FPGA2_CLK_CTRL] 223 = s->regs[FPGA3_CLK_CTRL] = 0x00101800; 224 s->regs[FPGA0_THR_STA] = s->regs[FPGA1_THR_STA] = s->regs[FPGA2_THR_STA] 225 = s->regs[FPGA3_THR_STA] = 0x00010000; 226 227 /* 0x1B0 - 0x1D8 */ 228 s->regs[BANDGAP_TRIP] = 0x0000001F; 229 s->regs[PLL_PREDIVISOR] = 0x00000001; 230 s->regs[CLK_621_TRUE] = 0x00000001; 231 232 /* 0x200 - 0x25C */ 233 s->regs[FPGA_RST_CTRL] = 0x01F33F0F; 234 s->regs[RST_REASON] = 0x00000040; 235 236 s->regs[BOOT_MODE] = 0x00000001; 237 238 /* 0x700 - 0x7D4 */ 239 for (i = 0; i < 54; i++) { 240 s->regs[MIO + i] = 0x00001601; 241 } 242 for (i = 2; i <= 8; i++) { 243 s->regs[MIO + i] = 0x00000601; 244 } 245 246 s->regs[MIO_MST_TRI0] = s->regs[MIO_MST_TRI1] = 0xFFFFFFFF; 247 248 s->regs[CPU_RAM + 0] = s->regs[CPU_RAM + 1] = s->regs[CPU_RAM + 3] 249 = s->regs[CPU_RAM + 4] = s->regs[CPU_RAM + 7] 250 = 0x00010101; 251 s->regs[CPU_RAM + 2] = s->regs[CPU_RAM + 5] = 0x01010101; 252 s->regs[CPU_RAM + 6] = 0x00000001; 253 254 s->regs[IOU + 0] = s->regs[IOU + 1] = s->regs[IOU + 2] = s->regs[IOU + 3] 255 = 0x09090909; 256 s->regs[IOU + 4] = s->regs[IOU + 5] = 0x00090909; 257 s->regs[IOU + 6] = 0x00000909; 258 259 s->regs[DMAC_RAM] = 0x00000009; 260 261 s->regs[AFI0 + 0] = s->regs[AFI0 + 1] = 0x09090909; 262 s->regs[AFI1 + 0] = s->regs[AFI1 + 1] = 0x09090909; 263 s->regs[AFI2 + 0] = s->regs[AFI2 + 1] = 0x09090909; 264 s->regs[AFI3 + 0] = s->regs[AFI3 + 1] = 0x09090909; 265 s->regs[AFI0 + 2] = s->regs[AFI1 + 2] = s->regs[AFI2 + 2] 266 = s->regs[AFI3 + 2] = 0x00000909; 267 268 s->regs[OCM + 0] = 0x01010101; 269 s->regs[OCM + 1] = s->regs[OCM + 2] = 0x09090909; 270 271 s->regs[DEVCI_RAM] = 0x00000909; 272 s->regs[CSG_RAM] = 0x00000001; 273 274 s->regs[DDRIOB + 0] = s->regs[DDRIOB + 1] = s->regs[DDRIOB + 2] 275 = s->regs[DDRIOB + 3] = 0x00000e00; 276 s->regs[DDRIOB + 4] = s->regs[DDRIOB + 5] = s->regs[DDRIOB + 6] 277 = 0x00000e00; 278 s->regs[DDRIOB + 12] = 0x00000021; 279 } 280 281 282 static bool zynq_slcr_check_offset(hwaddr offset, bool rnw) 283 { 284 switch (offset) { 285 case LOCK: 286 case UNLOCK: 287 case DDR_CAL_START: 288 case DDR_REF_START: 289 return !rnw; /* Write only */ 290 case LOCKSTA: 291 case FPGA0_THR_STA: 292 case FPGA1_THR_STA: 293 case FPGA2_THR_STA: 294 case FPGA3_THR_STA: 295 case BOOT_MODE: 296 case PSS_IDCODE: 297 case DDR_CMD_STA: 298 case DDR_DFI_STATUS: 299 case PLL_STATUS: 300 return rnw;/* read only */ 301 case SCL: 302 case ARM_PLL_CTRL ... IO_PLL_CTRL: 303 case ARM_PLL_CFG ... IO_PLL_CFG: 304 case ARM_CLK_CTRL ... TOPSW_CLK_CTRL: 305 case FPGA0_CLK_CTRL ... FPGA0_THR_CNT: 306 case FPGA1_CLK_CTRL ... FPGA1_THR_CNT: 307 case FPGA2_CLK_CTRL ... FPGA2_THR_CNT: 308 case FPGA3_CLK_CTRL ... FPGA3_THR_CNT: 309 case BANDGAP_TRIP: 310 case PLL_PREDIVISOR: 311 case CLK_621_TRUE: 312 case PSS_RST_CTRL ... A9_CPU_RST_CTRL: 313 case RS_AWDT_CTRL: 314 case RST_REASON: 315 case REBOOT_STATUS: 316 case APU_CTRL: 317 case WDT_CLK_SEL: 318 case TZ_DMA_NS ... TZ_DMA_PERIPH_NS: 319 case DDR_URGENT: 320 case DDR_URGENT_SEL: 321 case MIO ... MIO + MIO_LENGTH - 1: 322 case MIO_LOOPBACK ... MIO_MST_TRI1: 323 case SD0_WP_CD_SEL: 324 case SD1_WP_CD_SEL: 325 case LVL_SHFTR_EN: 326 case OCM_CFG: 327 case CPU_RAM: 328 case IOU: 329 case DMAC_RAM: 330 case AFI0 ... AFI3 + AFI_LENGTH - 1: 331 case OCM: 332 case DEVCI_RAM: 333 case CSG_RAM: 334 case GPIOB_CTRL ... GPIOB_CFG_CMOS33: 335 case GPIOB_CFG_HSTL: 336 case GPIOB_DRVR_BIAS_CTRL: 337 case DDRIOB ... DDRIOB + DDRIOB_LENGTH - 1: 338 return true; 339 default: 340 return false; 341 } 342 } 343 344 static uint64_t zynq_slcr_read(void *opaque, hwaddr offset, 345 unsigned size) 346 { 347 ZynqSLCRState *s = opaque; 348 offset /= 4; 349 uint32_t ret = s->regs[offset]; 350 351 if (!zynq_slcr_check_offset(offset, true)) { 352 qemu_log_mask(LOG_GUEST_ERROR, "zynq_slcr: Invalid read access to " 353 " addr %" HWADDR_PRIx "\n", offset * 4); 354 } 355 356 DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx32 "\n", offset * 4, ret); 357 return ret; 358 } 359 360 static void zynq_slcr_write(void *opaque, hwaddr offset, 361 uint64_t val, unsigned size) 362 { 363 ZynqSLCRState *s = (ZynqSLCRState *)opaque; 364 offset /= 4; 365 366 DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx64 "\n", offset * 4, val); 367 368 if (!zynq_slcr_check_offset(offset, false)) { 369 qemu_log_mask(LOG_GUEST_ERROR, "zynq_slcr: Invalid write access to " 370 "addr %" HWADDR_PRIx "\n", offset * 4); 371 return; 372 } 373 374 switch (offset) { 375 case SCL: 376 s->regs[SCL] = val & 0x1; 377 return; 378 case LOCK: 379 if ((val & 0xFFFF) == XILINX_LOCK_KEY) { 380 DB_PRINT("XILINX LOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset, 381 (unsigned)val & 0xFFFF); 382 s->regs[LOCKSTA] = 1; 383 } else { 384 DB_PRINT("WRONG XILINX LOCK KEY 0xF8000000 + 0x%x <= 0x%x\n", 385 (int)offset, (unsigned)val & 0xFFFF); 386 } 387 return; 388 case UNLOCK: 389 if ((val & 0xFFFF) == XILINX_UNLOCK_KEY) { 390 DB_PRINT("XILINX UNLOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset, 391 (unsigned)val & 0xFFFF); 392 s->regs[LOCKSTA] = 0; 393 } else { 394 DB_PRINT("WRONG XILINX UNLOCK KEY 0xF8000000 + 0x%x <= 0x%x\n", 395 (int)offset, (unsigned)val & 0xFFFF); 396 } 397 return; 398 } 399 400 if (s->regs[LOCKSTA]) { 401 qemu_log_mask(LOG_GUEST_ERROR, 402 "SCLR registers are locked. Unlock them first\n"); 403 return; 404 } 405 s->regs[offset] = val; 406 407 switch (offset) { 408 case PSS_RST_CTRL: 409 if (val & R_PSS_RST_CTRL_SOFT_RST) { 410 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 411 } 412 break; 413 } 414 } 415 416 static const MemoryRegionOps slcr_ops = { 417 .read = zynq_slcr_read, 418 .write = zynq_slcr_write, 419 .endianness = DEVICE_NATIVE_ENDIAN, 420 }; 421 422 static void zynq_slcr_init(Object *obj) 423 { 424 ZynqSLCRState *s = ZYNQ_SLCR(obj); 425 426 memory_region_init_io(&s->iomem, obj, &slcr_ops, s, "slcr", 427 ZYNQ_SLCR_MMIO_SIZE); 428 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); 429 } 430 431 static const VMStateDescription vmstate_zynq_slcr = { 432 .name = "zynq_slcr", 433 .version_id = 2, 434 .minimum_version_id = 2, 435 .fields = (VMStateField[]) { 436 VMSTATE_UINT32_ARRAY(regs, ZynqSLCRState, ZYNQ_SLCR_NUM_REGS), 437 VMSTATE_END_OF_LIST() 438 } 439 }; 440 441 static void zynq_slcr_class_init(ObjectClass *klass, void *data) 442 { 443 DeviceClass *dc = DEVICE_CLASS(klass); 444 445 dc->vmsd = &vmstate_zynq_slcr; 446 dc->reset = zynq_slcr_reset; 447 } 448 449 static const TypeInfo zynq_slcr_info = { 450 .class_init = zynq_slcr_class_init, 451 .name = TYPE_ZYNQ_SLCR, 452 .parent = TYPE_SYS_BUS_DEVICE, 453 .instance_size = sizeof(ZynqSLCRState), 454 .instance_init = zynq_slcr_init, 455 }; 456 457 static void zynq_slcr_register_types(void) 458 { 459 type_register_static(&zynq_slcr_info); 460 } 461 462 type_init(zynq_slcr_register_types) 463