xref: /openbmc/qemu/include/hw/i2c/aspeed_i2c.h (revision 6054fc73e8f4acaafa63b4616e39414e53bce9a9)
1 /*
2  *  ASPEED AST2400 I2C Controller
3  *
4  *  Copyright (C) 2016 IBM Corp.
5  *
6  *  This program is free software; you can redistribute it and/or modify
7  *  it under the terms of the GNU General Public License as published by
8  *  the Free Software Foundation; either version 2 of the License, or
9  *  (at your option) any later version.
10  *
11  *  This program is distributed in the hope that it will be useful,
12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  *  GNU General Public License for more details.
15  *
16  *  You should have received a copy of the GNU General Public License along
17  *  with this program; if not, write to the Free Software Foundation, Inc.,
18  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19  */
20 
21 #ifndef ASPEED_I2C_H
22 #define ASPEED_I2C_H
23 
24 #include "hw/i2c/i2c.h"
25 #include "hw/sysbus.h"
26 
27 #define TYPE_ASPEED_I2C "aspeed.i2c"
28 #define TYPE_ASPEED_2400_I2C TYPE_ASPEED_I2C "-ast2400"
29 #define TYPE_ASPEED_2500_I2C TYPE_ASPEED_I2C "-ast2500"
30 #define TYPE_ASPEED_2600_I2C TYPE_ASPEED_I2C "-ast2600"
31 #define ASPEED_I2C(obj) \
32     OBJECT_CHECK(AspeedI2CState, (obj), TYPE_ASPEED_I2C)
33 
34 #define ASPEED_I2C_NR_BUSSES 16
35 #define ASPEED_I2C_MAX_POOL_SIZE 0x800
36 
37 struct AspeedI2CState;
38 
39 typedef struct AspeedI2CBus {
40     struct AspeedI2CState *controller;
41 
42     MemoryRegion mr;
43 
44     I2CBus *bus;
45     uint8_t id;
46     qemu_irq irq;
47 
48     uint32_t ctrl;
49     uint32_t timing[2];
50     uint32_t intr_ctrl;
51     uint32_t intr_status;
52     uint32_t cmd;
53     uint32_t buf;
54     uint32_t pool_ctrl;
55 } AspeedI2CBus;
56 
57 typedef struct AspeedI2CState {
58     SysBusDevice parent_obj;
59 
60     MemoryRegion iomem;
61     qemu_irq irq;
62 
63     uint32_t intr_status;
64     MemoryRegion pool_iomem;
65     uint8_t pool[ASPEED_I2C_MAX_POOL_SIZE];
66 
67     AspeedI2CBus busses[ASPEED_I2C_NR_BUSSES];
68 } AspeedI2CState;
69 
70 #define ASPEED_I2C_CLASS(klass) \
71      OBJECT_CLASS_CHECK(AspeedI2CClass, (klass), TYPE_ASPEED_I2C)
72 #define ASPEED_I2C_GET_CLASS(obj) \
73      OBJECT_GET_CLASS(AspeedI2CClass, (obj), TYPE_ASPEED_I2C)
74 
75 typedef struct AspeedI2CClass {
76     SysBusDeviceClass parent_class;
77 
78     uint8_t num_busses;
79     uint8_t reg_size;
80     uint8_t gap;
81     qemu_irq (*bus_get_irq)(AspeedI2CBus *);
82 
83     uint64_t pool_size;
84     hwaddr pool_base;
85     uint8_t *(*bus_pool_base)(AspeedI2CBus *);
86 } AspeedI2CClass;
87 
88 I2CBus *aspeed_i2c_get_bus(DeviceState *dev, int busnr);
89 
90 #endif /* ASPEED_I2C_H */
91