1 /* 2 * QEMU SMBus EEPROM device 3 * 4 * Copyright (c) 2007 Arastra, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "hw/hw.h" 29 #include "hw/i2c/i2c.h" 30 #include "hw/i2c/smbus_slave.h" 31 #include "hw/i2c/smbus_eeprom.h" 32 33 //#define DEBUG 34 35 typedef struct SMBusEEPROMDevice { 36 SMBusDevice smbusdev; 37 void *data; 38 uint8_t offset; 39 } SMBusEEPROMDevice; 40 41 static void eeprom_quick_cmd(SMBusDevice *dev, uint8_t read) 42 { 43 #ifdef DEBUG 44 printf("eeprom_quick_cmd: addr=0x%02x read=%d\n", dev->i2c.address, read); 45 #endif 46 } 47 48 static uint8_t eeprom_receive_byte(SMBusDevice *dev) 49 { 50 SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev; 51 uint8_t *data = eeprom->data; 52 uint8_t val = data[eeprom->offset++]; 53 #ifdef DEBUG 54 printf("eeprom_receive_byte: addr=0x%02x val=0x%02x\n", 55 dev->i2c.address, val); 56 #endif 57 return val; 58 } 59 60 static int eeprom_write_data(SMBusDevice *dev, uint8_t *buf, uint8_t len) 61 { 62 SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev; 63 uint8_t *data = eeprom->data; 64 65 #ifdef DEBUG 66 printf("eeprom_write_byte: addr=0x%02x cmd=0x%02x val=0x%02x\n", 67 dev->i2c.address, buf[0], buf[1]); 68 #endif 69 /* len is guaranteed to be > 0 */ 70 eeprom->offset = buf[0]; 71 buf++; 72 len--; 73 74 for (; len > 0; len--) { 75 data[eeprom->offset] = *buf++; 76 eeprom->offset = (eeprom->offset + 1) % 256; 77 } 78 79 return 0; 80 } 81 82 static uint8_t eeprom_read_data(SMBusDevice *dev, int n) 83 { 84 /* As with writes, we implement block reads without the 85 SMBus length byte. */ 86 return eeprom_receive_byte(dev); 87 } 88 89 static void smbus_eeprom_realize(DeviceState *dev, Error **errp) 90 { 91 SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *)dev; 92 93 eeprom->offset = 0; 94 } 95 96 static Property smbus_eeprom_properties[] = { 97 DEFINE_PROP_PTR("data", SMBusEEPROMDevice, data), 98 DEFINE_PROP_END_OF_LIST(), 99 }; 100 101 static void smbus_eeprom_class_initfn(ObjectClass *klass, void *data) 102 { 103 DeviceClass *dc = DEVICE_CLASS(klass); 104 SMBusDeviceClass *sc = SMBUS_DEVICE_CLASS(klass); 105 106 dc->realize = smbus_eeprom_realize; 107 sc->quick_cmd = eeprom_quick_cmd; 108 sc->receive_byte = eeprom_receive_byte; 109 sc->write_data = eeprom_write_data; 110 sc->read_data = eeprom_read_data; 111 dc->props = smbus_eeprom_properties; 112 /* Reason: pointer property "data" */ 113 dc->user_creatable = false; 114 } 115 116 static const TypeInfo smbus_eeprom_info = { 117 .name = "smbus-eeprom", 118 .parent = TYPE_SMBUS_DEVICE, 119 .instance_size = sizeof(SMBusEEPROMDevice), 120 .class_init = smbus_eeprom_class_initfn, 121 }; 122 123 static void smbus_eeprom_register_types(void) 124 { 125 type_register_static(&smbus_eeprom_info); 126 } 127 128 type_init(smbus_eeprom_register_types) 129 130 void smbus_eeprom_init_one(I2CBus *smbus, uint8_t address, uint8_t *eeprom_buf) 131 { 132 DeviceState *dev; 133 134 dev = qdev_create((BusState *) smbus, "smbus-eeprom"); 135 qdev_prop_set_uint8(dev, "address", address); 136 qdev_prop_set_ptr(dev, "data", eeprom_buf); 137 qdev_init_nofail(dev); 138 } 139 140 void smbus_eeprom_init(I2CBus *smbus, int nb_eeprom, 141 const uint8_t *eeprom_spd, int eeprom_spd_size) 142 { 143 int i; 144 uint8_t *eeprom_buf = g_malloc0(8 * 256); /* XXX: make this persistent */ 145 if (eeprom_spd_size > 0) { 146 memcpy(eeprom_buf, eeprom_spd, eeprom_spd_size); 147 } 148 149 for (i = 0; i < nb_eeprom; i++) { 150 smbus_eeprom_init_one(smbus, 0x50 + i, eeprom_buf + (i * 256)); 151 } 152 } 153 154 /* Generate SDRAM SPD EEPROM data describing a module of type and size */ 155 uint8_t *spd_data_generate(enum sdram_type type, ram_addr_t ram_size, 156 Error **errp) 157 { 158 uint8_t *spd; 159 uint8_t nbanks; 160 uint16_t density; 161 uint32_t size; 162 int min_log2, max_log2, sz_log2; 163 int i; 164 165 switch (type) { 166 case SDR: 167 min_log2 = 2; 168 max_log2 = 9; 169 break; 170 case DDR: 171 min_log2 = 5; 172 max_log2 = 12; 173 break; 174 case DDR2: 175 min_log2 = 7; 176 max_log2 = 14; 177 break; 178 default: 179 g_assert_not_reached(); 180 } 181 size = ram_size >> 20; /* work in terms of megabytes */ 182 if (size < 4) { 183 error_setg(errp, "SDRAM size is too small"); 184 return NULL; 185 } 186 sz_log2 = 31 - clz32(size); 187 size = 1U << sz_log2; 188 if (ram_size > size * MiB) { 189 error_setg(errp, "SDRAM size 0x"RAM_ADDR_FMT" is not a power of 2, " 190 "truncating to %u MB", ram_size, size); 191 } 192 if (sz_log2 < min_log2) { 193 error_setg(errp, 194 "Memory size is too small for SDRAM type, adjusting type"); 195 if (size >= 32) { 196 type = DDR; 197 min_log2 = 5; 198 max_log2 = 12; 199 } else { 200 type = SDR; 201 min_log2 = 2; 202 max_log2 = 9; 203 } 204 } 205 206 nbanks = 1; 207 while (sz_log2 > max_log2 && nbanks < 8) { 208 sz_log2--; 209 nbanks++; 210 } 211 212 if (size > (1ULL << sz_log2) * nbanks) { 213 error_setg(errp, "Memory size is too big for SDRAM, truncating"); 214 } 215 216 /* split to 2 banks if possible to avoid a bug in MIPS Malta firmware */ 217 if (nbanks == 1 && sz_log2 > min_log2) { 218 sz_log2--; 219 nbanks++; 220 } 221 222 density = 1ULL << (sz_log2 - 2); 223 switch (type) { 224 case DDR2: 225 density = (density & 0xe0) | (density >> 8 & 0x1f); 226 break; 227 case DDR: 228 density = (density & 0xf8) | (density >> 8 & 0x07); 229 break; 230 case SDR: 231 default: 232 density &= 0xff; 233 break; 234 } 235 236 spd = g_malloc0(256); 237 spd[0] = 128; /* data bytes in EEPROM */ 238 spd[1] = 8; /* log2 size of EEPROM */ 239 spd[2] = type; 240 spd[3] = 13; /* row address bits */ 241 spd[4] = 10; /* column address bits */ 242 spd[5] = (type == DDR2 ? nbanks - 1 : nbanks); 243 spd[6] = 64; /* module data width */ 244 /* reserved / data width high */ 245 spd[8] = 4; /* interface voltage level */ 246 spd[9] = 0x25; /* highest CAS latency */ 247 spd[10] = 1; /* access time */ 248 /* DIMM configuration 0 = non-ECC */ 249 spd[12] = 0x82; /* refresh requirements */ 250 spd[13] = 8; /* primary SDRAM width */ 251 /* ECC SDRAM width */ 252 spd[15] = (type == DDR2 ? 0 : 1); /* reserved / delay for random col rd */ 253 spd[16] = 12; /* burst lengths supported */ 254 spd[17] = 4; /* banks per SDRAM device */ 255 spd[18] = 12; /* ~CAS latencies supported */ 256 spd[19] = (type == DDR2 ? 0 : 1); /* reserved / ~CS latencies supported */ 257 spd[20] = 2; /* DIMM type / ~WE latencies */ 258 /* module features */ 259 /* memory chip features */ 260 spd[23] = 0x12; /* clock cycle time @ medium CAS latency */ 261 /* data access time */ 262 /* clock cycle time @ short CAS latency */ 263 /* data access time */ 264 spd[27] = 20; /* min. row precharge time */ 265 spd[28] = 15; /* min. row active row delay */ 266 spd[29] = 20; /* min. ~RAS to ~CAS delay */ 267 spd[30] = 45; /* min. active to precharge time */ 268 spd[31] = density; 269 spd[32] = 20; /* addr/cmd setup time */ 270 spd[33] = 8; /* addr/cmd hold time */ 271 spd[34] = 20; /* data input setup time */ 272 spd[35] = 8; /* data input hold time */ 273 274 /* checksum */ 275 for (i = 0; i < 63; i++) { 276 spd[63] += spd[i]; 277 } 278 return spd; 279 } 280