3dbab141 | 03-Sep-2024 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw/i2c/aspeed: Add support for Tx/Rx buffer 64 bit addresses
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) and the base address of dram is "0x4 00000000" which is 64bits address.
It h
hw/i2c/aspeed: Add support for Tx/Rx buffer 64 bit addresses
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) and the base address of dram is "0x4 00000000" which is 64bits address.
It has "Master DMA Mode Tx Buffer Base Address[39:32](0x60)" and "Master DMA Mode Rx Buffer Base Address[39:32](0x64)" registers to save the high part physical address of Tx/Rx buffer address for master mode.
It has "Slave DMA Mode Tx Buffer Base Address[39:32](0x68)" and "Slave DMA Mode Rx Buffer Base Address[39:32](0x6C)" registers to save the high part physical address of Tx/Rx buffer address for slave mode.
Ex: Tx buffer address for master mode [39:0] The "Master DMA Mode Tx Buffer Base Address[39:32](0x60)" bits [7:0] which corresponds the bits [39:32] of the 64 bits address of the Tx buffer address. The "Master DMA Mode Tx Buffer Base Address(0x30)" bits [31:0] which corresponds the bits [31:0] of the 64 bits address of the Tx buffer address.
Introduce a new has_dma64 class attribute and new registers for the new mode to support DMA 64 bits dram address. Update new mode register number to 28.
The aspeed_i2c_bus_vmstate is changed again and version is not increased because it was done earlier in the same series.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
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1809ab6a | 03-Sep-2024 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw/i2c/aspeed: Add AST2700 support
Introduce a new ast2700 class to support AST2700. The I2C bus register memory regions and I2C bus pool buffer memory regions are discontinuous and they do not back
hw/i2c/aspeed: Add AST2700 support
Introduce a new ast2700 class to support AST2700. The I2C bus register memory regions and I2C bus pool buffer memory regions are discontinuous and they do not back compatible AST2600.
Add a new ast2700 i2c class init function to match the address of I2C bus register and pool buffer from the datasheet.
An I2C controller registers owns 8KB address space.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
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c400c388 | 03-Sep-2024 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw/i2c/aspeed: Introduce a new dma_dram_offset attribute in AspeedI2Cbus
The "Current DMA Operating Address Status(0x50)" register of I2C new mode has been removed in AST2700. This register is used
hw/i2c/aspeed: Introduce a new dma_dram_offset attribute in AspeedI2Cbus
The "Current DMA Operating Address Status(0x50)" register of I2C new mode has been removed in AST2700. This register is used for debugging and it is a read only register.
To support AST2700 DMA mode, introduce a new dma_dram_offset class attribute in AspeedI2Cbus to save the current DMA operating address.
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) And the base address of dram is "0x4 00000000" which is 64bits address.
Set the dma_dram_offset data type to uint64_t for 64 bits dram address DMA support.
Both "DMA Mode Buffer Address Register(I2CD24 old mode)" and "DMA Operating Address Status (I2CC50 new mode)" are used for showing the low part dram offset bits [31:0], so change to read/write both register bits [31:0] in bus register read/write functions.
The aspeed_i2c_bus_vmstate is changed again and version is not increased because it was done earlier in the same series.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
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d46a4ba0 | 03-Sep-2024 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw/i2c/aspeed: Support discontinuous poll buffer memory region of I2C bus
It only support continuous pool buffer memory region for all I2C bus. However, the pool buffer address of all I2c bus are di
hw/i2c/aspeed: Support discontinuous poll buffer memory region of I2C bus
It only support continuous pool buffer memory region for all I2C bus. However, the pool buffer address of all I2c bus are discontinuous for AST2700.
Ex: the pool buffer address of I2C bus for ast2700 as following. 0x1A0 - 0x1BF: Device 0 buffer 0x2A0 - 0x2BF: Device 1 buffer 0x3A0 - 0x3BF: Device 2 buffer 0x4A0 - 0x4BF: Device 3 buffer 0x5A0 - 0x5BF: Device 4 buffer 0x6A0 - 0x6BF: Device 5 buffer 0x7A0 - 0x7BF: Device 6 buffer 0x8A0 - 0x8BF: Device 7 buffer 0x9A0 - 0x9BF: Device 8 buffer 0xAA0 - 0xABF: Device 9 buffer 0xBA0 - 0xBBF: Device 10 buffer 0xCA0 - 0xCBF: Device 11 buffer 0xDA0 - 0xDBF: Device 12 buffer 0xEA0 - 0xEBF: Device 13 buffer 0xFA0 – 0xFBF: Device 14 buffer 0x10A0 – 0x10BF: Device 15 buffer
Introduce a new class attribute to make user set each I2C bus pool buffer gap size. Update formula to create all I2C bus pool buffer memory regions.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
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62c0c65d | 03-Sep-2024 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw/i2c/aspeed: Introduce a new bus pool buffer attribute in AspeedI2Cbus
According to the datasheet of ASPEED SOCs, each I2C bus has their own pool buffer since AST2500. Only AST2400 utilized a pool
hw/i2c/aspeed: Introduce a new bus pool buffer attribute in AspeedI2Cbus
According to the datasheet of ASPEED SOCs, each I2C bus has their own pool buffer since AST2500. Only AST2400 utilized a pool buffer share to all I2C bus. Besides, using a share pool buffer only support pool buffer memory regions are continuous for all I2C bus.
To make this model more readable and support discontinuous bus pool buffer memory regions, changes to introduce a new bus pool buffer attribute in AspeedI2Cbus and new memops. So, it does not need to calculate the pool buffer offset for different I2C bus.
Introduce a new has_share_pool class attribute in AspeedI2CClass and use it to create either a share pool buffer or bus pool buffers in aspeed_i2c_realize. Update each pull buffer size to 0x10 for AST2500 and 0x20 for AST2600 and AST1030.
Incrementing the version of aspeed_i2c_bus_vmstate to 6.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
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5d337540 | 18-Jul-2024 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw/i2c/aspeed: rename the I2C class pool attribute to share_pool
According to the datasheet of ASPEED SOCs, each I2C bus has their own pool buffer since AST2500.
Only AST2400 utilized a pool buffer
hw/i2c/aspeed: rename the I2C class pool attribute to share_pool
According to the datasheet of ASPEED SOCs, each I2C bus has their own pool buffer since AST2500.
Only AST2400 utilized a pool buffer share to all I2C bus. And firmware required to set the offset of pool buffer by writing "Function Control Register(I2CD 00)"
To make this model more readable, will change to introduce a new bus pool buffer attribute in AspeedI2Cbus. So, it does not need to calculate the pool buffer offset for different I2C bus.
This patch rename the I2C class pool attribute to share_pool. It make user more understand share pool and bus pool are different.
Incrementing the version of aspeed_i2c_vmstate to 3.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
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3401b1dd | 23-Oct-2023 |
Titus Rwantare <titusr@google.com> |
hw/i2c: pmbus: add VCAP register
VCAP is a register for devices with energy storage capacitors.
Reviewed-by: Benjamin Streb <bstreb@google.com> Acked-by: Corey Minyard <cminyard@mvista.com> Signed-
hw/i2c: pmbus: add VCAP register
VCAP is a register for devices with energy storage capacitors.
Reviewed-by: Benjamin Streb <bstreb@google.com> Acked-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Titus Rwantare <titusr@google.com> Message-ID: <20231023-staging-pmbus-v3-v4-4-07a8cb7cd20a@google.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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b7fba25e | 23-Oct-2023 |
Titus Rwantare <titusr@google.com> |
hw/i2c: pmbus: add fan support
PMBus devices may integrate fans whose operation is configurable over PMBus. This commit allows the driver to read and write the fan control registers but does not mod
hw/i2c: pmbus: add fan support
PMBus devices may integrate fans whose operation is configurable over PMBus. This commit allows the driver to read and write the fan control registers but does not model the operation of fans.
Reviewed-by: Stephen Longfield <slongfield@google.com> Acked-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Titus Rwantare <titusr@google.com> Message-ID: <20231023-staging-pmbus-v3-v4-3-07a8cb7cd20a@google.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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144729b9 | 23-Oct-2023 |
Titus Rwantare <titusr@google.com> |
hw/i2c: pmbus: add vout mode bitfields
The VOUT_MODE command is described in the PMBus Specification, Part II, Ver 1.3 Section 8.3
VOUT_MODE has a three bit mode and 4 bit parameter, the three bit
hw/i2c: pmbus: add vout mode bitfields
The VOUT_MODE command is described in the PMBus Specification, Part II, Ver 1.3 Section 8.3
VOUT_MODE has a three bit mode and 4 bit parameter, the three bit mode determines whether voltages are formatted as uint16, uint16, VID, and Direct modes. VID and Direct modes use the remaining 5 bits to scale the voltage readings.
Reviewed-by: Hao Wu <wuhaotsh@google.com> Acked-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Titus Rwantare <titusr@google.com> Message-ID: <20231023-staging-pmbus-v3-v4-2-07a8cb7cd20a@google.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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acc3d20a | 12-Aug-2023 |
Hang Yu <francis_yuu@stu.pku.edu.cn> |
hw/i2c/aspeed: Add support for buffer organization
Added support for the buffer organization option in pool buffer control register.when set to 1,The buffer is split into two parts: Lower 16 bytes f
hw/i2c/aspeed: Add support for buffer organization
Added support for the buffer organization option in pool buffer control register.when set to 1,The buffer is split into two parts: Lower 16 bytes for Tx and higher 16 bytes for Rx.
Signed-off-by: Hang Yu <francis_yuu@stu.pku.edu.cn> Reviewed-by: Cédric Le Goater <clg@kaod.org> [ clg: checkpatch fixes ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
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92518611 | 10-Jan-2023 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
hw/i2c/versatile_i2c: Replace VersatileI2CState -> ArmSbconI2CState
In order to rename TYPE_VERSATILE_I2C as TYPE_ARM_SBCON_I2C (the formal ARM naming), start renaming its state.
Signed-off-by: Phi
hw/i2c/versatile_i2c: Replace VersatileI2CState -> ArmSbconI2CState
In order to rename TYPE_VERSATILE_I2C as TYPE_ARM_SBCON_I2C (the formal ARM naming), start renaming its state.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230110082508.24038-3-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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