1 /* 2 * PowerMac descriptor-based DMA emulation 3 * 4 * Copyright (c) 2005-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2009 Laurent Vivier 7 * 8 * some parts from linux-2.6.28, arch/powerpc/include/asm/dbdma.h 9 * 10 * Definitions for using the Apple Descriptor-Based DMA controller 11 * in Power Macintosh computers. 12 * 13 * Copyright (C) 1996 Paul Mackerras. 14 * 15 * some parts from mol 0.9.71 16 * 17 * Descriptor based DMA emulation 18 * 19 * Copyright (C) 1998-2004 Samuel Rydh (samuel@ibrium.se) 20 * 21 * Permission is hereby granted, free of charge, to any person obtaining a copy 22 * of this software and associated documentation files (the "Software"), to deal 23 * in the Software without restriction, including without limitation the rights 24 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 25 * copies of the Software, and to permit persons to whom the Software is 26 * furnished to do so, subject to the following conditions: 27 * 28 * The above copyright notice and this permission notice shall be included in 29 * all copies or substantial portions of the Software. 30 * 31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 32 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 33 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 34 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 35 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 36 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 37 * THE SOFTWARE. 38 */ 39 40 #include "qemu/osdep.h" 41 #include "hw/hw.h" 42 #include "hw/irq.h" 43 #include "hw/ppc/mac_dbdma.h" 44 #include "migration/vmstate.h" 45 #include "qemu/main-loop.h" 46 #include "qemu/module.h" 47 #include "qemu/log.h" 48 #include "sysemu/dma.h" 49 50 /* debug DBDMA */ 51 #define DEBUG_DBDMA 0 52 #define DEBUG_DBDMA_CHANMASK ((1ull << DBDMA_CHANNELS) - 1) 53 54 #define DBDMA_DPRINTF(fmt, ...) do { \ 55 if (DEBUG_DBDMA) { \ 56 printf("DBDMA: " fmt , ## __VA_ARGS__); \ 57 } \ 58 } while (0) 59 60 #define DBDMA_DPRINTFCH(ch, fmt, ...) do { \ 61 if (DEBUG_DBDMA) { \ 62 if ((1ul << (ch)->channel) & DEBUG_DBDMA_CHANMASK) { \ 63 printf("DBDMA[%02x]: " fmt , (ch)->channel, ## __VA_ARGS__); \ 64 } \ 65 } \ 66 } while (0) 67 68 /* 69 */ 70 71 static DBDMAState *dbdma_from_ch(DBDMA_channel *ch) 72 { 73 return container_of(ch, DBDMAState, channels[ch->channel]); 74 } 75 76 #if DEBUG_DBDMA 77 static void dump_dbdma_cmd(DBDMA_channel *ch, dbdma_cmd *cmd) 78 { 79 DBDMA_DPRINTFCH(ch, "dbdma_cmd %p\n", cmd); 80 DBDMA_DPRINTFCH(ch, " req_count 0x%04x\n", le16_to_cpu(cmd->req_count)); 81 DBDMA_DPRINTFCH(ch, " command 0x%04x\n", le16_to_cpu(cmd->command)); 82 DBDMA_DPRINTFCH(ch, " phy_addr 0x%08x\n", le32_to_cpu(cmd->phy_addr)); 83 DBDMA_DPRINTFCH(ch, " cmd_dep 0x%08x\n", le32_to_cpu(cmd->cmd_dep)); 84 DBDMA_DPRINTFCH(ch, " res_count 0x%04x\n", le16_to_cpu(cmd->res_count)); 85 DBDMA_DPRINTFCH(ch, " xfer_status 0x%04x\n", 86 le16_to_cpu(cmd->xfer_status)); 87 } 88 #else 89 static void dump_dbdma_cmd(DBDMA_channel *ch, dbdma_cmd *cmd) 90 { 91 } 92 #endif 93 static void dbdma_cmdptr_load(DBDMA_channel *ch) 94 { 95 DBDMA_DPRINTFCH(ch, "dbdma_cmdptr_load 0x%08x\n", 96 ch->regs[DBDMA_CMDPTR_LO]); 97 dma_memory_read(&address_space_memory, ch->regs[DBDMA_CMDPTR_LO], 98 &ch->current, sizeof(dbdma_cmd)); 99 } 100 101 static void dbdma_cmdptr_save(DBDMA_channel *ch) 102 { 103 DBDMA_DPRINTFCH(ch, "-> update 0x%08x stat=0x%08x, res=0x%04x\n", 104 ch->regs[DBDMA_CMDPTR_LO], 105 le16_to_cpu(ch->current.xfer_status), 106 le16_to_cpu(ch->current.res_count)); 107 dma_memory_write(&address_space_memory, ch->regs[DBDMA_CMDPTR_LO], 108 &ch->current, sizeof(dbdma_cmd)); 109 } 110 111 static void kill_channel(DBDMA_channel *ch) 112 { 113 DBDMA_DPRINTFCH(ch, "kill_channel\n"); 114 115 ch->regs[DBDMA_STATUS] |= DEAD; 116 ch->regs[DBDMA_STATUS] &= ~ACTIVE; 117 118 qemu_irq_raise(ch->irq); 119 } 120 121 static void conditional_interrupt(DBDMA_channel *ch) 122 { 123 dbdma_cmd *current = &ch->current; 124 uint16_t intr; 125 uint16_t sel_mask, sel_value; 126 uint32_t status; 127 int cond; 128 129 DBDMA_DPRINTFCH(ch, "%s\n", __func__); 130 131 intr = le16_to_cpu(current->command) & INTR_MASK; 132 133 switch(intr) { 134 case INTR_NEVER: /* don't interrupt */ 135 return; 136 case INTR_ALWAYS: /* always interrupt */ 137 qemu_irq_raise(ch->irq); 138 DBDMA_DPRINTFCH(ch, "%s: raise\n", __func__); 139 return; 140 } 141 142 status = ch->regs[DBDMA_STATUS] & DEVSTAT; 143 144 sel_mask = (ch->regs[DBDMA_INTR_SEL] >> 16) & 0x0f; 145 sel_value = ch->regs[DBDMA_INTR_SEL] & 0x0f; 146 147 cond = (status & sel_mask) == (sel_value & sel_mask); 148 149 switch(intr) { 150 case INTR_IFSET: /* intr if condition bit is 1 */ 151 if (cond) { 152 qemu_irq_raise(ch->irq); 153 DBDMA_DPRINTFCH(ch, "%s: raise\n", __func__); 154 } 155 return; 156 case INTR_IFCLR: /* intr if condition bit is 0 */ 157 if (!cond) { 158 qemu_irq_raise(ch->irq); 159 DBDMA_DPRINTFCH(ch, "%s: raise\n", __func__); 160 } 161 return; 162 } 163 } 164 165 static int conditional_wait(DBDMA_channel *ch) 166 { 167 dbdma_cmd *current = &ch->current; 168 uint16_t wait; 169 uint16_t sel_mask, sel_value; 170 uint32_t status; 171 int cond; 172 int res = 0; 173 174 wait = le16_to_cpu(current->command) & WAIT_MASK; 175 switch(wait) { 176 case WAIT_NEVER: /* don't wait */ 177 return 0; 178 case WAIT_ALWAYS: /* always wait */ 179 DBDMA_DPRINTFCH(ch, " [WAIT_ALWAYS]\n"); 180 return 1; 181 } 182 183 status = ch->regs[DBDMA_STATUS] & DEVSTAT; 184 185 sel_mask = (ch->regs[DBDMA_WAIT_SEL] >> 16) & 0x0f; 186 sel_value = ch->regs[DBDMA_WAIT_SEL] & 0x0f; 187 188 cond = (status & sel_mask) == (sel_value & sel_mask); 189 190 switch(wait) { 191 case WAIT_IFSET: /* wait if condition bit is 1 */ 192 if (cond) { 193 res = 1; 194 } 195 DBDMA_DPRINTFCH(ch, " [WAIT_IFSET=%d]\n", res); 196 break; 197 case WAIT_IFCLR: /* wait if condition bit is 0 */ 198 if (!cond) { 199 res = 1; 200 } 201 DBDMA_DPRINTFCH(ch, " [WAIT_IFCLR=%d]\n", res); 202 break; 203 } 204 return res; 205 } 206 207 static void next(DBDMA_channel *ch) 208 { 209 uint32_t cp; 210 211 ch->regs[DBDMA_STATUS] &= ~BT; 212 213 cp = ch->regs[DBDMA_CMDPTR_LO]; 214 ch->regs[DBDMA_CMDPTR_LO] = cp + sizeof(dbdma_cmd); 215 dbdma_cmdptr_load(ch); 216 } 217 218 static void branch(DBDMA_channel *ch) 219 { 220 dbdma_cmd *current = &ch->current; 221 222 ch->regs[DBDMA_CMDPTR_LO] = le32_to_cpu(current->cmd_dep); 223 ch->regs[DBDMA_STATUS] |= BT; 224 dbdma_cmdptr_load(ch); 225 } 226 227 static void conditional_branch(DBDMA_channel *ch) 228 { 229 dbdma_cmd *current = &ch->current; 230 uint16_t br; 231 uint16_t sel_mask, sel_value; 232 uint32_t status; 233 int cond; 234 235 /* check if we must branch */ 236 237 br = le16_to_cpu(current->command) & BR_MASK; 238 239 switch(br) { 240 case BR_NEVER: /* don't branch */ 241 next(ch); 242 return; 243 case BR_ALWAYS: /* always branch */ 244 DBDMA_DPRINTFCH(ch, " [BR_ALWAYS]\n"); 245 branch(ch); 246 return; 247 } 248 249 status = ch->regs[DBDMA_STATUS] & DEVSTAT; 250 251 sel_mask = (ch->regs[DBDMA_BRANCH_SEL] >> 16) & 0x0f; 252 sel_value = ch->regs[DBDMA_BRANCH_SEL] & 0x0f; 253 254 cond = (status & sel_mask) == (sel_value & sel_mask); 255 256 switch(br) { 257 case BR_IFSET: /* branch if condition bit is 1 */ 258 if (cond) { 259 DBDMA_DPRINTFCH(ch, " [BR_IFSET = 1]\n"); 260 branch(ch); 261 } else { 262 DBDMA_DPRINTFCH(ch, " [BR_IFSET = 0]\n"); 263 next(ch); 264 } 265 return; 266 case BR_IFCLR: /* branch if condition bit is 0 */ 267 if (!cond) { 268 DBDMA_DPRINTFCH(ch, " [BR_IFCLR = 1]\n"); 269 branch(ch); 270 } else { 271 DBDMA_DPRINTFCH(ch, " [BR_IFCLR = 0]\n"); 272 next(ch); 273 } 274 return; 275 } 276 } 277 278 static void channel_run(DBDMA_channel *ch); 279 280 static void dbdma_end(DBDMA_io *io) 281 { 282 DBDMA_channel *ch = io->channel; 283 dbdma_cmd *current = &ch->current; 284 285 DBDMA_DPRINTFCH(ch, "%s\n", __func__); 286 287 if (conditional_wait(ch)) 288 goto wait; 289 290 current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]); 291 current->res_count = cpu_to_le16(io->len); 292 dbdma_cmdptr_save(ch); 293 if (io->is_last) 294 ch->regs[DBDMA_STATUS] &= ~FLUSH; 295 296 conditional_interrupt(ch); 297 conditional_branch(ch); 298 299 wait: 300 /* Indicate that we're ready for a new DMA round */ 301 ch->io.processing = false; 302 303 if ((ch->regs[DBDMA_STATUS] & RUN) && 304 (ch->regs[DBDMA_STATUS] & ACTIVE)) 305 channel_run(ch); 306 } 307 308 static void start_output(DBDMA_channel *ch, int key, uint32_t addr, 309 uint16_t req_count, int is_last) 310 { 311 DBDMA_DPRINTFCH(ch, "start_output\n"); 312 313 /* KEY_REGS, KEY_DEVICE and KEY_STREAM 314 * are not implemented in the mac-io chip 315 */ 316 317 DBDMA_DPRINTFCH(ch, "addr 0x%x key 0x%x\n", addr, key); 318 if (!addr || key > KEY_STREAM3) { 319 kill_channel(ch); 320 return; 321 } 322 323 ch->io.addr = addr; 324 ch->io.len = req_count; 325 ch->io.is_last = is_last; 326 ch->io.dma_end = dbdma_end; 327 ch->io.is_dma_out = 1; 328 ch->io.processing = true; 329 if (ch->rw) { 330 ch->rw(&ch->io); 331 } 332 } 333 334 static void start_input(DBDMA_channel *ch, int key, uint32_t addr, 335 uint16_t req_count, int is_last) 336 { 337 DBDMA_DPRINTFCH(ch, "start_input\n"); 338 339 /* KEY_REGS, KEY_DEVICE and KEY_STREAM 340 * are not implemented in the mac-io chip 341 */ 342 343 DBDMA_DPRINTFCH(ch, "addr 0x%x key 0x%x\n", addr, key); 344 if (!addr || key > KEY_STREAM3) { 345 kill_channel(ch); 346 return; 347 } 348 349 ch->io.addr = addr; 350 ch->io.len = req_count; 351 ch->io.is_last = is_last; 352 ch->io.dma_end = dbdma_end; 353 ch->io.is_dma_out = 0; 354 ch->io.processing = true; 355 if (ch->rw) { 356 ch->rw(&ch->io); 357 } 358 } 359 360 static void load_word(DBDMA_channel *ch, int key, uint32_t addr, 361 uint16_t len) 362 { 363 dbdma_cmd *current = &ch->current; 364 365 DBDMA_DPRINTFCH(ch, "load_word %d bytes, addr=%08x\n", len, addr); 366 367 /* only implements KEY_SYSTEM */ 368 369 if (key != KEY_SYSTEM) { 370 printf("DBDMA: LOAD_WORD, unimplemented key %x\n", key); 371 kill_channel(ch); 372 return; 373 } 374 375 dma_memory_read(&address_space_memory, addr, ¤t->cmd_dep, len); 376 377 if (conditional_wait(ch)) 378 goto wait; 379 380 current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]); 381 dbdma_cmdptr_save(ch); 382 ch->regs[DBDMA_STATUS] &= ~FLUSH; 383 384 conditional_interrupt(ch); 385 next(ch); 386 387 wait: 388 DBDMA_kick(dbdma_from_ch(ch)); 389 } 390 391 static void store_word(DBDMA_channel *ch, int key, uint32_t addr, 392 uint16_t len) 393 { 394 dbdma_cmd *current = &ch->current; 395 396 DBDMA_DPRINTFCH(ch, "store_word %d bytes, addr=%08x pa=%x\n", 397 len, addr, le32_to_cpu(current->cmd_dep)); 398 399 /* only implements KEY_SYSTEM */ 400 401 if (key != KEY_SYSTEM) { 402 printf("DBDMA: STORE_WORD, unimplemented key %x\n", key); 403 kill_channel(ch); 404 return; 405 } 406 407 dma_memory_write(&address_space_memory, addr, ¤t->cmd_dep, len); 408 409 if (conditional_wait(ch)) 410 goto wait; 411 412 current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]); 413 dbdma_cmdptr_save(ch); 414 ch->regs[DBDMA_STATUS] &= ~FLUSH; 415 416 conditional_interrupt(ch); 417 next(ch); 418 419 wait: 420 DBDMA_kick(dbdma_from_ch(ch)); 421 } 422 423 static void nop(DBDMA_channel *ch) 424 { 425 dbdma_cmd *current = &ch->current; 426 427 if (conditional_wait(ch)) 428 goto wait; 429 430 current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]); 431 dbdma_cmdptr_save(ch); 432 433 conditional_interrupt(ch); 434 conditional_branch(ch); 435 436 wait: 437 DBDMA_kick(dbdma_from_ch(ch)); 438 } 439 440 static void stop(DBDMA_channel *ch) 441 { 442 ch->regs[DBDMA_STATUS] &= ~(ACTIVE); 443 444 /* the stop command does not increment command pointer */ 445 } 446 447 static void channel_run(DBDMA_channel *ch) 448 { 449 dbdma_cmd *current = &ch->current; 450 uint16_t cmd, key; 451 uint16_t req_count; 452 uint32_t phy_addr; 453 454 DBDMA_DPRINTFCH(ch, "channel_run\n"); 455 dump_dbdma_cmd(ch, current); 456 457 /* clear WAKE flag at command fetch */ 458 459 ch->regs[DBDMA_STATUS] &= ~WAKE; 460 461 cmd = le16_to_cpu(current->command) & COMMAND_MASK; 462 463 switch (cmd) { 464 case DBDMA_NOP: 465 nop(ch); 466 return; 467 468 case DBDMA_STOP: 469 stop(ch); 470 return; 471 } 472 473 key = le16_to_cpu(current->command) & 0x0700; 474 req_count = le16_to_cpu(current->req_count); 475 phy_addr = le32_to_cpu(current->phy_addr); 476 477 if (key == KEY_STREAM4) { 478 printf("command %x, invalid key 4\n", cmd); 479 kill_channel(ch); 480 return; 481 } 482 483 switch (cmd) { 484 case OUTPUT_MORE: 485 DBDMA_DPRINTFCH(ch, "* OUTPUT_MORE *\n"); 486 start_output(ch, key, phy_addr, req_count, 0); 487 return; 488 489 case OUTPUT_LAST: 490 DBDMA_DPRINTFCH(ch, "* OUTPUT_LAST *\n"); 491 start_output(ch, key, phy_addr, req_count, 1); 492 return; 493 494 case INPUT_MORE: 495 DBDMA_DPRINTFCH(ch, "* INPUT_MORE *\n"); 496 start_input(ch, key, phy_addr, req_count, 0); 497 return; 498 499 case INPUT_LAST: 500 DBDMA_DPRINTFCH(ch, "* INPUT_LAST *\n"); 501 start_input(ch, key, phy_addr, req_count, 1); 502 return; 503 } 504 505 if (key < KEY_REGS) { 506 printf("command %x, invalid key %x\n", cmd, key); 507 key = KEY_SYSTEM; 508 } 509 510 /* for LOAD_WORD and STORE_WORD, req_count is on 3 bits 511 * and BRANCH is invalid 512 */ 513 514 req_count = req_count & 0x0007; 515 if (req_count & 0x4) { 516 req_count = 4; 517 phy_addr &= ~3; 518 } else if (req_count & 0x2) { 519 req_count = 2; 520 phy_addr &= ~1; 521 } else 522 req_count = 1; 523 524 switch (cmd) { 525 case LOAD_WORD: 526 DBDMA_DPRINTFCH(ch, "* LOAD_WORD *\n"); 527 load_word(ch, key, phy_addr, req_count); 528 return; 529 530 case STORE_WORD: 531 DBDMA_DPRINTFCH(ch, "* STORE_WORD *\n"); 532 store_word(ch, key, phy_addr, req_count); 533 return; 534 } 535 } 536 537 static void DBDMA_run(DBDMAState *s) 538 { 539 int channel; 540 541 for (channel = 0; channel < DBDMA_CHANNELS; channel++) { 542 DBDMA_channel *ch = &s->channels[channel]; 543 uint32_t status = ch->regs[DBDMA_STATUS]; 544 if (!ch->io.processing && (status & RUN) && (status & ACTIVE)) { 545 channel_run(ch); 546 } 547 } 548 } 549 550 static void DBDMA_run_bh(void *opaque) 551 { 552 DBDMAState *s = opaque; 553 554 DBDMA_DPRINTF("-> DBDMA_run_bh\n"); 555 DBDMA_run(s); 556 DBDMA_DPRINTF("<- DBDMA_run_bh\n"); 557 } 558 559 void DBDMA_kick(DBDMAState *dbdma) 560 { 561 qemu_bh_schedule(dbdma->bh); 562 } 563 564 void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq, 565 DBDMA_rw rw, DBDMA_flush flush, 566 void *opaque) 567 { 568 DBDMAState *s = dbdma; 569 DBDMA_channel *ch = &s->channels[nchan]; 570 571 DBDMA_DPRINTFCH(ch, "DBDMA_register_channel 0x%x\n", nchan); 572 573 assert(rw); 574 assert(flush); 575 576 ch->irq = irq; 577 ch->rw = rw; 578 ch->flush = flush; 579 ch->io.opaque = opaque; 580 } 581 582 static void dbdma_control_write(DBDMA_channel *ch) 583 { 584 uint16_t mask, value; 585 uint32_t status; 586 bool do_flush = false; 587 588 mask = (ch->regs[DBDMA_CONTROL] >> 16) & 0xffff; 589 value = ch->regs[DBDMA_CONTROL] & 0xffff; 590 591 /* This is the status register which we'll update 592 * appropriately and store back 593 */ 594 status = ch->regs[DBDMA_STATUS]; 595 596 /* RUN and PAUSE are bits under SW control only 597 * FLUSH and WAKE are set by SW and cleared by HW 598 * DEAD, ACTIVE and BT are only under HW control 599 * 600 * We handle ACTIVE separately at the end of the 601 * logic to ensure all cases are covered. 602 */ 603 604 /* Setting RUN will tentatively activate the channel 605 */ 606 if ((mask & RUN) && (value & RUN)) { 607 status |= RUN; 608 DBDMA_DPRINTFCH(ch, " Setting RUN !\n"); 609 } 610 611 /* Clearing RUN 1->0 will stop the channel */ 612 if ((mask & RUN) && !(value & RUN)) { 613 /* This has the side effect of clearing the DEAD bit */ 614 status &= ~(DEAD | RUN); 615 DBDMA_DPRINTFCH(ch, " Clearing RUN !\n"); 616 } 617 618 /* Setting WAKE wakes up an idle channel if it's running 619 * 620 * Note: The doc doesn't say so but assume that only works 621 * on a channel whose RUN bit is set. 622 * 623 * We set WAKE in status, it's not terribly useful as it will 624 * be cleared on the next command fetch but it seems to mimmic 625 * the HW behaviour and is useful for the way we handle 626 * ACTIVE further down. 627 */ 628 if ((mask & WAKE) && (value & WAKE) && (status & RUN)) { 629 status |= WAKE; 630 DBDMA_DPRINTFCH(ch, " Setting WAKE !\n"); 631 } 632 633 /* PAUSE being set will deactivate (or prevent activation) 634 * of the channel. We just copy it over for now, ACTIVE will 635 * be re-evaluated later. 636 */ 637 if (mask & PAUSE) { 638 status = (status & ~PAUSE) | (value & PAUSE); 639 DBDMA_DPRINTFCH(ch, " %sing PAUSE !\n", 640 (value & PAUSE) ? "sett" : "clear"); 641 } 642 643 /* FLUSH is its own thing */ 644 if ((mask & FLUSH) && (value & FLUSH)) { 645 DBDMA_DPRINTFCH(ch, " Setting FLUSH !\n"); 646 /* We set flush directly in the status register, we do *NOT* 647 * set it in "status" so that it gets naturally cleared when 648 * we update the status register further down. That way it 649 * will be set only during the HW flush operation so it is 650 * visible to any completions happening during that time. 651 */ 652 ch->regs[DBDMA_STATUS] |= FLUSH; 653 do_flush = true; 654 } 655 656 /* If either RUN or PAUSE is clear, so should ACTIVE be, 657 * otherwise, ACTIVE will be set if we modified RUN, PAUSE or 658 * set WAKE. That means that PAUSE was just cleared, RUN was 659 * just set or WAKE was just set. 660 */ 661 if ((status & PAUSE) || !(status & RUN)) { 662 status &= ~ACTIVE; 663 DBDMA_DPRINTFCH(ch, " -> ACTIVE down !\n"); 664 665 /* We stopped processing, we want the underlying HW command 666 * to complete *before* we clear the ACTIVE bit. Otherwise 667 * we can get into a situation where the command status will 668 * have RUN or ACTIVE not set which is going to confuse the 669 * MacOS driver. 670 */ 671 do_flush = true; 672 } else if (mask & (RUN | PAUSE)) { 673 status |= ACTIVE; 674 DBDMA_DPRINTFCH(ch, " -> ACTIVE up !\n"); 675 } else if ((mask & WAKE) && (value & WAKE)) { 676 status |= ACTIVE; 677 DBDMA_DPRINTFCH(ch, " -> ACTIVE up !\n"); 678 } 679 680 DBDMA_DPRINTFCH(ch, " new status=0x%08x\n", status); 681 682 /* If we need to flush the underlying HW, do it now, this happens 683 * both on FLUSH commands and when stopping the channel for safety. 684 */ 685 if (do_flush && ch->flush) { 686 ch->flush(&ch->io); 687 } 688 689 /* Finally update the status register image */ 690 ch->regs[DBDMA_STATUS] = status; 691 692 /* If active, make sure the BH gets to run */ 693 if (status & ACTIVE) { 694 DBDMA_kick(dbdma_from_ch(ch)); 695 } 696 } 697 698 static void dbdma_write(void *opaque, hwaddr addr, 699 uint64_t value, unsigned size) 700 { 701 int channel = addr >> DBDMA_CHANNEL_SHIFT; 702 DBDMAState *s = opaque; 703 DBDMA_channel *ch = &s->channels[channel]; 704 int reg = (addr - (channel << DBDMA_CHANNEL_SHIFT)) >> 2; 705 706 DBDMA_DPRINTFCH(ch, "writel 0x" TARGET_FMT_plx " <= 0x%08"PRIx64"\n", 707 addr, value); 708 DBDMA_DPRINTFCH(ch, "channel 0x%x reg 0x%x\n", 709 (uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg); 710 711 /* cmdptr cannot be modified if channel is ACTIVE */ 712 713 if (reg == DBDMA_CMDPTR_LO && (ch->regs[DBDMA_STATUS] & ACTIVE)) { 714 return; 715 } 716 717 ch->regs[reg] = value; 718 719 switch(reg) { 720 case DBDMA_CONTROL: 721 dbdma_control_write(ch); 722 break; 723 case DBDMA_CMDPTR_LO: 724 /* 16-byte aligned */ 725 ch->regs[DBDMA_CMDPTR_LO] &= ~0xf; 726 dbdma_cmdptr_load(ch); 727 break; 728 case DBDMA_STATUS: 729 case DBDMA_INTR_SEL: 730 case DBDMA_BRANCH_SEL: 731 case DBDMA_WAIT_SEL: 732 /* nothing to do */ 733 break; 734 case DBDMA_XFER_MODE: 735 case DBDMA_CMDPTR_HI: 736 case DBDMA_DATA2PTR_HI: 737 case DBDMA_DATA2PTR_LO: 738 case DBDMA_ADDRESS_HI: 739 case DBDMA_BRANCH_ADDR_HI: 740 case DBDMA_RES1: 741 case DBDMA_RES2: 742 case DBDMA_RES3: 743 case DBDMA_RES4: 744 /* unused */ 745 break; 746 } 747 } 748 749 static uint64_t dbdma_read(void *opaque, hwaddr addr, 750 unsigned size) 751 { 752 uint32_t value; 753 int channel = addr >> DBDMA_CHANNEL_SHIFT; 754 DBDMAState *s = opaque; 755 DBDMA_channel *ch = &s->channels[channel]; 756 int reg = (addr - (channel << DBDMA_CHANNEL_SHIFT)) >> 2; 757 758 value = ch->regs[reg]; 759 760 switch(reg) { 761 case DBDMA_CONTROL: 762 value = ch->regs[DBDMA_STATUS]; 763 break; 764 case DBDMA_STATUS: 765 case DBDMA_CMDPTR_LO: 766 case DBDMA_INTR_SEL: 767 case DBDMA_BRANCH_SEL: 768 case DBDMA_WAIT_SEL: 769 /* nothing to do */ 770 break; 771 case DBDMA_XFER_MODE: 772 case DBDMA_CMDPTR_HI: 773 case DBDMA_DATA2PTR_HI: 774 case DBDMA_DATA2PTR_LO: 775 case DBDMA_ADDRESS_HI: 776 case DBDMA_BRANCH_ADDR_HI: 777 /* unused */ 778 value = 0; 779 break; 780 case DBDMA_RES1: 781 case DBDMA_RES2: 782 case DBDMA_RES3: 783 case DBDMA_RES4: 784 /* reserved */ 785 break; 786 } 787 788 DBDMA_DPRINTFCH(ch, "readl 0x" TARGET_FMT_plx " => 0x%08x\n", addr, value); 789 DBDMA_DPRINTFCH(ch, "channel 0x%x reg 0x%x\n", 790 (uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg); 791 792 return value; 793 } 794 795 static const MemoryRegionOps dbdma_ops = { 796 .read = dbdma_read, 797 .write = dbdma_write, 798 .endianness = DEVICE_LITTLE_ENDIAN, 799 .valid = { 800 .min_access_size = 4, 801 .max_access_size = 4, 802 }, 803 }; 804 805 static const VMStateDescription vmstate_dbdma_io = { 806 .name = "dbdma_io", 807 .version_id = 0, 808 .minimum_version_id = 0, 809 .fields = (VMStateField[]) { 810 VMSTATE_UINT64(addr, struct DBDMA_io), 811 VMSTATE_INT32(len, struct DBDMA_io), 812 VMSTATE_INT32(is_last, struct DBDMA_io), 813 VMSTATE_INT32(is_dma_out, struct DBDMA_io), 814 VMSTATE_BOOL(processing, struct DBDMA_io), 815 VMSTATE_END_OF_LIST() 816 } 817 }; 818 819 static const VMStateDescription vmstate_dbdma_cmd = { 820 .name = "dbdma_cmd", 821 .version_id = 0, 822 .minimum_version_id = 0, 823 .fields = (VMStateField[]) { 824 VMSTATE_UINT16(req_count, dbdma_cmd), 825 VMSTATE_UINT16(command, dbdma_cmd), 826 VMSTATE_UINT32(phy_addr, dbdma_cmd), 827 VMSTATE_UINT32(cmd_dep, dbdma_cmd), 828 VMSTATE_UINT16(res_count, dbdma_cmd), 829 VMSTATE_UINT16(xfer_status, dbdma_cmd), 830 VMSTATE_END_OF_LIST() 831 } 832 }; 833 834 static const VMStateDescription vmstate_dbdma_channel = { 835 .name = "dbdma_channel", 836 .version_id = 1, 837 .minimum_version_id = 1, 838 .fields = (VMStateField[]) { 839 VMSTATE_UINT32_ARRAY(regs, struct DBDMA_channel, DBDMA_REGS), 840 VMSTATE_STRUCT(io, struct DBDMA_channel, 0, vmstate_dbdma_io, DBDMA_io), 841 VMSTATE_STRUCT(current, struct DBDMA_channel, 0, vmstate_dbdma_cmd, 842 dbdma_cmd), 843 VMSTATE_END_OF_LIST() 844 } 845 }; 846 847 static const VMStateDescription vmstate_dbdma = { 848 .name = "dbdma", 849 .version_id = 3, 850 .minimum_version_id = 3, 851 .fields = (VMStateField[]) { 852 VMSTATE_STRUCT_ARRAY(channels, DBDMAState, DBDMA_CHANNELS, 1, 853 vmstate_dbdma_channel, DBDMA_channel), 854 VMSTATE_END_OF_LIST() 855 } 856 }; 857 858 static void mac_dbdma_reset(DeviceState *d) 859 { 860 DBDMAState *s = MAC_DBDMA(d); 861 int i; 862 863 for (i = 0; i < DBDMA_CHANNELS; i++) { 864 memset(s->channels[i].regs, 0, DBDMA_SIZE); 865 } 866 } 867 868 static void dbdma_unassigned_rw(DBDMA_io *io) 869 { 870 DBDMA_channel *ch = io->channel; 871 dbdma_cmd *current = &ch->current; 872 uint16_t cmd; 873 qemu_log_mask(LOG_GUEST_ERROR, "%s: use of unassigned channel %d\n", 874 __func__, ch->channel); 875 ch->io.processing = false; 876 877 cmd = le16_to_cpu(current->command) & COMMAND_MASK; 878 if (cmd == OUTPUT_MORE || cmd == OUTPUT_LAST || 879 cmd == INPUT_MORE || cmd == INPUT_LAST) { 880 current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]); 881 current->res_count = cpu_to_le16(io->len); 882 dbdma_cmdptr_save(ch); 883 } 884 } 885 886 static void dbdma_unassigned_flush(DBDMA_io *io) 887 { 888 DBDMA_channel *ch = io->channel; 889 qemu_log_mask(LOG_GUEST_ERROR, "%s: use of unassigned channel %d\n", 890 __func__, ch->channel); 891 } 892 893 static void mac_dbdma_init(Object *obj) 894 { 895 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 896 DBDMAState *s = MAC_DBDMA(obj); 897 int i; 898 899 for (i = 0; i < DBDMA_CHANNELS; i++) { 900 DBDMA_channel *ch = &s->channels[i]; 901 902 ch->rw = dbdma_unassigned_rw; 903 ch->flush = dbdma_unassigned_flush; 904 ch->channel = i; 905 ch->io.channel = ch; 906 } 907 908 memory_region_init_io(&s->mem, obj, &dbdma_ops, s, "dbdma", 0x1000); 909 sysbus_init_mmio(sbd, &s->mem); 910 } 911 912 static void mac_dbdma_realize(DeviceState *dev, Error **errp) 913 { 914 DBDMAState *s = MAC_DBDMA(dev); 915 916 s->bh = qemu_bh_new(DBDMA_run_bh, s); 917 } 918 919 static void mac_dbdma_class_init(ObjectClass *oc, void *data) 920 { 921 DeviceClass *dc = DEVICE_CLASS(oc); 922 923 dc->realize = mac_dbdma_realize; 924 dc->reset = mac_dbdma_reset; 925 dc->vmsd = &vmstate_dbdma; 926 } 927 928 static const TypeInfo mac_dbdma_type_info = { 929 .name = TYPE_MAC_DBDMA, 930 .parent = TYPE_SYS_BUS_DEVICE, 931 .instance_size = sizeof(DBDMAState), 932 .instance_init = mac_dbdma_init, 933 .class_init = mac_dbdma_class_init 934 }; 935 936 static void mac_dbdma_register_types(void) 937 { 938 type_register_static(&mac_dbdma_type_info); 939 } 940 941 type_init(mac_dbdma_register_types) 942