xref: /openbmc/qemu/include/hw/arm/aspeed_soc.h (revision f7da1aa8fee9d0a4eb013ff8c173ead5a26e930e)
1 /*
2  * ASPEED SoC family
3  *
4  * Andrew Jeffery <andrew@aj.id.au>
5  *
6  * Copyright 2016 IBM Corp.
7  *
8  * This code is licensed under the GPL version 2 or later.  See
9  * the COPYING file in the top-level directory.
10  */
11 
12 #ifndef ASPEED_SOC_H
13 #define ASPEED_SOC_H
14 
15 #include "hw/intc/aspeed_vic.h"
16 #include "hw/misc/aspeed_scu.h"
17 #include "hw/misc/aspeed_sdmc.h"
18 #include "hw/misc/aspeed_xdma.h"
19 #include "hw/timer/aspeed_timer.h"
20 #include "hw/timer/aspeed_rtc.h"
21 #include "hw/i2c/aspeed_i2c.h"
22 #include "hw/ssi/aspeed_smc.h"
23 #include "hw/watchdog/wdt_aspeed.h"
24 #include "hw/net/ftgmac100.h"
25 #include "target/arm/cpu.h"
26 #include "hw/gpio/aspeed_gpio.h"
27 #include "hw/sd/aspeed_sdhci.h"
28 
29 #define ASPEED_SPIS_NUM  2
30 #define ASPEED_WDTS_NUM  4
31 #define ASPEED_CPUS_NUM  2
32 #define ASPEED_MACS_NUM  2
33 
34 typedef struct AspeedSoCState {
35     /*< private >*/
36     DeviceState parent;
37 
38     /*< public >*/
39     ARMCPU cpu[ASPEED_CPUS_NUM];
40     uint32_t num_cpus;
41     MemoryRegion sram;
42     AspeedVICState vic;
43     AspeedRtcState rtc;
44     AspeedTimerCtrlState timerctrl;
45     AspeedI2CState i2c;
46     AspeedSCUState scu;
47     AspeedXDMAState xdma;
48     AspeedSMCState fmc;
49     AspeedSMCState spi[ASPEED_SPIS_NUM];
50     AspeedSDMCState sdmc;
51     AspeedWDTState wdt[ASPEED_WDTS_NUM];
52     FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
53     AspeedGPIOState gpio;
54     AspeedSDHCIState sdhci;
55 } AspeedSoCState;
56 
57 #define TYPE_ASPEED_SOC "aspeed-soc"
58 #define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC)
59 
60 typedef struct AspeedSoCInfo {
61     const char *name;
62     const char *cpu_type;
63     uint32_t silicon_rev;
64     uint64_t sram_size;
65     int spis_num;
66     int wdts_num;
67     const int *irqmap;
68     const hwaddr *memmap;
69     uint32_t num_cpus;
70 } AspeedSoCInfo;
71 
72 typedef struct AspeedSoCClass {
73     DeviceClass parent_class;
74     AspeedSoCInfo *info;
75 } AspeedSoCClass;
76 
77 #define ASPEED_SOC_CLASS(klass)                                         \
78     OBJECT_CLASS_CHECK(AspeedSoCClass, (klass), TYPE_ASPEED_SOC)
79 #define ASPEED_SOC_GET_CLASS(obj)                               \
80     OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC)
81 
82 enum {
83     ASPEED_IOMEM,
84     ASPEED_UART1,
85     ASPEED_UART2,
86     ASPEED_UART3,
87     ASPEED_UART4,
88     ASPEED_UART5,
89     ASPEED_VUART,
90     ASPEED_FMC,
91     ASPEED_SPI1,
92     ASPEED_SPI2,
93     ASPEED_VIC,
94     ASPEED_SDMC,
95     ASPEED_SCU,
96     ASPEED_ADC,
97     ASPEED_SRAM,
98     ASPEED_SDHCI,
99     ASPEED_GPIO,
100     ASPEED_RTC,
101     ASPEED_TIMER1,
102     ASPEED_TIMER2,
103     ASPEED_TIMER3,
104     ASPEED_TIMER4,
105     ASPEED_TIMER5,
106     ASPEED_TIMER6,
107     ASPEED_TIMER7,
108     ASPEED_TIMER8,
109     ASPEED_WDT,
110     ASPEED_PWM,
111     ASPEED_LPC,
112     ASPEED_IBT,
113     ASPEED_I2C,
114     ASPEED_ETH1,
115     ASPEED_ETH2,
116     ASPEED_SDRAM,
117     ASPEED_XDMA,
118 };
119 
120 #endif /* ASPEED_SOC_H */
121