1 /* 2 * QEMU IDE Emulation: PCI VIA82C686B support. 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * Copyright (c) 2006 Openedhand Ltd. 6 * Copyright (c) 2010 Huacai Chen <zltjiangshi@gmail.com> 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "hw/hw.h" 29 #include "hw/pci/pci.h" 30 #include "migration/vmstate.h" 31 #include "qemu/module.h" 32 #include "sysemu/sysemu.h" 33 #include "sysemu/dma.h" 34 #include "sysemu/reset.h" 35 36 #include "hw/ide/pci.h" 37 #include "trace.h" 38 39 static uint64_t bmdma_read(void *opaque, hwaddr addr, 40 unsigned size) 41 { 42 BMDMAState *bm = opaque; 43 uint32_t val; 44 45 if (size != 1) { 46 return ((uint64_t)1 << (size * 8)) - 1; 47 } 48 49 switch (addr & 3) { 50 case 0: 51 val = bm->cmd; 52 break; 53 case 2: 54 val = bm->status; 55 break; 56 default: 57 val = 0xff; 58 break; 59 } 60 61 trace_bmdma_read_via(addr, val); 62 return val; 63 } 64 65 static void bmdma_write(void *opaque, hwaddr addr, 66 uint64_t val, unsigned size) 67 { 68 BMDMAState *bm = opaque; 69 70 if (size != 1) { 71 return; 72 } 73 74 trace_bmdma_write_via(addr, val); 75 switch (addr & 3) { 76 case 0: 77 bmdma_cmd_writeb(bm, val); 78 break; 79 case 2: 80 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06); 81 break; 82 default:; 83 } 84 } 85 86 static const MemoryRegionOps via_bmdma_ops = { 87 .read = bmdma_read, 88 .write = bmdma_write, 89 }; 90 91 static void bmdma_setup_bar(PCIIDEState *d) 92 { 93 int i; 94 95 memory_region_init(&d->bmdma_bar, OBJECT(d), "via-bmdma-container", 16); 96 for(i = 0;i < 2; i++) { 97 BMDMAState *bm = &d->bmdma[i]; 98 99 memory_region_init_io(&bm->extra_io, OBJECT(d), &via_bmdma_ops, bm, 100 "via-bmdma", 4); 101 memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io); 102 memory_region_init_io(&bm->addr_ioport, OBJECT(d), 103 &bmdma_addr_ioport_ops, bm, "bmdma", 4); 104 memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport); 105 } 106 } 107 108 static void via_ide_set_irq(void *opaque, int n, int level) 109 { 110 PCIDevice *d = PCI_DEVICE(opaque); 111 112 if (level) { 113 d->config[0x70 + n * 8] |= 0x80; 114 } else { 115 d->config[0x70 + n * 8] &= ~0x80; 116 } 117 118 level = (d->config[0x70] & 0x80) || (d->config[0x78] & 0x80); 119 n = pci_get_byte(d->config + PCI_INTERRUPT_LINE); 120 if (n) { 121 qemu_set_irq(isa_get_irq(NULL, n), level); 122 } 123 } 124 125 static void via_ide_reset(void *opaque) 126 { 127 PCIIDEState *d = opaque; 128 PCIDevice *pd = PCI_DEVICE(d); 129 uint8_t *pci_conf = pd->config; 130 int i; 131 132 for (i = 0; i < 2; i++) { 133 ide_bus_reset(&d->bus[i]); 134 } 135 136 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_WAIT); 137 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK | 138 PCI_STATUS_DEVSEL_MEDIUM); 139 140 pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, 0x000001f0); 141 pci_set_long(pci_conf + PCI_BASE_ADDRESS_1, 0x000003f4); 142 pci_set_long(pci_conf + PCI_BASE_ADDRESS_2, 0x00000170); 143 pci_set_long(pci_conf + PCI_BASE_ADDRESS_3, 0x00000374); 144 pci_set_long(pci_conf + PCI_BASE_ADDRESS_4, 0x0000cc01); /* BMIBA: 20-23h */ 145 pci_set_long(pci_conf + PCI_INTERRUPT_LINE, 0x0000010e); 146 147 /* IDE chip enable, IDE configuration 1/2, IDE FIFO Configuration*/ 148 pci_set_long(pci_conf + 0x40, 0x0a090600); 149 /* IDE misc configuration 1/2/3 */ 150 pci_set_long(pci_conf + 0x44, 0x00c00068); 151 /* IDE Timing control */ 152 pci_set_long(pci_conf + 0x48, 0xa8a8a8a8); 153 /* IDE Address Setup Time */ 154 pci_set_long(pci_conf + 0x4c, 0x000000ff); 155 /* UltraDMA Extended Timing Control*/ 156 pci_set_long(pci_conf + 0x50, 0x07070707); 157 /* UltraDMA FIFO Control */ 158 pci_set_long(pci_conf + 0x54, 0x00000004); 159 /* IDE primary sector size */ 160 pci_set_long(pci_conf + 0x60, 0x00000200); 161 /* IDE secondary sector size */ 162 pci_set_long(pci_conf + 0x68, 0x00000200); 163 /* PCI PM Block */ 164 pci_set_long(pci_conf + 0xc0, 0x00020001); 165 } 166 167 static void via_ide_realize(PCIDevice *dev, Error **errp) 168 { 169 PCIIDEState *d = PCI_IDE(dev); 170 uint8_t *pci_conf = dev->config; 171 int i; 172 173 pci_config_set_prog_interface(pci_conf, 0x8f); /* native PCI ATA mode */ 174 pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); 175 dev->wmask[PCI_INTERRUPT_LINE] = 0xf; 176 177 qemu_register_reset(via_ide_reset, d); 178 179 memory_region_init_io(&d->data_bar[0], OBJECT(d), &pci_ide_data_le_ops, 180 &d->bus[0], "via-ide0-data", 8); 181 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[0]); 182 183 memory_region_init_io(&d->cmd_bar[0], OBJECT(d), &pci_ide_cmd_le_ops, 184 &d->bus[0], "via-ide0-cmd", 4); 185 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[0]); 186 187 memory_region_init_io(&d->data_bar[1], OBJECT(d), &pci_ide_data_le_ops, 188 &d->bus[1], "via-ide1-data", 8); 189 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[1]); 190 191 memory_region_init_io(&d->cmd_bar[1], OBJECT(d), &pci_ide_cmd_le_ops, 192 &d->bus[1], "via-ide1-cmd", 4); 193 pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[1]); 194 195 bmdma_setup_bar(d); 196 pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); 197 198 vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d); 199 200 for (i = 0; i < 2; i++) { 201 ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2); 202 ide_init2(&d->bus[i], qemu_allocate_irq(via_ide_set_irq, d, i)); 203 204 bmdma_init(&d->bus[i], &d->bmdma[i], d); 205 d->bmdma[i].bus = &d->bus[i]; 206 ide_register_restart_cb(&d->bus[i]); 207 } 208 } 209 210 static void via_ide_exitfn(PCIDevice *dev) 211 { 212 PCIIDEState *d = PCI_IDE(dev); 213 unsigned i; 214 215 for (i = 0; i < 2; ++i) { 216 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io); 217 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport); 218 } 219 } 220 221 void via_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn) 222 { 223 PCIDevice *dev; 224 225 dev = pci_create_simple(bus, devfn, "via-ide"); 226 pci_ide_create_devs(dev, hd_table); 227 } 228 229 static void via_ide_class_init(ObjectClass *klass, void *data) 230 { 231 DeviceClass *dc = DEVICE_CLASS(klass); 232 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 233 234 k->realize = via_ide_realize; 235 k->exit = via_ide_exitfn; 236 k->vendor_id = PCI_VENDOR_ID_VIA; 237 k->device_id = PCI_DEVICE_ID_VIA_IDE; 238 k->revision = 0x06; 239 k->class_id = PCI_CLASS_STORAGE_IDE; 240 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 241 } 242 243 static const TypeInfo via_ide_info = { 244 .name = "via-ide", 245 .parent = TYPE_PCI_IDE, 246 .class_init = via_ide_class_init, 247 }; 248 249 static void via_ide_register_types(void) 250 { 251 type_register_static(&via_ide_info); 252 } 253 254 type_init(via_ide_register_types) 255