xref: /openbmc/qemu/hw/i2c/smbus_ich9.c (revision 93198b6cad8af03996373584284a1673ad6000cb)
1 /*
2  * ACPI implementation
3  *
4  * Copyright (c) 2006 Fabrice Bellard
5  * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
6  *               VA Linux Systems Japan K.K.
7  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
8  *
9  * This is based on acpi.c, but heavily rewritten.
10  *
11  * This library is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU Lesser General Public
13  * License version 2 as published by the Free Software Foundation.
14  *
15  * This library is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
18  * Lesser General Public License for more details.
19  *
20  * You should have received a copy of the GNU Lesser General Public
21  * License along with this library; if not, see <http://www.gnu.org/licenses/>
22  *
23  * Contributions after 2012-01-13 are licensed under the terms of the
24  * GNU GPL, version 2 or (at your option) any later version.
25  *
26  */
27 #include "qemu/osdep.h"
28 #include "hw/hw.h"
29 #include "hw/i2c/pm_smbus.h"
30 #include "hw/pci/pci.h"
31 #include "sysemu/sysemu.h"
32 
33 #include "hw/i386/ich9.h"
34 
35 #define ICH9_SMB_DEVICE(obj) \
36      OBJECT_CHECK(ICH9SMBState, (obj), TYPE_ICH9_SMB_DEVICE)
37 
38 typedef struct ICH9SMBState {
39     PCIDevice dev;
40 
41     bool irq_enabled;
42 
43     PMSMBus smb;
44 } ICH9SMBState;
45 
46 static const VMStateDescription vmstate_ich9_smbus = {
47     .name = "ich9_smb",
48     .version_id = 1,
49     .minimum_version_id = 1,
50     .fields = (VMStateField[]) {
51         VMSTATE_PCI_DEVICE(dev, struct ICH9SMBState),
52         VMSTATE_END_OF_LIST()
53     }
54 };
55 
56 static void ich9_smbus_write_config(PCIDevice *d, uint32_t address,
57                                     uint32_t val, int len)
58 {
59     ICH9SMBState *s = ICH9_SMB_DEVICE(d);
60 
61     pci_default_write_config(d, address, val, len);
62     if (range_covers_byte(address, len, ICH9_SMB_HOSTC)) {
63         uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC];
64         if (hostc & ICH9_SMB_HOSTC_HST_EN) {
65             memory_region_set_enabled(&s->smb.io, true);
66         } else {
67             memory_region_set_enabled(&s->smb.io, false);
68         }
69         s->smb.i2c_enable = (hostc & ICH9_SMB_HOSTC_I2C_EN) != 0;
70         if (hostc & ICH9_SMB_HOSTC_SSRESET) {
71             s->smb.reset(&s->smb);
72             s->dev.config[ICH9_SMB_HOSTC] &= ~ICH9_SMB_HOSTC_SSRESET;
73         }
74     }
75 }
76 
77 static void ich9_smbus_realize(PCIDevice *d, Error **errp)
78 {
79     ICH9SMBState *s = ICH9_SMB_DEVICE(d);
80 
81     /* TODO? D31IP.SMIP in chipset configuration space */
82     pci_config_set_interrupt_pin(d->config, 0x01); /* interrupt pin 1 */
83 
84     pci_set_byte(d->config + ICH9_SMB_HOSTC, 0);
85     /* TODO bar0, bar1: 64bit BAR support*/
86 
87     pm_smbus_init(&d->qdev, &s->smb, false);
88     pci_register_bar(d, ICH9_SMB_SMB_BASE_BAR, PCI_BASE_ADDRESS_SPACE_IO,
89                      &s->smb.io);
90 }
91 
92 static void ich9_smb_class_init(ObjectClass *klass, void *data)
93 {
94     DeviceClass *dc = DEVICE_CLASS(klass);
95     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
96 
97     k->vendor_id = PCI_VENDOR_ID_INTEL;
98     k->device_id = PCI_DEVICE_ID_INTEL_ICH9_6;
99     k->revision = ICH9_A2_SMB_REVISION;
100     k->class_id = PCI_CLASS_SERIAL_SMBUS;
101     dc->vmsd = &vmstate_ich9_smbus;
102     dc->desc = "ICH9 SMBUS Bridge";
103     k->realize = ich9_smbus_realize;
104     k->config_write = ich9_smbus_write_config;
105     /*
106      * Reason: part of ICH9 southbridge, needs to be wired up by
107      * pc_q35_init()
108      */
109     dc->user_creatable = false;
110 }
111 
112 static void ich9_smb_set_irq(PMSMBus *pmsmb, bool enabled)
113 {
114     ICH9SMBState *s = pmsmb->opaque;
115 
116     if (enabled == s->irq_enabled) {
117         return;
118     }
119 
120     s->irq_enabled = enabled;
121     pci_set_irq(&s->dev, enabled);
122 }
123 
124 I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
125 {
126     PCIDevice *d =
127         pci_create_simple_multifunction(bus, devfn, true, TYPE_ICH9_SMB_DEVICE);
128     ICH9SMBState *s = ICH9_SMB_DEVICE(d);
129     s->smb.set_irq = ich9_smb_set_irq;
130     s->smb.opaque = s;
131     return s->smb.smbus;
132 }
133 
134 static const TypeInfo ich9_smb_info = {
135     .name   = TYPE_ICH9_SMB_DEVICE,
136     .parent = TYPE_PCI_DEVICE,
137     .instance_size = sizeof(ICH9SMBState),
138     .class_init = ich9_smb_class_init,
139     .interfaces = (InterfaceInfo[]) {
140         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
141         { },
142     },
143 };
144 
145 static void ich9_smb_register(void)
146 {
147     type_register_static(&ich9_smb_info);
148 }
149 
150 type_init(ich9_smb_register);
151