1 /* 2 * ARM Aspeed I2C controller 3 * 4 * Copyright (C) 2016 IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 * 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/sysbus.h" 23 #include "migration/vmstate.h" 24 #include "qemu/log.h" 25 #include "qemu/module.h" 26 #include "hw/i2c/aspeed_i2c.h" 27 #include "hw/irq.h" 28 29 /* I2C Global Register */ 30 31 #define I2C_CTRL_STATUS 0x00 /* Device Interrupt Status */ 32 #define I2C_CTRL_ASSIGN 0x08 /* Device Interrupt Target 33 Assignment */ 34 35 /* I2C Device (Bus) Register */ 36 37 #define I2CD_FUN_CTRL_REG 0x00 /* I2CD Function Control */ 38 #define I2CD_POOL_PAGE_SEL(x) (((x) >> 20) & 0x7) /* AST2400 */ 39 #define I2CD_M_SDA_LOCK_EN (0x1 << 16) 40 #define I2CD_MULTI_MASTER_DIS (0x1 << 15) 41 #define I2CD_M_SCL_DRIVE_EN (0x1 << 14) 42 #define I2CD_MSB_STS (0x1 << 9) 43 #define I2CD_SDA_DRIVE_1T_EN (0x1 << 8) 44 #define I2CD_M_SDA_DRIVE_1T_EN (0x1 << 7) 45 #define I2CD_M_HIGH_SPEED_EN (0x1 << 6) 46 #define I2CD_DEF_ADDR_EN (0x1 << 5) 47 #define I2CD_DEF_ALERT_EN (0x1 << 4) 48 #define I2CD_DEF_ARP_EN (0x1 << 3) 49 #define I2CD_DEF_GCALL_EN (0x1 << 2) 50 #define I2CD_SLAVE_EN (0x1 << 1) 51 #define I2CD_MASTER_EN (0x1) 52 53 #define I2CD_AC_TIMING_REG1 0x04 /* Clock and AC Timing Control #1 */ 54 #define I2CD_AC_TIMING_REG2 0x08 /* Clock and AC Timing Control #1 */ 55 #define I2CD_INTR_CTRL_REG 0x0c /* I2CD Interrupt Control */ 56 #define I2CD_INTR_STS_REG 0x10 /* I2CD Interrupt Status */ 57 58 #define I2CD_INTR_SLAVE_ADDR_MATCH (0x1 << 31) /* 0: addr1 1: addr2 */ 59 #define I2CD_INTR_SLAVE_ADDR_RX_PENDING (0x1 << 30) 60 /* bits[19-16] Reserved */ 61 62 /* All bits below are cleared by writing 1 */ 63 #define I2CD_INTR_SLAVE_INACTIVE_TIMEOUT (0x1 << 15) 64 #define I2CD_INTR_SDA_DL_TIMEOUT (0x1 << 14) 65 #define I2CD_INTR_BUS_RECOVER_DONE (0x1 << 13) 66 #define I2CD_INTR_SMBUS_ALERT (0x1 << 12) /* Bus [0-3] only */ 67 #define I2CD_INTR_SMBUS_ARP_ADDR (0x1 << 11) /* Removed */ 68 #define I2CD_INTR_SMBUS_DEV_ALERT_ADDR (0x1 << 10) /* Removed */ 69 #define I2CD_INTR_SMBUS_DEF_ADDR (0x1 << 9) /* Removed */ 70 #define I2CD_INTR_GCALL_ADDR (0x1 << 8) /* Removed */ 71 #define I2CD_INTR_SLAVE_ADDR_RX_MATCH (0x1 << 7) /* use RX_DONE */ 72 #define I2CD_INTR_SCL_TIMEOUT (0x1 << 6) 73 #define I2CD_INTR_ABNORMAL (0x1 << 5) 74 #define I2CD_INTR_NORMAL_STOP (0x1 << 4) 75 #define I2CD_INTR_ARBIT_LOSS (0x1 << 3) 76 #define I2CD_INTR_RX_DONE (0x1 << 2) 77 #define I2CD_INTR_TX_NAK (0x1 << 1) 78 #define I2CD_INTR_TX_ACK (0x1 << 0) 79 80 #define I2CD_CMD_REG 0x14 /* I2CD Command/Status */ 81 #define I2CD_SDA_OE (0x1 << 28) 82 #define I2CD_SDA_O (0x1 << 27) 83 #define I2CD_SCL_OE (0x1 << 26) 84 #define I2CD_SCL_O (0x1 << 25) 85 #define I2CD_TX_TIMING (0x1 << 24) 86 #define I2CD_TX_STATUS (0x1 << 23) 87 88 #define I2CD_TX_STATE_SHIFT 19 /* Tx State Machine */ 89 #define I2CD_TX_STATE_MASK 0xf 90 #define I2CD_IDLE 0x0 91 #define I2CD_MACTIVE 0x8 92 #define I2CD_MSTART 0x9 93 #define I2CD_MSTARTR 0xa 94 #define I2CD_MSTOP 0xb 95 #define I2CD_MTXD 0xc 96 #define I2CD_MRXACK 0xd 97 #define I2CD_MRXD 0xe 98 #define I2CD_MTXACK 0xf 99 #define I2CD_SWAIT 0x1 100 #define I2CD_SRXD 0x4 101 #define I2CD_STXACK 0x5 102 #define I2CD_STXD 0x6 103 #define I2CD_SRXACK 0x7 104 #define I2CD_RECOVER 0x3 105 106 #define I2CD_SCL_LINE_STS (0x1 << 18) 107 #define I2CD_SDA_LINE_STS (0x1 << 17) 108 #define I2CD_BUS_BUSY_STS (0x1 << 16) 109 #define I2CD_SDA_OE_OUT_DIR (0x1 << 15) 110 #define I2CD_SDA_O_OUT_DIR (0x1 << 14) 111 #define I2CD_SCL_OE_OUT_DIR (0x1 << 13) 112 #define I2CD_SCL_O_OUT_DIR (0x1 << 12) 113 #define I2CD_BUS_RECOVER_CMD_EN (0x1 << 11) 114 #define I2CD_S_ALT_EN (0x1 << 10) 115 116 /* Command Bit */ 117 #define I2CD_RX_DMA_ENABLE (0x1 << 9) 118 #define I2CD_TX_DMA_ENABLE (0x1 << 8) 119 #define I2CD_RX_BUFF_ENABLE (0x1 << 7) 120 #define I2CD_TX_BUFF_ENABLE (0x1 << 6) 121 #define I2CD_M_STOP_CMD (0x1 << 5) 122 #define I2CD_M_S_RX_CMD_LAST (0x1 << 4) 123 #define I2CD_M_RX_CMD (0x1 << 3) 124 #define I2CD_S_TX_CMD (0x1 << 2) 125 #define I2CD_M_TX_CMD (0x1 << 1) 126 #define I2CD_M_START_CMD (0x1) 127 128 #define I2CD_DEV_ADDR_REG 0x18 /* Slave Device Address */ 129 #define I2CD_POOL_CTRL_REG 0x1c /* Pool Buffer Control */ 130 #define I2CD_POOL_RX_COUNT(x) (((x) >> 24) & 0xff) 131 #define I2CD_POOL_RX_SIZE(x) ((((x) >> 16) & 0xff) + 1) 132 #define I2CD_POOL_TX_COUNT(x) ((((x) >> 8) & 0xff) + 1) 133 #define I2CD_POOL_OFFSET(x) (((x) & 0x3f) << 2) /* AST2400 */ 134 #define I2CD_BYTE_BUF_REG 0x20 /* Transmit/Receive Byte Buffer */ 135 #define I2CD_BYTE_BUF_TX_SHIFT 0 136 #define I2CD_BYTE_BUF_TX_MASK 0xff 137 #define I2CD_BYTE_BUF_RX_SHIFT 8 138 #define I2CD_BYTE_BUF_RX_MASK 0xff 139 140 141 static inline bool aspeed_i2c_bus_is_master(AspeedI2CBus *bus) 142 { 143 return bus->ctrl & I2CD_MASTER_EN; 144 } 145 146 static inline bool aspeed_i2c_bus_is_enabled(AspeedI2CBus *bus) 147 { 148 return bus->ctrl & (I2CD_MASTER_EN | I2CD_SLAVE_EN); 149 } 150 151 static inline void aspeed_i2c_bus_raise_interrupt(AspeedI2CBus *bus) 152 { 153 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 154 155 bus->intr_status &= bus->intr_ctrl; 156 if (bus->intr_status) { 157 bus->controller->intr_status |= 1 << bus->id; 158 qemu_irq_raise(aic->bus_get_irq(bus)); 159 } 160 } 161 162 static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset, 163 unsigned size) 164 { 165 AspeedI2CBus *bus = opaque; 166 167 switch (offset) { 168 case I2CD_FUN_CTRL_REG: 169 return bus->ctrl; 170 case I2CD_AC_TIMING_REG1: 171 return bus->timing[0]; 172 case I2CD_AC_TIMING_REG2: 173 return bus->timing[1]; 174 case I2CD_INTR_CTRL_REG: 175 return bus->intr_ctrl; 176 case I2CD_INTR_STS_REG: 177 return bus->intr_status; 178 case I2CD_POOL_CTRL_REG: 179 return bus->pool_ctrl; 180 case I2CD_BYTE_BUF_REG: 181 return bus->buf; 182 case I2CD_CMD_REG: 183 return bus->cmd | (i2c_bus_busy(bus->bus) << 16); 184 default: 185 qemu_log_mask(LOG_GUEST_ERROR, 186 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset); 187 return -1; 188 } 189 } 190 191 static void aspeed_i2c_set_state(AspeedI2CBus *bus, uint8_t state) 192 { 193 bus->cmd &= ~(I2CD_TX_STATE_MASK << I2CD_TX_STATE_SHIFT); 194 bus->cmd |= (state & I2CD_TX_STATE_MASK) << I2CD_TX_STATE_SHIFT; 195 } 196 197 static uint8_t aspeed_i2c_get_state(AspeedI2CBus *bus) 198 { 199 return (bus->cmd >> I2CD_TX_STATE_SHIFT) & I2CD_TX_STATE_MASK; 200 } 201 202 static int aspeed_i2c_bus_send(AspeedI2CBus *bus, uint8_t pool_start) 203 { 204 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 205 int ret = -1; 206 int i; 207 208 if (bus->cmd & I2CD_TX_BUFF_ENABLE) { 209 for (i = pool_start; i < I2CD_POOL_TX_COUNT(bus->pool_ctrl); i++) { 210 uint8_t *pool_base = aic->bus_pool_base(bus); 211 212 ret = i2c_send(bus->bus, pool_base[i]); 213 if (ret) { 214 break; 215 } 216 } 217 bus->cmd &= ~I2CD_TX_BUFF_ENABLE; 218 } else { 219 ret = i2c_send(bus->bus, bus->buf); 220 } 221 222 return ret; 223 } 224 225 static void aspeed_i2c_bus_recv(AspeedI2CBus *bus) 226 { 227 AspeedI2CState *s = bus->controller; 228 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 229 uint8_t data; 230 int i; 231 232 if (bus->cmd & I2CD_RX_BUFF_ENABLE) { 233 uint8_t *pool_base = aic->bus_pool_base(bus); 234 235 for (i = 0; i < I2CD_POOL_RX_SIZE(bus->pool_ctrl); i++) { 236 pool_base[i] = i2c_recv(bus->bus); 237 } 238 239 /* Update RX count */ 240 bus->pool_ctrl &= ~(0xff << 24); 241 bus->pool_ctrl |= (i & 0xff) << 24; 242 bus->cmd &= ~I2CD_RX_BUFF_ENABLE; 243 } else { 244 data = i2c_recv(bus->bus); 245 bus->buf = (data & I2CD_BYTE_BUF_RX_MASK) << I2CD_BYTE_BUF_RX_SHIFT; 246 } 247 } 248 249 static void aspeed_i2c_handle_rx_cmd(AspeedI2CBus *bus) 250 { 251 aspeed_i2c_set_state(bus, I2CD_MRXD); 252 aspeed_i2c_bus_recv(bus); 253 bus->intr_status |= I2CD_INTR_RX_DONE; 254 if (bus->cmd & I2CD_M_S_RX_CMD_LAST) { 255 i2c_nack(bus->bus); 256 } 257 bus->cmd &= ~(I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST); 258 aspeed_i2c_set_state(bus, I2CD_MACTIVE); 259 } 260 261 static uint8_t aspeed_i2c_get_addr(AspeedI2CBus *bus) 262 { 263 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 264 265 if (bus->cmd & I2CD_TX_BUFF_ENABLE) { 266 uint8_t *pool_base = aic->bus_pool_base(bus); 267 268 return pool_base[0]; 269 } else { 270 return bus->buf; 271 } 272 } 273 274 /* 275 * The state machine needs some refinement. It is only used to track 276 * invalid STOP commands for the moment. 277 */ 278 static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value) 279 { 280 uint8_t pool_start = 0; 281 282 bus->cmd &= ~0xFFFF; 283 bus->cmd |= value & 0xFFFF; 284 285 if (bus->cmd & I2CD_M_START_CMD) { 286 uint8_t state = aspeed_i2c_get_state(bus) & I2CD_MACTIVE ? 287 I2CD_MSTARTR : I2CD_MSTART; 288 uint8_t addr; 289 290 aspeed_i2c_set_state(bus, state); 291 292 addr = aspeed_i2c_get_addr(bus); 293 294 if (i2c_start_transfer(bus->bus, extract32(addr, 1, 7), 295 extract32(addr, 0, 1))) { 296 bus->intr_status |= I2CD_INTR_TX_NAK; 297 } else { 298 bus->intr_status |= I2CD_INTR_TX_ACK; 299 } 300 301 bus->cmd &= ~I2CD_M_START_CMD; 302 303 /* 304 * The START command is also a TX command, as the slave 305 * address is sent on the bus. Drop the TX flag if nothing 306 * else needs to be sent in this sequence. 307 */ 308 if (bus->cmd & I2CD_TX_BUFF_ENABLE) { 309 if (I2CD_POOL_TX_COUNT(bus->pool_ctrl) == 1) { 310 bus->cmd &= ~I2CD_M_TX_CMD; 311 } else { 312 /* 313 * Increase the start index in the TX pool buffer to 314 * skip the address byte. 315 */ 316 pool_start++; 317 } 318 } else { 319 bus->cmd &= ~I2CD_M_TX_CMD; 320 } 321 322 /* No slave found */ 323 if (!i2c_bus_busy(bus->bus)) { 324 return; 325 } 326 aspeed_i2c_set_state(bus, I2CD_MACTIVE); 327 } 328 329 if (bus->cmd & I2CD_M_TX_CMD) { 330 aspeed_i2c_set_state(bus, I2CD_MTXD); 331 if (aspeed_i2c_bus_send(bus, pool_start)) { 332 bus->intr_status |= (I2CD_INTR_TX_NAK); 333 i2c_end_transfer(bus->bus); 334 } else { 335 bus->intr_status |= I2CD_INTR_TX_ACK; 336 } 337 bus->cmd &= ~I2CD_M_TX_CMD; 338 aspeed_i2c_set_state(bus, I2CD_MACTIVE); 339 } 340 341 if ((bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST)) && 342 !(bus->intr_status & I2CD_INTR_RX_DONE)) { 343 aspeed_i2c_handle_rx_cmd(bus); 344 } 345 346 if (bus->cmd & I2CD_M_STOP_CMD) { 347 if (!(aspeed_i2c_get_state(bus) & I2CD_MACTIVE)) { 348 qemu_log_mask(LOG_GUEST_ERROR, "%s: abnormal stop\n", __func__); 349 bus->intr_status |= I2CD_INTR_ABNORMAL; 350 } else { 351 aspeed_i2c_set_state(bus, I2CD_MSTOP); 352 i2c_end_transfer(bus->bus); 353 bus->intr_status |= I2CD_INTR_NORMAL_STOP; 354 } 355 bus->cmd &= ~I2CD_M_STOP_CMD; 356 aspeed_i2c_set_state(bus, I2CD_IDLE); 357 } 358 } 359 360 static void aspeed_i2c_bus_write(void *opaque, hwaddr offset, 361 uint64_t value, unsigned size) 362 { 363 AspeedI2CBus *bus = opaque; 364 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); 365 bool handle_rx; 366 367 switch (offset) { 368 case I2CD_FUN_CTRL_REG: 369 if (value & I2CD_SLAVE_EN) { 370 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n", 371 __func__); 372 break; 373 } 374 bus->ctrl = value & 0x0071C3FF; 375 break; 376 case I2CD_AC_TIMING_REG1: 377 bus->timing[0] = value & 0xFFFFF0F; 378 break; 379 case I2CD_AC_TIMING_REG2: 380 bus->timing[1] = value & 0x7; 381 break; 382 case I2CD_INTR_CTRL_REG: 383 bus->intr_ctrl = value & 0x7FFF; 384 break; 385 case I2CD_INTR_STS_REG: 386 handle_rx = (bus->intr_status & I2CD_INTR_RX_DONE) && 387 (value & I2CD_INTR_RX_DONE); 388 bus->intr_status &= ~(value & 0x7FFF); 389 if (!bus->intr_status) { 390 bus->controller->intr_status &= ~(1 << bus->id); 391 qemu_irq_lower(aic->bus_get_irq(bus)); 392 } 393 if (handle_rx && (bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST))) { 394 aspeed_i2c_handle_rx_cmd(bus); 395 aspeed_i2c_bus_raise_interrupt(bus); 396 } 397 break; 398 case I2CD_DEV_ADDR_REG: 399 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n", 400 __func__); 401 break; 402 case I2CD_POOL_CTRL_REG: 403 bus->pool_ctrl &= ~0xffffff; 404 bus->pool_ctrl |= (value & 0xffffff); 405 break; 406 407 case I2CD_BYTE_BUF_REG: 408 bus->buf = (value & I2CD_BYTE_BUF_TX_MASK) << I2CD_BYTE_BUF_TX_SHIFT; 409 break; 410 case I2CD_CMD_REG: 411 if (!aspeed_i2c_bus_is_enabled(bus)) { 412 break; 413 } 414 415 if (!aspeed_i2c_bus_is_master(bus)) { 416 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n", 417 __func__); 418 break; 419 } 420 421 aspeed_i2c_bus_handle_cmd(bus, value); 422 aspeed_i2c_bus_raise_interrupt(bus); 423 break; 424 425 default: 426 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 427 __func__, offset); 428 } 429 } 430 431 static uint64_t aspeed_i2c_ctrl_read(void *opaque, hwaddr offset, 432 unsigned size) 433 { 434 AspeedI2CState *s = opaque; 435 436 switch (offset) { 437 case I2C_CTRL_STATUS: 438 return s->intr_status; 439 default: 440 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 441 __func__, offset); 442 break; 443 } 444 445 return -1; 446 } 447 448 static void aspeed_i2c_ctrl_write(void *opaque, hwaddr offset, 449 uint64_t value, unsigned size) 450 { 451 switch (offset) { 452 case I2C_CTRL_STATUS: 453 default: 454 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 455 __func__, offset); 456 break; 457 } 458 } 459 460 static const MemoryRegionOps aspeed_i2c_bus_ops = { 461 .read = aspeed_i2c_bus_read, 462 .write = aspeed_i2c_bus_write, 463 .endianness = DEVICE_LITTLE_ENDIAN, 464 }; 465 466 static const MemoryRegionOps aspeed_i2c_ctrl_ops = { 467 .read = aspeed_i2c_ctrl_read, 468 .write = aspeed_i2c_ctrl_write, 469 .endianness = DEVICE_LITTLE_ENDIAN, 470 }; 471 472 static uint64_t aspeed_i2c_pool_read(void *opaque, hwaddr offset, 473 unsigned size) 474 { 475 AspeedI2CState *s = opaque; 476 uint64_t ret = 0; 477 int i; 478 479 for (i = 0; i < size; i++) { 480 ret |= (uint64_t) s->pool[offset + i] << (8 * i); 481 } 482 483 return ret; 484 } 485 486 static void aspeed_i2c_pool_write(void *opaque, hwaddr offset, 487 uint64_t value, unsigned size) 488 { 489 AspeedI2CState *s = opaque; 490 int i; 491 492 for (i = 0; i < size; i++) { 493 s->pool[offset + i] = (value >> (8 * i)) & 0xFF; 494 } 495 } 496 497 static const MemoryRegionOps aspeed_i2c_pool_ops = { 498 .read = aspeed_i2c_pool_read, 499 .write = aspeed_i2c_pool_write, 500 .endianness = DEVICE_LITTLE_ENDIAN, 501 .valid = { 502 .min_access_size = 1, 503 .max_access_size = 4, 504 }, 505 }; 506 507 static const VMStateDescription aspeed_i2c_bus_vmstate = { 508 .name = TYPE_ASPEED_I2C, 509 .version_id = 2, 510 .minimum_version_id = 2, 511 .fields = (VMStateField[]) { 512 VMSTATE_UINT8(id, AspeedI2CBus), 513 VMSTATE_UINT32(ctrl, AspeedI2CBus), 514 VMSTATE_UINT32_ARRAY(timing, AspeedI2CBus, 2), 515 VMSTATE_UINT32(intr_ctrl, AspeedI2CBus), 516 VMSTATE_UINT32(intr_status, AspeedI2CBus), 517 VMSTATE_UINT32(cmd, AspeedI2CBus), 518 VMSTATE_UINT32(buf, AspeedI2CBus), 519 VMSTATE_UINT32(pool_ctrl, AspeedI2CBus), 520 VMSTATE_END_OF_LIST() 521 } 522 }; 523 524 static const VMStateDescription aspeed_i2c_vmstate = { 525 .name = TYPE_ASPEED_I2C, 526 .version_id = 2, 527 .minimum_version_id = 2, 528 .fields = (VMStateField[]) { 529 VMSTATE_UINT32(intr_status, AspeedI2CState), 530 VMSTATE_STRUCT_ARRAY(busses, AspeedI2CState, 531 ASPEED_I2C_NR_BUSSES, 1, aspeed_i2c_bus_vmstate, 532 AspeedI2CBus), 533 VMSTATE_UINT8_ARRAY(pool, AspeedI2CState, ASPEED_I2C_MAX_POOL_SIZE), 534 VMSTATE_END_OF_LIST() 535 } 536 }; 537 538 static void aspeed_i2c_reset(DeviceState *dev) 539 { 540 int i; 541 AspeedI2CState *s = ASPEED_I2C(dev); 542 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 543 544 s->intr_status = 0; 545 546 for (i = 0; i < aic->num_busses; i++) { 547 s->busses[i].intr_ctrl = 0; 548 s->busses[i].intr_status = 0; 549 s->busses[i].cmd = 0; 550 s->busses[i].buf = 0; 551 i2c_end_transfer(s->busses[i].bus); 552 } 553 } 554 555 /* 556 * Address Definitions (AST2400 and AST2500) 557 * 558 * 0x000 ... 0x03F: Global Register 559 * 0x040 ... 0x07F: Device 1 560 * 0x080 ... 0x0BF: Device 2 561 * 0x0C0 ... 0x0FF: Device 3 562 * 0x100 ... 0x13F: Device 4 563 * 0x140 ... 0x17F: Device 5 564 * 0x180 ... 0x1BF: Device 6 565 * 0x1C0 ... 0x1FF: Device 7 566 * 0x200 ... 0x2FF: Buffer Pool (unused in linux driver) 567 * 0x300 ... 0x33F: Device 8 568 * 0x340 ... 0x37F: Device 9 569 * 0x380 ... 0x3BF: Device 10 570 * 0x3C0 ... 0x3FF: Device 11 571 * 0x400 ... 0x43F: Device 12 572 * 0x440 ... 0x47F: Device 13 573 * 0x480 ... 0x4BF: Device 14 574 * 0x800 ... 0xFFF: Buffer Pool (unused in linux driver) 575 */ 576 static void aspeed_i2c_realize(DeviceState *dev, Error **errp) 577 { 578 int i; 579 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 580 AspeedI2CState *s = ASPEED_I2C(dev); 581 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 582 583 sysbus_init_irq(sbd, &s->irq); 584 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_i2c_ctrl_ops, s, 585 "aspeed.i2c", 0x1000); 586 sysbus_init_mmio(sbd, &s->iomem); 587 588 for (i = 0; i < aic->num_busses; i++) { 589 char name[32]; 590 int offset = i < aic->gap ? 1 : 5; 591 592 sysbus_init_irq(sbd, &s->busses[i].irq); 593 snprintf(name, sizeof(name), "aspeed.i2c.%d", i); 594 s->busses[i].controller = s; 595 s->busses[i].id = i; 596 s->busses[i].bus = i2c_init_bus(dev, name); 597 memory_region_init_io(&s->busses[i].mr, OBJECT(dev), 598 &aspeed_i2c_bus_ops, &s->busses[i], name, 599 aic->reg_size); 600 memory_region_add_subregion(&s->iomem, aic->reg_size * (i + offset), 601 &s->busses[i].mr); 602 } 603 604 memory_region_init_io(&s->pool_iomem, OBJECT(s), &aspeed_i2c_pool_ops, s, 605 "aspeed.i2c-pool", aic->pool_size); 606 memory_region_add_subregion(&s->iomem, aic->pool_base, &s->pool_iomem); 607 } 608 609 static void aspeed_i2c_class_init(ObjectClass *klass, void *data) 610 { 611 DeviceClass *dc = DEVICE_CLASS(klass); 612 613 dc->vmsd = &aspeed_i2c_vmstate; 614 dc->reset = aspeed_i2c_reset; 615 dc->realize = aspeed_i2c_realize; 616 dc->desc = "Aspeed I2C Controller"; 617 } 618 619 static const TypeInfo aspeed_i2c_info = { 620 .name = TYPE_ASPEED_I2C, 621 .parent = TYPE_SYS_BUS_DEVICE, 622 .instance_size = sizeof(AspeedI2CState), 623 .class_init = aspeed_i2c_class_init, 624 .class_size = sizeof(AspeedI2CClass), 625 .abstract = true, 626 }; 627 628 static qemu_irq aspeed_2400_i2c_bus_get_irq(AspeedI2CBus *bus) 629 { 630 return bus->controller->irq; 631 } 632 633 static uint8_t *aspeed_2400_i2c_bus_pool_base(AspeedI2CBus *bus) 634 { 635 uint8_t *pool_page = 636 &bus->controller->pool[I2CD_POOL_PAGE_SEL(bus->ctrl) * 0x100]; 637 638 return &pool_page[I2CD_POOL_OFFSET(bus->pool_ctrl)]; 639 } 640 641 static void aspeed_2400_i2c_class_init(ObjectClass *klass, void *data) 642 { 643 DeviceClass *dc = DEVICE_CLASS(klass); 644 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); 645 646 dc->desc = "ASPEED 2400 I2C Controller"; 647 648 aic->num_busses = 14; 649 aic->reg_size = 0x40; 650 aic->gap = 7; 651 aic->bus_get_irq = aspeed_2400_i2c_bus_get_irq; 652 aic->pool_size = 0x800; 653 aic->pool_base = 0x800; 654 aic->bus_pool_base = aspeed_2400_i2c_bus_pool_base; 655 } 656 657 static const TypeInfo aspeed_2400_i2c_info = { 658 .name = TYPE_ASPEED_2400_I2C, 659 .parent = TYPE_ASPEED_I2C, 660 .class_init = aspeed_2400_i2c_class_init, 661 }; 662 663 static qemu_irq aspeed_2500_i2c_bus_get_irq(AspeedI2CBus *bus) 664 { 665 return bus->controller->irq; 666 } 667 668 static uint8_t *aspeed_2500_i2c_bus_pool_base(AspeedI2CBus *bus) 669 { 670 return &bus->controller->pool[bus->id * 0x10]; 671 } 672 673 static void aspeed_2500_i2c_class_init(ObjectClass *klass, void *data) 674 { 675 DeviceClass *dc = DEVICE_CLASS(klass); 676 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); 677 678 dc->desc = "ASPEED 2500 I2C Controller"; 679 680 aic->num_busses = 14; 681 aic->reg_size = 0x40; 682 aic->gap = 7; 683 aic->bus_get_irq = aspeed_2500_i2c_bus_get_irq; 684 aic->pool_size = 0x100; 685 aic->pool_base = 0x200; 686 aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base; 687 } 688 689 static const TypeInfo aspeed_2500_i2c_info = { 690 .name = TYPE_ASPEED_2500_I2C, 691 .parent = TYPE_ASPEED_I2C, 692 .class_init = aspeed_2500_i2c_class_init, 693 }; 694 695 static qemu_irq aspeed_2600_i2c_bus_get_irq(AspeedI2CBus *bus) 696 { 697 return bus->irq; 698 } 699 700 static uint8_t *aspeed_2600_i2c_bus_pool_base(AspeedI2CBus *bus) 701 { 702 return &bus->controller->pool[bus->id * 0x20]; 703 } 704 705 static void aspeed_2600_i2c_class_init(ObjectClass *klass, void *data) 706 { 707 DeviceClass *dc = DEVICE_CLASS(klass); 708 AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass); 709 710 dc->desc = "ASPEED 2600 I2C Controller"; 711 712 aic->num_busses = 16; 713 aic->reg_size = 0x80; 714 aic->gap = -1; /* no gap */ 715 aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq; 716 aic->pool_size = 0x200; 717 aic->pool_base = 0xC00; 718 aic->bus_pool_base = aspeed_2600_i2c_bus_pool_base; 719 } 720 721 static const TypeInfo aspeed_2600_i2c_info = { 722 .name = TYPE_ASPEED_2600_I2C, 723 .parent = TYPE_ASPEED_I2C, 724 .class_init = aspeed_2600_i2c_class_init, 725 }; 726 727 static void aspeed_i2c_register_types(void) 728 { 729 type_register_static(&aspeed_i2c_info); 730 type_register_static(&aspeed_2400_i2c_info); 731 type_register_static(&aspeed_2500_i2c_info); 732 type_register_static(&aspeed_2600_i2c_info); 733 } 734 735 type_init(aspeed_i2c_register_types) 736 737 738 I2CBus *aspeed_i2c_get_bus(DeviceState *dev, int busnr) 739 { 740 AspeedI2CState *s = ASPEED_I2C(dev); 741 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s); 742 I2CBus *bus = NULL; 743 744 if (busnr >= 0 && busnr < aic->num_busses) { 745 bus = s->busses[busnr].bus; 746 } 747 748 return bus; 749 } 750