1 /* 2 * QEMU INTEL 82574 GbE NIC emulation 3 * 4 * Software developer's manuals: 5 * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf 6 * 7 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com) 8 * Developed by Daynix Computing LTD (http://www.daynix.com) 9 * 10 * Authors: 11 * Dmitry Fleytman <dmitry@daynix.com> 12 * Leonid Bloch <leonid@daynix.com> 13 * Yan Vugenfirer <yan@daynix.com> 14 * 15 * Based on work done by: 16 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. 17 * Copyright (c) 2008 Qumranet 18 * Based on work done by: 19 * Copyright (c) 2007 Dan Aloni 20 * Copyright (c) 2004 Antony T Curtis 21 * 22 * This library is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU Lesser General Public 24 * License as published by the Free Software Foundation; either 25 * version 2 of the License, or (at your option) any later version. 26 * 27 * This library is distributed in the hope that it will be useful, 28 * but WITHOUT ANY WARRANTY; without even the implied warranty of 29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 * Lesser General Public License for more details. 31 * 32 * You should have received a copy of the GNU Lesser General Public 33 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 34 */ 35 36 #include "qemu/osdep.h" 37 #include "qemu/units.h" 38 #include "net/net.h" 39 #include "net/tap.h" 40 #include "qemu/module.h" 41 #include "qemu/range.h" 42 #include "sysemu/sysemu.h" 43 #include "hw/pci/msi.h" 44 #include "hw/pci/msix.h" 45 #include "migration/vmstate.h" 46 47 #include "e1000_regs.h" 48 49 #include "e1000x_common.h" 50 #include "e1000e_core.h" 51 52 #include "trace.h" 53 #include "qapi/error.h" 54 55 #define TYPE_E1000E "e1000e" 56 #define E1000E(obj) OBJECT_CHECK(E1000EState, (obj), TYPE_E1000E) 57 58 typedef struct E1000EState { 59 PCIDevice parent_obj; 60 NICState *nic; 61 NICConf conf; 62 63 MemoryRegion mmio; 64 MemoryRegion flash; 65 MemoryRegion io; 66 MemoryRegion msix; 67 68 uint32_t ioaddr; 69 70 uint16_t subsys_ven; 71 uint16_t subsys; 72 73 uint16_t subsys_ven_used; 74 uint16_t subsys_used; 75 76 bool disable_vnet; 77 78 E1000ECore core; 79 80 } E1000EState; 81 82 #define E1000E_MMIO_IDX 0 83 #define E1000E_FLASH_IDX 1 84 #define E1000E_IO_IDX 2 85 #define E1000E_MSIX_IDX 3 86 87 #define E1000E_MMIO_SIZE (128 * KiB) 88 #define E1000E_FLASH_SIZE (128 * KiB) 89 #define E1000E_IO_SIZE (32) 90 #define E1000E_MSIX_SIZE (16 * KiB) 91 92 #define E1000E_MSIX_TABLE (0x0000) 93 #define E1000E_MSIX_PBA (0x2000) 94 95 static uint64_t 96 e1000e_mmio_read(void *opaque, hwaddr addr, unsigned size) 97 { 98 E1000EState *s = opaque; 99 return e1000e_core_read(&s->core, addr, size); 100 } 101 102 static void 103 e1000e_mmio_write(void *opaque, hwaddr addr, 104 uint64_t val, unsigned size) 105 { 106 E1000EState *s = opaque; 107 e1000e_core_write(&s->core, addr, val, size); 108 } 109 110 static bool 111 e1000e_io_get_reg_index(E1000EState *s, uint32_t *idx) 112 { 113 if (s->ioaddr < 0x1FFFF) { 114 *idx = s->ioaddr; 115 return true; 116 } 117 118 if (s->ioaddr < 0x7FFFF) { 119 trace_e1000e_wrn_io_addr_undefined(s->ioaddr); 120 return false; 121 } 122 123 if (s->ioaddr < 0xFFFFF) { 124 trace_e1000e_wrn_io_addr_flash(s->ioaddr); 125 return false; 126 } 127 128 trace_e1000e_wrn_io_addr_unknown(s->ioaddr); 129 return false; 130 } 131 132 static uint64_t 133 e1000e_io_read(void *opaque, hwaddr addr, unsigned size) 134 { 135 E1000EState *s = opaque; 136 uint32_t idx = 0; 137 uint64_t val; 138 139 switch (addr) { 140 case E1000_IOADDR: 141 trace_e1000e_io_read_addr(s->ioaddr); 142 return s->ioaddr; 143 case E1000_IODATA: 144 if (e1000e_io_get_reg_index(s, &idx)) { 145 val = e1000e_core_read(&s->core, idx, sizeof(val)); 146 trace_e1000e_io_read_data(idx, val); 147 return val; 148 } 149 return 0; 150 default: 151 trace_e1000e_wrn_io_read_unknown(addr); 152 return 0; 153 } 154 } 155 156 static void 157 e1000e_io_write(void *opaque, hwaddr addr, 158 uint64_t val, unsigned size) 159 { 160 E1000EState *s = opaque; 161 uint32_t idx = 0; 162 163 switch (addr) { 164 case E1000_IOADDR: 165 trace_e1000e_io_write_addr(val); 166 s->ioaddr = (uint32_t) val; 167 return; 168 case E1000_IODATA: 169 if (e1000e_io_get_reg_index(s, &idx)) { 170 trace_e1000e_io_write_data(idx, val); 171 e1000e_core_write(&s->core, idx, val, sizeof(val)); 172 } 173 return; 174 default: 175 trace_e1000e_wrn_io_write_unknown(addr); 176 return; 177 } 178 } 179 180 static const MemoryRegionOps mmio_ops = { 181 .read = e1000e_mmio_read, 182 .write = e1000e_mmio_write, 183 .endianness = DEVICE_LITTLE_ENDIAN, 184 .impl = { 185 .min_access_size = 4, 186 .max_access_size = 4, 187 }, 188 }; 189 190 static const MemoryRegionOps io_ops = { 191 .read = e1000e_io_read, 192 .write = e1000e_io_write, 193 .endianness = DEVICE_LITTLE_ENDIAN, 194 .impl = { 195 .min_access_size = 4, 196 .max_access_size = 4, 197 }, 198 }; 199 200 static int 201 e1000e_nc_can_receive(NetClientState *nc) 202 { 203 E1000EState *s = qemu_get_nic_opaque(nc); 204 return e1000e_can_receive(&s->core); 205 } 206 207 static ssize_t 208 e1000e_nc_receive_iov(NetClientState *nc, const struct iovec *iov, int iovcnt) 209 { 210 E1000EState *s = qemu_get_nic_opaque(nc); 211 return e1000e_receive_iov(&s->core, iov, iovcnt); 212 } 213 214 static ssize_t 215 e1000e_nc_receive(NetClientState *nc, const uint8_t *buf, size_t size) 216 { 217 E1000EState *s = qemu_get_nic_opaque(nc); 218 return e1000e_receive(&s->core, buf, size); 219 } 220 221 static void 222 e1000e_set_link_status(NetClientState *nc) 223 { 224 E1000EState *s = qemu_get_nic_opaque(nc); 225 e1000e_core_set_link_status(&s->core); 226 } 227 228 static NetClientInfo net_e1000e_info = { 229 .type = NET_CLIENT_DRIVER_NIC, 230 .size = sizeof(NICState), 231 .can_receive = e1000e_nc_can_receive, 232 .receive = e1000e_nc_receive, 233 .receive_iov = e1000e_nc_receive_iov, 234 .link_status_changed = e1000e_set_link_status, 235 }; 236 237 /* 238 * EEPROM (NVM) contents documented in Table 36, section 6.1 239 * and generally 6.1.2 Software accessed words. 240 */ 241 static const uint16_t e1000e_eeprom_template[64] = { 242 /* Address | Compat. | ImVer | Compat. */ 243 0x0000, 0x0000, 0x0000, 0x0420, 0xf746, 0x2010, 0xffff, 0xffff, 244 /* PBA |ICtrl1 | SSID | SVID | DevID |-------|ICtrl2 */ 245 0x0000, 0x0000, 0x026b, 0x0000, 0x8086, 0x0000, 0x0000, 0x8058, 246 /* NVM words 1,2,3 |-------------------------------|PCI-EID*/ 247 0x0000, 0x2001, 0x7e7c, 0xffff, 0x1000, 0x00c8, 0x0000, 0x2704, 248 /* PCIe Init. Conf 1,2,3 |PCICtrl|PHY|LD1|-------| RevID | LD0,2 */ 249 0x6cc9, 0x3150, 0x070e, 0x460b, 0x2d84, 0x0100, 0xf000, 0x0706, 250 /* FLPAR |FLANADD|LAN-PWR|FlVndr |ICtrl3 |APTSMBA|APTRxEP|APTSMBC*/ 251 0x6000, 0x0080, 0x0f04, 0x7fff, 0x4f01, 0xc600, 0x0000, 0x20ff, 252 /* APTIF | APTMC |APTuCP |LSWFWID|MSWFWID|NC-SIMC|NC-SIC | VPDP */ 253 0x0028, 0x0003, 0x0000, 0x0000, 0x0000, 0x0003, 0x0000, 0xffff, 254 /* SW Section */ 255 0x0100, 0xc000, 0x121c, 0xc007, 0xffff, 0xffff, 0xffff, 0xffff, 256 /* SW Section |CHKSUM */ 257 0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0x0120, 0xffff, 0x0000, 258 }; 259 260 static void e1000e_core_realize(E1000EState *s) 261 { 262 s->core.owner = &s->parent_obj; 263 s->core.owner_nic = s->nic; 264 } 265 266 static void 267 e1000e_unuse_msix_vectors(E1000EState *s, int num_vectors) 268 { 269 int i; 270 for (i = 0; i < num_vectors; i++) { 271 msix_vector_unuse(PCI_DEVICE(s), i); 272 } 273 } 274 275 static bool 276 e1000e_use_msix_vectors(E1000EState *s, int num_vectors) 277 { 278 int i; 279 for (i = 0; i < num_vectors; i++) { 280 int res = msix_vector_use(PCI_DEVICE(s), i); 281 if (res < 0) { 282 trace_e1000e_msix_use_vector_fail(i, res); 283 e1000e_unuse_msix_vectors(s, i); 284 return false; 285 } 286 } 287 return true; 288 } 289 290 static void 291 e1000e_init_msix(E1000EState *s) 292 { 293 PCIDevice *d = PCI_DEVICE(s); 294 int res = msix_init(PCI_DEVICE(s), E1000E_MSIX_VEC_NUM, 295 &s->msix, 296 E1000E_MSIX_IDX, E1000E_MSIX_TABLE, 297 &s->msix, 298 E1000E_MSIX_IDX, E1000E_MSIX_PBA, 299 0xA0, NULL); 300 301 if (res < 0) { 302 trace_e1000e_msix_init_fail(res); 303 } else { 304 if (!e1000e_use_msix_vectors(s, E1000E_MSIX_VEC_NUM)) { 305 msix_uninit(d, &s->msix, &s->msix); 306 } 307 } 308 } 309 310 static void 311 e1000e_cleanup_msix(E1000EState *s) 312 { 313 if (msix_present(PCI_DEVICE(s))) { 314 e1000e_unuse_msix_vectors(s, E1000E_MSIX_VEC_NUM); 315 msix_uninit(PCI_DEVICE(s), &s->msix, &s->msix); 316 } 317 } 318 319 static void 320 e1000e_init_net_peer(E1000EState *s, PCIDevice *pci_dev, uint8_t *macaddr) 321 { 322 DeviceState *dev = DEVICE(pci_dev); 323 NetClientState *nc; 324 int i; 325 326 s->nic = qemu_new_nic(&net_e1000e_info, &s->conf, 327 object_get_typename(OBJECT(s)), dev->id, s); 328 329 s->core.max_queue_num = s->conf.peers.queues - 1; 330 331 trace_e1000e_mac_set_permanent(MAC_ARG(macaddr)); 332 memcpy(s->core.permanent_mac, macaddr, sizeof(s->core.permanent_mac)); 333 334 qemu_format_nic_info_str(qemu_get_queue(s->nic), macaddr); 335 336 /* Setup virtio headers */ 337 if (s->disable_vnet) { 338 s->core.has_vnet = false; 339 trace_e1000e_cfg_support_virtio(false); 340 return; 341 } else { 342 s->core.has_vnet = true; 343 } 344 345 for (i = 0; i < s->conf.peers.queues; i++) { 346 nc = qemu_get_subqueue(s->nic, i); 347 if (!nc->peer || !qemu_has_vnet_hdr(nc->peer)) { 348 s->core.has_vnet = false; 349 trace_e1000e_cfg_support_virtio(false); 350 return; 351 } 352 } 353 354 trace_e1000e_cfg_support_virtio(true); 355 356 for (i = 0; i < s->conf.peers.queues; i++) { 357 nc = qemu_get_subqueue(s->nic, i); 358 qemu_set_vnet_hdr_len(nc->peer, sizeof(struct virtio_net_hdr)); 359 qemu_using_vnet_hdr(nc->peer, true); 360 } 361 } 362 363 static inline uint64_t 364 e1000e_gen_dsn(uint8_t *mac) 365 { 366 return (uint64_t)(mac[5]) | 367 (uint64_t)(mac[4]) << 8 | 368 (uint64_t)(mac[3]) << 16 | 369 (uint64_t)(0x00FF) << 24 | 370 (uint64_t)(0x00FF) << 32 | 371 (uint64_t)(mac[2]) << 40 | 372 (uint64_t)(mac[1]) << 48 | 373 (uint64_t)(mac[0]) << 56; 374 } 375 376 static int 377 e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc) 378 { 379 Error *local_err = NULL; 380 int ret = pci_add_capability(pdev, PCI_CAP_ID_PM, offset, 381 PCI_PM_SIZEOF, &local_err); 382 383 if (local_err) { 384 error_report_err(local_err); 385 return ret; 386 } 387 388 pci_set_word(pdev->config + offset + PCI_PM_PMC, 389 PCI_PM_CAP_VER_1_1 | 390 pmc); 391 392 pci_set_word(pdev->wmask + offset + PCI_PM_CTRL, 393 PCI_PM_CTRL_STATE_MASK | 394 PCI_PM_CTRL_PME_ENABLE | 395 PCI_PM_CTRL_DATA_SEL_MASK); 396 397 pci_set_word(pdev->w1cmask + offset + PCI_PM_CTRL, 398 PCI_PM_CTRL_PME_STATUS); 399 400 return ret; 401 } 402 403 static void e1000e_write_config(PCIDevice *pci_dev, uint32_t address, 404 uint32_t val, int len) 405 { 406 E1000EState *s = E1000E(pci_dev); 407 408 pci_default_write_config(pci_dev, address, val, len); 409 410 if (range_covers_byte(address, len, PCI_COMMAND) && 411 (pci_dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) { 412 e1000e_start_recv(&s->core); 413 } 414 } 415 416 static void e1000e_pci_realize(PCIDevice *pci_dev, Error **errp) 417 { 418 static const uint16_t e1000e_pmrb_offset = 0x0C8; 419 static const uint16_t e1000e_pcie_offset = 0x0E0; 420 static const uint16_t e1000e_aer_offset = 0x100; 421 static const uint16_t e1000e_dsn_offset = 0x140; 422 E1000EState *s = E1000E(pci_dev); 423 uint8_t *macaddr; 424 int ret; 425 426 trace_e1000e_cb_pci_realize(); 427 428 pci_dev->config_write = e1000e_write_config; 429 430 pci_dev->config[PCI_CACHE_LINE_SIZE] = 0x10; 431 pci_dev->config[PCI_INTERRUPT_PIN] = 1; 432 433 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, s->subsys_ven); 434 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, s->subsys); 435 436 s->subsys_ven_used = s->subsys_ven; 437 s->subsys_used = s->subsys; 438 439 /* Define IO/MMIO regions */ 440 memory_region_init_io(&s->mmio, OBJECT(s), &mmio_ops, s, 441 "e1000e-mmio", E1000E_MMIO_SIZE); 442 pci_register_bar(pci_dev, E1000E_MMIO_IDX, 443 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio); 444 445 /* 446 * We provide a dummy implementation for the flash BAR 447 * for drivers that may theoretically probe for its presence. 448 */ 449 memory_region_init(&s->flash, OBJECT(s), 450 "e1000e-flash", E1000E_FLASH_SIZE); 451 pci_register_bar(pci_dev, E1000E_FLASH_IDX, 452 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->flash); 453 454 memory_region_init_io(&s->io, OBJECT(s), &io_ops, s, 455 "e1000e-io", E1000E_IO_SIZE); 456 pci_register_bar(pci_dev, E1000E_IO_IDX, 457 PCI_BASE_ADDRESS_SPACE_IO, &s->io); 458 459 memory_region_init(&s->msix, OBJECT(s), "e1000e-msix", 460 E1000E_MSIX_SIZE); 461 pci_register_bar(pci_dev, E1000E_MSIX_IDX, 462 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix); 463 464 /* Create networking backend */ 465 qemu_macaddr_default_if_unset(&s->conf.macaddr); 466 macaddr = s->conf.macaddr.a; 467 468 e1000e_init_msix(s); 469 470 if (pcie_endpoint_cap_v1_init(pci_dev, e1000e_pcie_offset) < 0) { 471 hw_error("Failed to initialize PCIe capability"); 472 } 473 474 ret = msi_init(PCI_DEVICE(s), 0xD0, 1, true, false, NULL); 475 if (ret) { 476 trace_e1000e_msi_init_fail(ret); 477 } 478 479 if (e1000e_add_pm_capability(pci_dev, e1000e_pmrb_offset, 480 PCI_PM_CAP_DSI) < 0) { 481 hw_error("Failed to initialize PM capability"); 482 } 483 484 if (pcie_aer_init(pci_dev, PCI_ERR_VER, e1000e_aer_offset, 485 PCI_ERR_SIZEOF, NULL) < 0) { 486 hw_error("Failed to initialize AER capability"); 487 } 488 489 pcie_dev_ser_num_init(pci_dev, e1000e_dsn_offset, 490 e1000e_gen_dsn(macaddr)); 491 492 e1000e_init_net_peer(s, pci_dev, macaddr); 493 494 /* Initialize core */ 495 e1000e_core_realize(s); 496 497 e1000e_core_pci_realize(&s->core, 498 e1000e_eeprom_template, 499 sizeof(e1000e_eeprom_template), 500 macaddr); 501 } 502 503 static void e1000e_pci_uninit(PCIDevice *pci_dev) 504 { 505 E1000EState *s = E1000E(pci_dev); 506 507 trace_e1000e_cb_pci_uninit(); 508 509 e1000e_core_pci_uninit(&s->core); 510 511 pcie_aer_exit(pci_dev); 512 pcie_cap_exit(pci_dev); 513 514 qemu_del_nic(s->nic); 515 516 e1000e_cleanup_msix(s); 517 msi_uninit(pci_dev); 518 } 519 520 static void e1000e_qdev_reset(DeviceState *dev) 521 { 522 E1000EState *s = E1000E(dev); 523 524 trace_e1000e_cb_qdev_reset(); 525 526 e1000e_core_reset(&s->core); 527 } 528 529 static int e1000e_pre_save(void *opaque) 530 { 531 E1000EState *s = opaque; 532 533 trace_e1000e_cb_pre_save(); 534 535 e1000e_core_pre_save(&s->core); 536 537 return 0; 538 } 539 540 static int e1000e_post_load(void *opaque, int version_id) 541 { 542 E1000EState *s = opaque; 543 544 trace_e1000e_cb_post_load(); 545 546 if ((s->subsys != s->subsys_used) || 547 (s->subsys_ven != s->subsys_ven_used)) { 548 fprintf(stderr, 549 "ERROR: Cannot migrate while device properties " 550 "(subsys/subsys_ven) differ"); 551 return -1; 552 } 553 554 return e1000e_core_post_load(&s->core); 555 } 556 557 static const VMStateDescription e1000e_vmstate_tx = { 558 .name = "e1000e-tx", 559 .version_id = 1, 560 .minimum_version_id = 1, 561 .fields = (VMStateField[]) { 562 VMSTATE_UINT8(sum_needed, struct e1000e_tx), 563 VMSTATE_UINT8(props.ipcss, struct e1000e_tx), 564 VMSTATE_UINT8(props.ipcso, struct e1000e_tx), 565 VMSTATE_UINT16(props.ipcse, struct e1000e_tx), 566 VMSTATE_UINT8(props.tucss, struct e1000e_tx), 567 VMSTATE_UINT8(props.tucso, struct e1000e_tx), 568 VMSTATE_UINT16(props.tucse, struct e1000e_tx), 569 VMSTATE_UINT8(props.hdr_len, struct e1000e_tx), 570 VMSTATE_UINT16(props.mss, struct e1000e_tx), 571 VMSTATE_UINT32(props.paylen, struct e1000e_tx), 572 VMSTATE_INT8(props.ip, struct e1000e_tx), 573 VMSTATE_INT8(props.tcp, struct e1000e_tx), 574 VMSTATE_BOOL(props.tse, struct e1000e_tx), 575 VMSTATE_BOOL(cptse, struct e1000e_tx), 576 VMSTATE_BOOL(skip_cp, struct e1000e_tx), 577 VMSTATE_END_OF_LIST() 578 } 579 }; 580 581 static const VMStateDescription e1000e_vmstate_intr_timer = { 582 .name = "e1000e-intr-timer", 583 .version_id = 1, 584 .minimum_version_id = 1, 585 .fields = (VMStateField[]) { 586 VMSTATE_TIMER_PTR(timer, E1000IntrDelayTimer), 587 VMSTATE_BOOL(running, E1000IntrDelayTimer), 588 VMSTATE_END_OF_LIST() 589 } 590 }; 591 592 #define VMSTATE_E1000E_INTR_DELAY_TIMER(_f, _s) \ 593 VMSTATE_STRUCT(_f, _s, 0, \ 594 e1000e_vmstate_intr_timer, E1000IntrDelayTimer) 595 596 #define VMSTATE_E1000E_INTR_DELAY_TIMER_ARRAY(_f, _s, _num) \ 597 VMSTATE_STRUCT_ARRAY(_f, _s, _num, 0, \ 598 e1000e_vmstate_intr_timer, E1000IntrDelayTimer) 599 600 static const VMStateDescription e1000e_vmstate = { 601 .name = "e1000e", 602 .version_id = 1, 603 .minimum_version_id = 1, 604 .pre_save = e1000e_pre_save, 605 .post_load = e1000e_post_load, 606 .fields = (VMStateField[]) { 607 VMSTATE_PCI_DEVICE(parent_obj, E1000EState), 608 VMSTATE_MSIX(parent_obj, E1000EState), 609 610 VMSTATE_UINT32(ioaddr, E1000EState), 611 VMSTATE_UINT32(core.rxbuf_min_shift, E1000EState), 612 VMSTATE_UINT8(core.rx_desc_len, E1000EState), 613 VMSTATE_UINT32_ARRAY(core.rxbuf_sizes, E1000EState, 614 E1000_PSRCTL_BUFFS_PER_DESC), 615 VMSTATE_UINT32(core.rx_desc_buf_size, E1000EState), 616 VMSTATE_UINT16_ARRAY(core.eeprom, E1000EState, E1000E_EEPROM_SIZE), 617 VMSTATE_UINT16_2DARRAY(core.phy, E1000EState, 618 E1000E_PHY_PAGES, E1000E_PHY_PAGE_SIZE), 619 VMSTATE_UINT32_ARRAY(core.mac, E1000EState, E1000E_MAC_SIZE), 620 VMSTATE_UINT8_ARRAY(core.permanent_mac, E1000EState, ETH_ALEN), 621 622 VMSTATE_UINT32(core.delayed_causes, E1000EState), 623 624 VMSTATE_UINT16(subsys, E1000EState), 625 VMSTATE_UINT16(subsys_ven, E1000EState), 626 627 VMSTATE_E1000E_INTR_DELAY_TIMER(core.rdtr, E1000EState), 628 VMSTATE_E1000E_INTR_DELAY_TIMER(core.radv, E1000EState), 629 VMSTATE_E1000E_INTR_DELAY_TIMER(core.raid, E1000EState), 630 VMSTATE_E1000E_INTR_DELAY_TIMER(core.tadv, E1000EState), 631 VMSTATE_E1000E_INTR_DELAY_TIMER(core.tidv, E1000EState), 632 633 VMSTATE_E1000E_INTR_DELAY_TIMER(core.itr, E1000EState), 634 VMSTATE_BOOL(core.itr_intr_pending, E1000EState), 635 636 VMSTATE_E1000E_INTR_DELAY_TIMER_ARRAY(core.eitr, E1000EState, 637 E1000E_MSIX_VEC_NUM), 638 VMSTATE_BOOL_ARRAY(core.eitr_intr_pending, E1000EState, 639 E1000E_MSIX_VEC_NUM), 640 641 VMSTATE_UINT32(core.itr_guest_value, E1000EState), 642 VMSTATE_UINT32_ARRAY(core.eitr_guest_value, E1000EState, 643 E1000E_MSIX_VEC_NUM), 644 645 VMSTATE_UINT16(core.vet, E1000EState), 646 647 VMSTATE_STRUCT_ARRAY(core.tx, E1000EState, E1000E_NUM_QUEUES, 0, 648 e1000e_vmstate_tx, struct e1000e_tx), 649 VMSTATE_END_OF_LIST() 650 } 651 }; 652 653 static PropertyInfo e1000e_prop_disable_vnet, 654 e1000e_prop_subsys_ven, 655 e1000e_prop_subsys; 656 657 static Property e1000e_properties[] = { 658 DEFINE_NIC_PROPERTIES(E1000EState, conf), 659 DEFINE_PROP_SIGNED("disable_vnet_hdr", E1000EState, disable_vnet, false, 660 e1000e_prop_disable_vnet, bool), 661 DEFINE_PROP_SIGNED("subsys_ven", E1000EState, subsys_ven, 662 PCI_VENDOR_ID_INTEL, 663 e1000e_prop_subsys_ven, uint16_t), 664 DEFINE_PROP_SIGNED("subsys", E1000EState, subsys, 0, 665 e1000e_prop_subsys, uint16_t), 666 DEFINE_PROP_END_OF_LIST(), 667 }; 668 669 static void e1000e_class_init(ObjectClass *class, void *data) 670 { 671 DeviceClass *dc = DEVICE_CLASS(class); 672 PCIDeviceClass *c = PCI_DEVICE_CLASS(class); 673 674 c->realize = e1000e_pci_realize; 675 c->exit = e1000e_pci_uninit; 676 c->vendor_id = PCI_VENDOR_ID_INTEL; 677 c->device_id = E1000_DEV_ID_82574L; 678 c->revision = 0; 679 c->romfile = "efi-e1000e.rom"; 680 c->class_id = PCI_CLASS_NETWORK_ETHERNET; 681 682 dc->desc = "Intel 82574L GbE Controller"; 683 dc->reset = e1000e_qdev_reset; 684 dc->vmsd = &e1000e_vmstate; 685 dc->props = e1000e_properties; 686 687 e1000e_prop_disable_vnet = qdev_prop_uint8; 688 e1000e_prop_disable_vnet.description = "Do not use virtio headers, " 689 "perform SW offloads emulation " 690 "instead"; 691 692 e1000e_prop_subsys_ven = qdev_prop_uint16; 693 e1000e_prop_subsys_ven.description = "PCI device Subsystem Vendor ID"; 694 695 e1000e_prop_subsys = qdev_prop_uint16; 696 e1000e_prop_subsys.description = "PCI device Subsystem ID"; 697 698 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 699 } 700 701 static void e1000e_instance_init(Object *obj) 702 { 703 E1000EState *s = E1000E(obj); 704 device_add_bootindex_property(obj, &s->conf.bootindex, 705 "bootindex", "/ethernet-phy@0", 706 DEVICE(obj), NULL); 707 } 708 709 static const TypeInfo e1000e_info = { 710 .name = TYPE_E1000E, 711 .parent = TYPE_PCI_DEVICE, 712 .instance_size = sizeof(E1000EState), 713 .class_init = e1000e_class_init, 714 .instance_init = e1000e_instance_init, 715 .interfaces = (InterfaceInfo[]) { 716 { INTERFACE_PCIE_DEVICE }, 717 { } 718 }, 719 }; 720 721 static void e1000e_register_types(void) 722 { 723 type_register_static(&e1000e_info); 724 } 725 726 type_init(e1000e_register_types) 727