1 /* 2 * QEMU SMBus EEPROM device 3 * 4 * Copyright (c) 2007 Arastra, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "hw/hw.h" 29 #include "hw/i2c/i2c.h" 30 #include "hw/i2c/smbus_slave.h" 31 #include "hw/i2c/smbus_eeprom.h" 32 33 //#define DEBUG 34 35 typedef struct SMBusEEPROMDevice { 36 SMBusDevice smbusdev; 37 void *data; 38 uint8_t offset; 39 } SMBusEEPROMDevice; 40 41 static void eeprom_quick_cmd(SMBusDevice *dev, uint8_t read) 42 { 43 #ifdef DEBUG 44 printf("eeprom_quick_cmd: addr=0x%02x read=%d\n", dev->i2c.address, read); 45 #endif 46 } 47 48 static uint8_t eeprom_receive_byte(SMBusDevice *dev) 49 { 50 SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev; 51 uint8_t *data = eeprom->data; 52 uint8_t val = data[eeprom->offset++]; 53 #ifdef DEBUG 54 printf("eeprom_receive_byte: addr=0x%02x val=0x%02x\n", 55 dev->i2c.address, val); 56 #endif 57 return val; 58 } 59 60 static int eeprom_write_data(SMBusDevice *dev, uint8_t *buf, uint8_t len) 61 { 62 SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev; 63 uint8_t *data = eeprom->data; 64 65 #ifdef DEBUG 66 printf("eeprom_write_byte: addr=0x%02x cmd=0x%02x val=0x%02x\n", 67 dev->i2c.address, buf[0], buf[1]); 68 #endif 69 /* len is guaranteed to be > 0 */ 70 eeprom->offset = buf[0]; 71 buf++; 72 len--; 73 74 for (; len > 0; len--) { 75 data[eeprom->offset] = *buf++; 76 eeprom->offset = (eeprom->offset + 1) % 256; 77 } 78 79 return 0; 80 } 81 82 static void smbus_eeprom_realize(DeviceState *dev, Error **errp) 83 { 84 SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *)dev; 85 86 eeprom->offset = 0; 87 } 88 89 static Property smbus_eeprom_properties[] = { 90 DEFINE_PROP_PTR("data", SMBusEEPROMDevice, data), 91 DEFINE_PROP_END_OF_LIST(), 92 }; 93 94 static void smbus_eeprom_class_initfn(ObjectClass *klass, void *data) 95 { 96 DeviceClass *dc = DEVICE_CLASS(klass); 97 SMBusDeviceClass *sc = SMBUS_DEVICE_CLASS(klass); 98 99 dc->realize = smbus_eeprom_realize; 100 sc->quick_cmd = eeprom_quick_cmd; 101 sc->receive_byte = eeprom_receive_byte; 102 sc->write_data = eeprom_write_data; 103 dc->props = smbus_eeprom_properties; 104 /* Reason: pointer property "data" */ 105 dc->user_creatable = false; 106 } 107 108 static const TypeInfo smbus_eeprom_info = { 109 .name = "smbus-eeprom", 110 .parent = TYPE_SMBUS_DEVICE, 111 .instance_size = sizeof(SMBusEEPROMDevice), 112 .class_init = smbus_eeprom_class_initfn, 113 }; 114 115 static void smbus_eeprom_register_types(void) 116 { 117 type_register_static(&smbus_eeprom_info); 118 } 119 120 type_init(smbus_eeprom_register_types) 121 122 void smbus_eeprom_init_one(I2CBus *smbus, uint8_t address, uint8_t *eeprom_buf) 123 { 124 DeviceState *dev; 125 126 dev = qdev_create((BusState *) smbus, "smbus-eeprom"); 127 qdev_prop_set_uint8(dev, "address", address); 128 qdev_prop_set_ptr(dev, "data", eeprom_buf); 129 qdev_init_nofail(dev); 130 } 131 132 void smbus_eeprom_init(I2CBus *smbus, int nb_eeprom, 133 const uint8_t *eeprom_spd, int eeprom_spd_size) 134 { 135 int i; 136 uint8_t *eeprom_buf = g_malloc0(8 * 256); /* XXX: make this persistent */ 137 if (eeprom_spd_size > 0) { 138 memcpy(eeprom_buf, eeprom_spd, eeprom_spd_size); 139 } 140 141 for (i = 0; i < nb_eeprom; i++) { 142 smbus_eeprom_init_one(smbus, 0x50 + i, eeprom_buf + (i * 256)); 143 } 144 } 145 146 /* Generate SDRAM SPD EEPROM data describing a module of type and size */ 147 uint8_t *spd_data_generate(enum sdram_type type, ram_addr_t ram_size, 148 Error **errp) 149 { 150 uint8_t *spd; 151 uint8_t nbanks; 152 uint16_t density; 153 uint32_t size; 154 int min_log2, max_log2, sz_log2; 155 int i; 156 157 switch (type) { 158 case SDR: 159 min_log2 = 2; 160 max_log2 = 9; 161 break; 162 case DDR: 163 min_log2 = 5; 164 max_log2 = 12; 165 break; 166 case DDR2: 167 min_log2 = 7; 168 max_log2 = 14; 169 break; 170 default: 171 g_assert_not_reached(); 172 } 173 size = ram_size >> 20; /* work in terms of megabytes */ 174 if (size < 4) { 175 error_setg(errp, "SDRAM size is too small"); 176 return NULL; 177 } 178 sz_log2 = 31 - clz32(size); 179 size = 1U << sz_log2; 180 if (ram_size > size * MiB) { 181 error_setg(errp, "SDRAM size 0x"RAM_ADDR_FMT" is not a power of 2, " 182 "truncating to %u MB", ram_size, size); 183 } 184 if (sz_log2 < min_log2) { 185 error_setg(errp, 186 "Memory size is too small for SDRAM type, adjusting type"); 187 if (size >= 32) { 188 type = DDR; 189 min_log2 = 5; 190 max_log2 = 12; 191 } else { 192 type = SDR; 193 min_log2 = 2; 194 max_log2 = 9; 195 } 196 } 197 198 nbanks = 1; 199 while (sz_log2 > max_log2 && nbanks < 8) { 200 sz_log2--; 201 nbanks++; 202 } 203 204 if (size > (1ULL << sz_log2) * nbanks) { 205 error_setg(errp, "Memory size is too big for SDRAM, truncating"); 206 } 207 208 /* split to 2 banks if possible to avoid a bug in MIPS Malta firmware */ 209 if (nbanks == 1 && sz_log2 > min_log2) { 210 sz_log2--; 211 nbanks++; 212 } 213 214 density = 1ULL << (sz_log2 - 2); 215 switch (type) { 216 case DDR2: 217 density = (density & 0xe0) | (density >> 8 & 0x1f); 218 break; 219 case DDR: 220 density = (density & 0xf8) | (density >> 8 & 0x07); 221 break; 222 case SDR: 223 default: 224 density &= 0xff; 225 break; 226 } 227 228 spd = g_malloc0(256); 229 spd[0] = 128; /* data bytes in EEPROM */ 230 spd[1] = 8; /* log2 size of EEPROM */ 231 spd[2] = type; 232 spd[3] = 13; /* row address bits */ 233 spd[4] = 10; /* column address bits */ 234 spd[5] = (type == DDR2 ? nbanks - 1 : nbanks); 235 spd[6] = 64; /* module data width */ 236 /* reserved / data width high */ 237 spd[8] = 4; /* interface voltage level */ 238 spd[9] = 0x25; /* highest CAS latency */ 239 spd[10] = 1; /* access time */ 240 /* DIMM configuration 0 = non-ECC */ 241 spd[12] = 0x82; /* refresh requirements */ 242 spd[13] = 8; /* primary SDRAM width */ 243 /* ECC SDRAM width */ 244 spd[15] = (type == DDR2 ? 0 : 1); /* reserved / delay for random col rd */ 245 spd[16] = 12; /* burst lengths supported */ 246 spd[17] = 4; /* banks per SDRAM device */ 247 spd[18] = 12; /* ~CAS latencies supported */ 248 spd[19] = (type == DDR2 ? 0 : 1); /* reserved / ~CS latencies supported */ 249 spd[20] = 2; /* DIMM type / ~WE latencies */ 250 /* module features */ 251 /* memory chip features */ 252 spd[23] = 0x12; /* clock cycle time @ medium CAS latency */ 253 /* data access time */ 254 /* clock cycle time @ short CAS latency */ 255 /* data access time */ 256 spd[27] = 20; /* min. row precharge time */ 257 spd[28] = 15; /* min. row active row delay */ 258 spd[29] = 20; /* min. ~RAS to ~CAS delay */ 259 spd[30] = 45; /* min. active to precharge time */ 260 spd[31] = density; 261 spd[32] = 20; /* addr/cmd setup time */ 262 spd[33] = 8; /* addr/cmd hold time */ 263 spd[34] = 20; /* data input setup time */ 264 spd[35] = 8; /* data input hold time */ 265 266 /* checksum */ 267 for (i = 0; i < 63; i++) { 268 spd[63] += spd[i]; 269 } 270 return spd; 271 } 272