1 /* 2 * QEMU MCH/ICH9 PCI Bridge Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2009, 2010, 2011 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on piix.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "hw/hw.h" 33 #include "hw/pci-host/q35.h" 34 #include "qapi/error.h" 35 #include "qapi/visitor.h" 36 #include "qemu/module.h" 37 38 /**************************************************************************** 39 * Q35 host 40 */ 41 42 #define Q35_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 35) 43 44 static void q35_host_realize(DeviceState *dev, Error **errp) 45 { 46 PCIHostState *pci = PCI_HOST_BRIDGE(dev); 47 Q35PCIHost *s = Q35_HOST_DEVICE(dev); 48 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 49 50 sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); 51 sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); 52 53 sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); 54 sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); 55 56 /* register q35 0xcf8 port as coalesced pio */ 57 memory_region_set_flush_coalesced(&pci->data_mem); 58 memory_region_add_coalescing(&pci->conf_mem, 0, 4); 59 60 pci->bus = pci_root_bus_new(DEVICE(s), "pcie.0", 61 s->mch.pci_address_space, 62 s->mch.address_space_io, 63 0, TYPE_PCIE_BUS); 64 PC_MACHINE(qdev_get_machine())->bus = pci->bus; 65 qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus)); 66 qdev_init_nofail(DEVICE(&s->mch)); 67 } 68 69 static const char *q35_host_root_bus_path(PCIHostState *host_bridge, 70 PCIBus *rootbus) 71 { 72 Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge); 73 74 /* For backwards compat with old device paths */ 75 if (s->mch.short_root_bus) { 76 return "0000"; 77 } 78 return "0000:00"; 79 } 80 81 static void q35_host_get_pci_hole_start(Object *obj, Visitor *v, 82 const char *name, void *opaque, 83 Error **errp) 84 { 85 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 86 uint64_t val64; 87 uint32_t value; 88 89 val64 = range_is_empty(&s->mch.pci_hole) 90 ? 0 : range_lob(&s->mch.pci_hole); 91 value = val64; 92 assert(value == val64); 93 visit_type_uint32(v, name, &value, errp); 94 } 95 96 static void q35_host_get_pci_hole_end(Object *obj, Visitor *v, 97 const char *name, void *opaque, 98 Error **errp) 99 { 100 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 101 uint64_t val64; 102 uint32_t value; 103 104 val64 = range_is_empty(&s->mch.pci_hole) 105 ? 0 : range_upb(&s->mch.pci_hole) + 1; 106 value = val64; 107 assert(value == val64); 108 visit_type_uint32(v, name, &value, errp); 109 } 110 111 /* 112 * The 64bit PCI hole start is set by the Guest firmware 113 * as the address of the first 64bit PCI MEM resource. 114 * If no PCI device has resources on the 64bit area, 115 * the 64bit PCI hole will start after "over 4G RAM" and the 116 * reserved space for memory hotplug if any. 117 */ 118 static uint64_t q35_host_get_pci_hole64_start_value(Object *obj) 119 { 120 PCIHostState *h = PCI_HOST_BRIDGE(obj); 121 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 122 Range w64; 123 uint64_t value; 124 125 pci_bus_get_w64_range(h->bus, &w64); 126 value = range_is_empty(&w64) ? 0 : range_lob(&w64); 127 if (!value && s->pci_hole64_fix) { 128 value = pc_pci_hole64_start(); 129 } 130 return value; 131 } 132 133 static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v, 134 const char *name, void *opaque, 135 Error **errp) 136 { 137 uint64_t hole64_start = q35_host_get_pci_hole64_start_value(obj); 138 139 visit_type_uint64(v, name, &hole64_start, errp); 140 } 141 142 /* 143 * The 64bit PCI hole end is set by the Guest firmware 144 * as the address of the last 64bit PCI MEM resource. 145 * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE 146 * that can be configured by the user. 147 */ 148 static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v, 149 const char *name, void *opaque, 150 Error **errp) 151 { 152 PCIHostState *h = PCI_HOST_BRIDGE(obj); 153 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 154 uint64_t hole64_start = q35_host_get_pci_hole64_start_value(obj); 155 Range w64; 156 uint64_t value, hole64_end; 157 158 pci_bus_get_w64_range(h->bus, &w64); 159 value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1; 160 hole64_end = ROUND_UP(hole64_start + s->mch.pci_hole64_size, 1ULL << 30); 161 if (s->pci_hole64_fix && value < hole64_end) { 162 value = hole64_end; 163 } 164 visit_type_uint64(v, name, &value, errp); 165 } 166 167 static void q35_host_get_mmcfg_size(Object *obj, Visitor *v, const char *name, 168 void *opaque, Error **errp) 169 { 170 PCIExpressHost *e = PCIE_HOST_BRIDGE(obj); 171 172 visit_type_uint64(v, name, &e->size, errp); 173 } 174 175 /* 176 * NOTE: setting defaults for the mch.* fields in this table 177 * doesn't work, because mch is a separate QOM object that is 178 * zeroed by the object_initialize(&s->mch, ...) call inside 179 * q35_host_initfn(). The default values for those 180 * properties need to be initialized manually by 181 * q35_host_initfn() after the object_initialize() call. 182 */ 183 static Property q35_host_props[] = { 184 DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr, 185 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), 186 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost, 187 mch.pci_hole64_size, Q35_PCI_HOST_HOLE64_SIZE_DEFAULT), 188 DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0), 189 DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, Q35PCIHost, 190 mch.below_4g_mem_size, 0), 191 DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost, 192 mch.above_4g_mem_size, 0), 193 DEFINE_PROP_BOOL("x-pci-hole64-fix", Q35PCIHost, pci_hole64_fix, true), 194 DEFINE_PROP_END_OF_LIST(), 195 }; 196 197 static void q35_host_class_init(ObjectClass *klass, void *data) 198 { 199 DeviceClass *dc = DEVICE_CLASS(klass); 200 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 201 202 hc->root_bus_path = q35_host_root_bus_path; 203 dc->realize = q35_host_realize; 204 dc->props = q35_host_props; 205 /* Reason: needs to be wired up by pc_q35_init */ 206 dc->user_creatable = false; 207 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 208 dc->fw_name = "pci"; 209 } 210 211 static void q35_host_initfn(Object *obj) 212 { 213 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 214 PCIHostState *phb = PCI_HOST_BRIDGE(obj); 215 216 memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, 217 "pci-conf-idx", 4); 218 memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, 219 "pci-conf-data", 4); 220 221 object_initialize_child(OBJECT(s), "mch", &s->mch, sizeof(s->mch), 222 TYPE_MCH_PCI_DEVICE, &error_abort, NULL); 223 qdev_prop_set_int32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); 224 qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); 225 /* mch's object_initialize resets the default value, set it again */ 226 qdev_prop_set_uint64(DEVICE(s), PCI_HOST_PROP_PCI_HOLE64_SIZE, 227 Q35_PCI_HOST_HOLE64_SIZE_DEFAULT); 228 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32", 229 q35_host_get_pci_hole_start, 230 NULL, NULL, NULL, NULL); 231 232 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32", 233 q35_host_get_pci_hole_end, 234 NULL, NULL, NULL, NULL); 235 236 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64", 237 q35_host_get_pci_hole64_start, 238 NULL, NULL, NULL, NULL); 239 240 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64", 241 q35_host_get_pci_hole64_end, 242 NULL, NULL, NULL, NULL); 243 244 object_property_add(obj, PCIE_HOST_MCFG_SIZE, "uint64", 245 q35_host_get_mmcfg_size, 246 NULL, NULL, NULL, NULL); 247 248 object_property_add_link(obj, MCH_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION, 249 (Object **) &s->mch.ram_memory, 250 qdev_prop_allow_set_link_before_realize, 0, NULL); 251 252 object_property_add_link(obj, MCH_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION, 253 (Object **) &s->mch.pci_address_space, 254 qdev_prop_allow_set_link_before_realize, 0, NULL); 255 256 object_property_add_link(obj, MCH_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION, 257 (Object **) &s->mch.system_memory, 258 qdev_prop_allow_set_link_before_realize, 0, NULL); 259 260 object_property_add_link(obj, MCH_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION, 261 (Object **) &s->mch.address_space_io, 262 qdev_prop_allow_set_link_before_realize, 0, NULL); 263 264 /* Leave enough space for the biggest MCFG BAR */ 265 /* TODO: this matches current bios behaviour, but 266 * it's not a power of two, which means an MTRR 267 * can't cover it exactly. 268 */ 269 range_set_bounds(&s->mch.pci_hole, 270 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT + MCH_HOST_BRIDGE_PCIEXBAR_MAX, 271 IO_APIC_DEFAULT_ADDRESS - 1); 272 } 273 274 static const TypeInfo q35_host_info = { 275 .name = TYPE_Q35_HOST_DEVICE, 276 .parent = TYPE_PCIE_HOST_BRIDGE, 277 .instance_size = sizeof(Q35PCIHost), 278 .instance_init = q35_host_initfn, 279 .class_init = q35_host_class_init, 280 }; 281 282 /**************************************************************************** 283 * MCH D0:F0 284 */ 285 286 static uint64_t tseg_blackhole_read(void *ptr, hwaddr reg, unsigned size) 287 { 288 return 0xffffffff; 289 } 290 291 static void tseg_blackhole_write(void *opaque, hwaddr addr, uint64_t val, 292 unsigned width) 293 { 294 /* nothing */ 295 } 296 297 static const MemoryRegionOps tseg_blackhole_ops = { 298 .read = tseg_blackhole_read, 299 .write = tseg_blackhole_write, 300 .endianness = DEVICE_NATIVE_ENDIAN, 301 .valid.min_access_size = 1, 302 .valid.max_access_size = 4, 303 .impl.min_access_size = 4, 304 .impl.max_access_size = 4, 305 .endianness = DEVICE_LITTLE_ENDIAN, 306 }; 307 308 /* PCIe MMCFG */ 309 static void mch_update_pciexbar(MCHPCIState *mch) 310 { 311 PCIDevice *pci_dev = PCI_DEVICE(mch); 312 BusState *bus = qdev_get_parent_bus(DEVICE(mch)); 313 PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent); 314 315 uint64_t pciexbar; 316 int enable; 317 uint64_t addr; 318 uint64_t addr_mask; 319 uint32_t length; 320 321 pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); 322 enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; 323 addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; 324 switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { 325 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: 326 length = 256 * 1024 * 1024; 327 break; 328 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: 329 length = 128 * 1024 * 1024; 330 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | 331 MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 332 break; 333 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: 334 length = 64 * 1024 * 1024; 335 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 336 break; 337 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: 338 default: 339 abort(); 340 } 341 addr = pciexbar & addr_mask; 342 pcie_host_mmcfg_update(pehb, enable, addr, length); 343 /* Leave enough space for the MCFG BAR */ 344 /* 345 * TODO: this matches current bios behaviour, but it's not a power of two, 346 * which means an MTRR can't cover it exactly. 347 */ 348 if (enable) { 349 range_set_bounds(&mch->pci_hole, 350 addr + length, 351 IO_APIC_DEFAULT_ADDRESS - 1); 352 } else { 353 range_set_bounds(&mch->pci_hole, 354 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT, 355 IO_APIC_DEFAULT_ADDRESS - 1); 356 } 357 } 358 359 /* PAM */ 360 static void mch_update_pam(MCHPCIState *mch) 361 { 362 PCIDevice *pd = PCI_DEVICE(mch); 363 int i; 364 365 memory_region_transaction_begin(); 366 for (i = 0; i < 13; i++) { 367 pam_update(&mch->pam_regions[i], i, 368 pd->config[MCH_HOST_BRIDGE_PAM0 + DIV_ROUND_UP(i, 2)]); 369 } 370 memory_region_transaction_commit(); 371 } 372 373 /* SMRAM */ 374 static void mch_update_smram(MCHPCIState *mch) 375 { 376 PCIDevice *pd = PCI_DEVICE(mch); 377 bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME); 378 uint32_t tseg_size; 379 380 /* implement SMRAM.D_LCK */ 381 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) { 382 pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN; 383 pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK; 384 pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK; 385 } 386 387 memory_region_transaction_begin(); 388 389 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) { 390 /* Hide (!) low SMRAM if H_SMRAME = 1 */ 391 memory_region_set_enabled(&mch->smram_region, h_smrame); 392 /* Show high SMRAM if H_SMRAME = 1 */ 393 memory_region_set_enabled(&mch->open_high_smram, h_smrame); 394 } else { 395 /* Hide high SMRAM and low SMRAM */ 396 memory_region_set_enabled(&mch->smram_region, true); 397 memory_region_set_enabled(&mch->open_high_smram, false); 398 } 399 400 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME) { 401 memory_region_set_enabled(&mch->low_smram, !h_smrame); 402 memory_region_set_enabled(&mch->high_smram, h_smrame); 403 } else { 404 memory_region_set_enabled(&mch->low_smram, false); 405 memory_region_set_enabled(&mch->high_smram, false); 406 } 407 408 if (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) { 409 switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & 410 MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) { 411 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB: 412 tseg_size = 1024 * 1024; 413 break; 414 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB: 415 tseg_size = 1024 * 1024 * 2; 416 break; 417 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB: 418 tseg_size = 1024 * 1024 * 8; 419 break; 420 default: 421 tseg_size = 1024 * 1024 * (uint32_t)mch->ext_tseg_mbytes; 422 break; 423 } 424 } else { 425 tseg_size = 0; 426 } 427 memory_region_del_subregion(mch->system_memory, &mch->tseg_blackhole); 428 memory_region_set_enabled(&mch->tseg_blackhole, tseg_size); 429 memory_region_set_size(&mch->tseg_blackhole, tseg_size); 430 memory_region_add_subregion_overlap(mch->system_memory, 431 mch->below_4g_mem_size - tseg_size, 432 &mch->tseg_blackhole, 1); 433 434 memory_region_set_enabled(&mch->tseg_window, tseg_size); 435 memory_region_set_size(&mch->tseg_window, tseg_size); 436 memory_region_set_address(&mch->tseg_window, 437 mch->below_4g_mem_size - tseg_size); 438 memory_region_set_alias_offset(&mch->tseg_window, 439 mch->below_4g_mem_size - tseg_size); 440 441 memory_region_transaction_commit(); 442 } 443 444 static void mch_update_ext_tseg_mbytes(MCHPCIState *mch) 445 { 446 PCIDevice *pd = PCI_DEVICE(mch); 447 uint8_t *reg = pd->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES; 448 449 if (mch->ext_tseg_mbytes > 0 && 450 pci_get_word(reg) == MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY) { 451 pci_set_word(reg, mch->ext_tseg_mbytes); 452 } 453 } 454 455 static void mch_write_config(PCIDevice *d, 456 uint32_t address, uint32_t val, int len) 457 { 458 MCHPCIState *mch = MCH_PCI_DEVICE(d); 459 460 pci_default_write_config(d, address, val, len); 461 462 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, 463 MCH_HOST_BRIDGE_PAM_SIZE)) { 464 mch_update_pam(mch); 465 } 466 467 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, 468 MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { 469 mch_update_pciexbar(mch); 470 } 471 472 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM, 473 MCH_HOST_BRIDGE_SMRAM_SIZE)) { 474 mch_update_smram(mch); 475 } 476 477 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, 478 MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE)) { 479 mch_update_ext_tseg_mbytes(mch); 480 } 481 } 482 483 static void mch_update(MCHPCIState *mch) 484 { 485 mch_update_pciexbar(mch); 486 mch_update_pam(mch); 487 mch_update_smram(mch); 488 mch_update_ext_tseg_mbytes(mch); 489 } 490 491 static int mch_post_load(void *opaque, int version_id) 492 { 493 MCHPCIState *mch = opaque; 494 mch_update(mch); 495 return 0; 496 } 497 498 static const VMStateDescription vmstate_mch = { 499 .name = "mch", 500 .version_id = 1, 501 .minimum_version_id = 1, 502 .post_load = mch_post_load, 503 .fields = (VMStateField[]) { 504 VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), 505 /* Used to be smm_enabled, which was basically always zero because 506 * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code. 507 */ 508 VMSTATE_UNUSED(1), 509 VMSTATE_END_OF_LIST() 510 } 511 }; 512 513 static void mch_reset(DeviceState *qdev) 514 { 515 PCIDevice *d = PCI_DEVICE(qdev); 516 MCHPCIState *mch = MCH_PCI_DEVICE(d); 517 518 pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, 519 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); 520 521 d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; 522 d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT; 523 d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK; 524 d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK; 525 526 if (mch->ext_tseg_mbytes > 0) { 527 pci_set_word(d->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, 528 MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY); 529 } 530 531 mch_update(mch); 532 } 533 534 static void mch_realize(PCIDevice *d, Error **errp) 535 { 536 int i; 537 MCHPCIState *mch = MCH_PCI_DEVICE(d); 538 539 if (mch->ext_tseg_mbytes > MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX) { 540 error_setg(errp, "invalid extended-tseg-mbytes value: %" PRIu16, 541 mch->ext_tseg_mbytes); 542 return; 543 } 544 545 /* setup pci memory mapping */ 546 pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory, 547 mch->pci_address_space); 548 549 /* if *disabled* show SMRAM to all CPUs */ 550 memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", 551 mch->pci_address_space, MCH_HOST_BRIDGE_SMRAM_C_BASE, 552 MCH_HOST_BRIDGE_SMRAM_C_SIZE); 553 memory_region_add_subregion_overlap(mch->system_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 554 &mch->smram_region, 1); 555 memory_region_set_enabled(&mch->smram_region, true); 556 557 memory_region_init_alias(&mch->open_high_smram, OBJECT(mch), "smram-open-high", 558 mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 559 MCH_HOST_BRIDGE_SMRAM_C_SIZE); 560 memory_region_add_subregion_overlap(mch->system_memory, 0xfeda0000, 561 &mch->open_high_smram, 1); 562 memory_region_set_enabled(&mch->open_high_smram, false); 563 564 /* smram, as seen by SMM CPUs */ 565 memory_region_init(&mch->smram, OBJECT(mch), "smram", 1ull << 32); 566 memory_region_set_enabled(&mch->smram, true); 567 memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low", 568 mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 569 MCH_HOST_BRIDGE_SMRAM_C_SIZE); 570 memory_region_set_enabled(&mch->low_smram, true); 571 memory_region_add_subregion(&mch->smram, MCH_HOST_BRIDGE_SMRAM_C_BASE, 572 &mch->low_smram); 573 memory_region_init_alias(&mch->high_smram, OBJECT(mch), "smram-high", 574 mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 575 MCH_HOST_BRIDGE_SMRAM_C_SIZE); 576 memory_region_set_enabled(&mch->high_smram, true); 577 memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram); 578 579 memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch), 580 &tseg_blackhole_ops, NULL, 581 "tseg-blackhole", 0); 582 memory_region_set_enabled(&mch->tseg_blackhole, false); 583 memory_region_add_subregion_overlap(mch->system_memory, 584 mch->below_4g_mem_size, 585 &mch->tseg_blackhole, 1); 586 587 memory_region_init_alias(&mch->tseg_window, OBJECT(mch), "tseg-window", 588 mch->ram_memory, mch->below_4g_mem_size, 0); 589 memory_region_set_enabled(&mch->tseg_window, false); 590 memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size, 591 &mch->tseg_window); 592 object_property_add_const_link(qdev_get_machine(), "smram", 593 OBJECT(&mch->smram), &error_abort); 594 595 init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 596 mch->pci_address_space, &mch->pam_regions[0], 597 PAM_BIOS_BASE, PAM_BIOS_SIZE); 598 for (i = 0; i < 12; ++i) { 599 init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 600 mch->pci_address_space, &mch->pam_regions[i+1], 601 PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); 602 } 603 } 604 605 uint64_t mch_mcfg_base(void) 606 { 607 bool ambiguous; 608 Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous); 609 if (!o) { 610 return 0; 611 } 612 return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; 613 } 614 615 static Property mch_props[] = { 616 DEFINE_PROP_UINT16("extended-tseg-mbytes", MCHPCIState, ext_tseg_mbytes, 617 16), 618 DEFINE_PROP_END_OF_LIST(), 619 }; 620 621 static void mch_class_init(ObjectClass *klass, void *data) 622 { 623 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 624 DeviceClass *dc = DEVICE_CLASS(klass); 625 626 k->realize = mch_realize; 627 k->config_write = mch_write_config; 628 dc->reset = mch_reset; 629 dc->props = mch_props; 630 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 631 dc->desc = "Host bridge"; 632 dc->vmsd = &vmstate_mch; 633 k->vendor_id = PCI_VENDOR_ID_INTEL; 634 /* 635 * The 'q35' machine type implements an Intel Series 3 chipset, 636 * of which there are several variants. The key difference between 637 * the 82P35 MCH ('p35') and 82Q35 GMCH ('q35') variants is that 638 * the latter has an integrated graphics adapter. QEMU does not 639 * implement integrated graphics, so uses the PCI ID for the 82P35 640 * chipset. 641 */ 642 k->device_id = PCI_DEVICE_ID_INTEL_P35_MCH; 643 k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT; 644 k->class_id = PCI_CLASS_BRIDGE_HOST; 645 /* 646 * PCI-facing part of the host bridge, not usable without the 647 * host-facing part, which can't be device_add'ed, yet. 648 */ 649 dc->user_creatable = false; 650 } 651 652 static const TypeInfo mch_info = { 653 .name = TYPE_MCH_PCI_DEVICE, 654 .parent = TYPE_PCI_DEVICE, 655 .instance_size = sizeof(MCHPCIState), 656 .class_init = mch_class_init, 657 .interfaces = (InterfaceInfo[]) { 658 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 659 { }, 660 }, 661 }; 662 663 static void q35_register(void) 664 { 665 type_register_static(&mch_info); 666 type_register_static(&q35_host_info); 667 } 668 669 type_init(q35_register); 670