1 /* 2 * STM32F2XX ADC 3 * 4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/sysbus.h" 27 #include "migration/vmstate.h" 28 #include "hw/hw.h" 29 #include "qemu/log.h" 30 #include "qemu/module.h" 31 #include "hw/adc/stm32f2xx_adc.h" 32 33 #ifndef STM_ADC_ERR_DEBUG 34 #define STM_ADC_ERR_DEBUG 0 35 #endif 36 37 #define DB_PRINT_L(lvl, fmt, args...) do { \ 38 if (STM_ADC_ERR_DEBUG >= lvl) { \ 39 qemu_log("%s: " fmt, __func__, ## args); \ 40 } \ 41 } while (0) 42 43 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) 44 45 static void stm32f2xx_adc_reset(DeviceState *dev) 46 { 47 STM32F2XXADCState *s = STM32F2XX_ADC(dev); 48 49 s->adc_sr = 0x00000000; 50 s->adc_cr1 = 0x00000000; 51 s->adc_cr2 = 0x00000000; 52 s->adc_smpr1 = 0x00000000; 53 s->adc_smpr2 = 0x00000000; 54 s->adc_jofr[0] = 0x00000000; 55 s->adc_jofr[1] = 0x00000000; 56 s->adc_jofr[2] = 0x00000000; 57 s->adc_jofr[3] = 0x00000000; 58 s->adc_htr = 0x00000FFF; 59 s->adc_ltr = 0x00000000; 60 s->adc_sqr1 = 0x00000000; 61 s->adc_sqr2 = 0x00000000; 62 s->adc_sqr3 = 0x00000000; 63 s->adc_jsqr = 0x00000000; 64 s->adc_jdr[0] = 0x00000000; 65 s->adc_jdr[1] = 0x00000000; 66 s->adc_jdr[2] = 0x00000000; 67 s->adc_jdr[3] = 0x00000000; 68 s->adc_dr = 0x00000000; 69 } 70 71 static uint32_t stm32f2xx_adc_generate_value(STM32F2XXADCState *s) 72 { 73 /* Attempts to fake some ADC values */ 74 s->adc_dr = s->adc_dr + 7; 75 76 switch ((s->adc_cr1 & ADC_CR1_RES) >> 24) { 77 case 0: 78 /* 12-bit */ 79 s->adc_dr &= 0xFFF; 80 break; 81 case 1: 82 /* 10-bit */ 83 s->adc_dr &= 0x3FF; 84 break; 85 case 2: 86 /* 8-bit */ 87 s->adc_dr &= 0xFF; 88 break; 89 default: 90 /* 6-bit */ 91 s->adc_dr &= 0x3F; 92 } 93 94 if (s->adc_cr2 & ADC_CR2_ALIGN) { 95 return (s->adc_dr << 1) & 0xFFF0; 96 } else { 97 return s->adc_dr; 98 } 99 } 100 101 static uint64_t stm32f2xx_adc_read(void *opaque, hwaddr addr, 102 unsigned int size) 103 { 104 STM32F2XXADCState *s = opaque; 105 106 DB_PRINT("Address: 0x%" HWADDR_PRIx "\n", addr); 107 108 if (addr >= ADC_COMMON_ADDRESS) { 109 qemu_log_mask(LOG_UNIMP, 110 "%s: ADC Common Register Unsupported\n", __func__); 111 } 112 113 switch (addr) { 114 case ADC_SR: 115 return s->adc_sr; 116 case ADC_CR1: 117 return s->adc_cr1; 118 case ADC_CR2: 119 return s->adc_cr2 & 0xFFFFFFF; 120 case ADC_SMPR1: 121 return s->adc_smpr1; 122 case ADC_SMPR2: 123 return s->adc_smpr2; 124 case ADC_JOFR1: 125 case ADC_JOFR2: 126 case ADC_JOFR3: 127 case ADC_JOFR4: 128 qemu_log_mask(LOG_UNIMP, "%s: " \ 129 "Injection ADC is not implemented, the registers are " \ 130 "included for compatibility\n", __func__); 131 return s->adc_jofr[(addr - ADC_JOFR1) / 4]; 132 case ADC_HTR: 133 return s->adc_htr; 134 case ADC_LTR: 135 return s->adc_ltr; 136 case ADC_SQR1: 137 return s->adc_sqr1; 138 case ADC_SQR2: 139 return s->adc_sqr2; 140 case ADC_SQR3: 141 return s->adc_sqr3; 142 case ADC_JSQR: 143 qemu_log_mask(LOG_UNIMP, "%s: " \ 144 "Injection ADC is not implemented, the registers are " \ 145 "included for compatibility\n", __func__); 146 return s->adc_jsqr; 147 case ADC_JDR1: 148 case ADC_JDR2: 149 case ADC_JDR3: 150 case ADC_JDR4: 151 qemu_log_mask(LOG_UNIMP, "%s: " \ 152 "Injection ADC is not implemented, the registers are " \ 153 "included for compatibility\n", __func__); 154 return s->adc_jdr[(addr - ADC_JDR1) / 4] - 155 s->adc_jofr[(addr - ADC_JDR1) / 4]; 156 case ADC_DR: 157 if ((s->adc_cr2 & ADC_CR2_ADON) && (s->adc_cr2 & ADC_CR2_SWSTART)) { 158 s->adc_cr2 ^= ADC_CR2_SWSTART; 159 return stm32f2xx_adc_generate_value(s); 160 } else { 161 return 0; 162 } 163 default: 164 qemu_log_mask(LOG_GUEST_ERROR, 165 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr); 166 } 167 168 return 0; 169 } 170 171 static void stm32f2xx_adc_write(void *opaque, hwaddr addr, 172 uint64_t val64, unsigned int size) 173 { 174 STM32F2XXADCState *s = opaque; 175 uint32_t value = (uint32_t) val64; 176 177 DB_PRINT("Address: 0x%" HWADDR_PRIx ", Value: 0x%x\n", 178 addr, value); 179 180 if (addr >= 0x100) { 181 qemu_log_mask(LOG_UNIMP, 182 "%s: ADC Common Register Unsupported\n", __func__); 183 } 184 185 switch (addr) { 186 case ADC_SR: 187 s->adc_sr &= (value & 0x3F); 188 break; 189 case ADC_CR1: 190 s->adc_cr1 = value; 191 break; 192 case ADC_CR2: 193 s->adc_cr2 = value; 194 break; 195 case ADC_SMPR1: 196 s->adc_smpr1 = value; 197 break; 198 case ADC_SMPR2: 199 s->adc_smpr2 = value; 200 break; 201 case ADC_JOFR1: 202 case ADC_JOFR2: 203 case ADC_JOFR3: 204 case ADC_JOFR4: 205 s->adc_jofr[(addr - ADC_JOFR1) / 4] = (value & 0xFFF); 206 qemu_log_mask(LOG_UNIMP, "%s: " \ 207 "Injection ADC is not implemented, the registers are " \ 208 "included for compatibility\n", __func__); 209 break; 210 case ADC_HTR: 211 s->adc_htr = value; 212 break; 213 case ADC_LTR: 214 s->adc_ltr = value; 215 break; 216 case ADC_SQR1: 217 s->adc_sqr1 = value; 218 break; 219 case ADC_SQR2: 220 s->adc_sqr2 = value; 221 break; 222 case ADC_SQR3: 223 s->adc_sqr3 = value; 224 break; 225 case ADC_JSQR: 226 s->adc_jsqr = value; 227 qemu_log_mask(LOG_UNIMP, "%s: " \ 228 "Injection ADC is not implemented, the registers are " \ 229 "included for compatibility\n", __func__); 230 break; 231 case ADC_JDR1: 232 case ADC_JDR2: 233 case ADC_JDR3: 234 case ADC_JDR4: 235 s->adc_jdr[(addr - ADC_JDR1) / 4] = value; 236 qemu_log_mask(LOG_UNIMP, "%s: " \ 237 "Injection ADC is not implemented, the registers are " \ 238 "included for compatibility\n", __func__); 239 break; 240 default: 241 qemu_log_mask(LOG_GUEST_ERROR, 242 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr); 243 } 244 } 245 246 static const MemoryRegionOps stm32f2xx_adc_ops = { 247 .read = stm32f2xx_adc_read, 248 .write = stm32f2xx_adc_write, 249 .endianness = DEVICE_NATIVE_ENDIAN, 250 }; 251 252 static const VMStateDescription vmstate_stm32f2xx_adc = { 253 .name = TYPE_STM32F2XX_ADC, 254 .version_id = 1, 255 .minimum_version_id = 1, 256 .fields = (VMStateField[]) { 257 VMSTATE_UINT32(adc_sr, STM32F2XXADCState), 258 VMSTATE_UINT32(adc_cr1, STM32F2XXADCState), 259 VMSTATE_UINT32(adc_cr2, STM32F2XXADCState), 260 VMSTATE_UINT32(adc_smpr1, STM32F2XXADCState), 261 VMSTATE_UINT32(adc_smpr2, STM32F2XXADCState), 262 VMSTATE_UINT32_ARRAY(adc_jofr, STM32F2XXADCState, 4), 263 VMSTATE_UINT32(adc_htr, STM32F2XXADCState), 264 VMSTATE_UINT32(adc_ltr, STM32F2XXADCState), 265 VMSTATE_UINT32(adc_sqr1, STM32F2XXADCState), 266 VMSTATE_UINT32(adc_sqr2, STM32F2XXADCState), 267 VMSTATE_UINT32(adc_sqr3, STM32F2XXADCState), 268 VMSTATE_UINT32(adc_jsqr, STM32F2XXADCState), 269 VMSTATE_UINT32_ARRAY(adc_jdr, STM32F2XXADCState, 4), 270 VMSTATE_UINT32(adc_dr, STM32F2XXADCState), 271 VMSTATE_END_OF_LIST() 272 } 273 }; 274 275 static void stm32f2xx_adc_init(Object *obj) 276 { 277 STM32F2XXADCState *s = STM32F2XX_ADC(obj); 278 279 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 280 281 memory_region_init_io(&s->mmio, obj, &stm32f2xx_adc_ops, s, 282 TYPE_STM32F2XX_ADC, 0xFF); 283 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 284 } 285 286 static void stm32f2xx_adc_class_init(ObjectClass *klass, void *data) 287 { 288 DeviceClass *dc = DEVICE_CLASS(klass); 289 290 dc->reset = stm32f2xx_adc_reset; 291 dc->vmsd = &vmstate_stm32f2xx_adc; 292 } 293 294 static const TypeInfo stm32f2xx_adc_info = { 295 .name = TYPE_STM32F2XX_ADC, 296 .parent = TYPE_SYS_BUS_DEVICE, 297 .instance_size = sizeof(STM32F2XXADCState), 298 .instance_init = stm32f2xx_adc_init, 299 .class_init = stm32f2xx_adc_class_init, 300 }; 301 302 static void stm32f2xx_adc_register_types(void) 303 { 304 type_register_static(&stm32f2xx_adc_info); 305 } 306 307 type_init(stm32f2xx_adc_register_types) 308