arm64: dts: ti: k3-am64: Merge the two main_conf nodes

There are two nodes representing the same register space, this looks to
have been created by some merge or copy/paste error. Remove the second

arm64: dts: ti: k3-am64: Merge the two main_conf nodes

There are two nodes representing the same register space, this looks to
have been created by some merge or copy/paste error. Remove the second
instance of this node and move its children into the first instance.

Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230802174521.236255-2-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-am62a: Remove syscon compatible from epwm_tbclk

The other instances have been fixed, but AM62a seems to have been missed,
fix this here.

Signed-off-by: Andrew Davis <afd@ti.com>

arm64: dts: ti: k3-am62a: Remove syscon compatible from epwm_tbclk

The other instances have been fixed, but AM62a seems to have been missed,
fix this here.

Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230802174521.236255-1-afd@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-am62a7-sk: Enable dual role support for Type-C port

USB0 is interfaced with a Type-C DRP connector and is managed via a
USB PD controller. Add support for the Type-C port with dua

arm64: dts: ti: k3-am62a7-sk: Enable dual role support for Type-C port

USB0 is interfaced with a Type-C DRP connector and is managed via a
USB PD controller. Add support for the Type-C port with dual data
and power sink role.

Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230725103651.1612-1-r-gunasekaran@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-am625-verdin: enable CAN_2

Add Verdin CAN_2 (TI AM62 MCU_MCAN0) and enable it on the Yavia,
Dahlia and Verdin Development board.

Signed-off-by: Hiago De Franco <hiago.franco@tora

arm64: dts: ti: k3-am625-verdin: enable CAN_2

Add Verdin CAN_2 (TI AM62 MCU_MCAN0) and enable it on the Yavia,
Dahlia and Verdin Development board.

Signed-off-by: Hiago De Franco <hiago.franco@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Link: https://lore.kernel.org/r/20230802073635.11290-3-francesco@dolcini.it
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-am62: Add MCU MCAN nodes

On AM62x there are no hardware interrupts routed to A53 GIC
interrupt controller for MCU MCAN IPs, so MCU MCAN nodes were
omitted from MCU dtsi.

Timer po

arm64: dts: ti: k3-am62: Add MCU MCAN nodes

On AM62x there are no hardware interrupts routed to A53 GIC
interrupt controller for MCU MCAN IPs, so MCU MCAN nodes were
omitted from MCU dtsi.

Timer polling was introduced in commits [1][2] so now add MCU MCAN nodes
to the MCU dtsi for the Cortex A53.

[1] commit b382380c0d2d ("can: m_can: Add hrtimer to generate software interrupt")
[2] commit bb410c03b999 ("dt-bindings: net: can: Remove interrupt properties for MCAN")

[fd: fixed labels to match datasheet numbering, revised commit message,
fixed reg/reg-names order]

Signed-off-by: Judith Mendez <jm@ti.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Link: https://lore.kernel.org/r/20230802073635.11290-2-francesco@dolcini.it
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3: Fixup remaining pin group node names for make dtbs checks

Fix up outstanding pingroup node names to be compliant with the
upcoming pinctrl-single schema.

Reviewed-by: Tony Lindg

arm64: dts: ti: k3: Fixup remaining pin group node names for make dtbs checks

Fix up outstanding pingroup node names to be compliant with the
upcoming pinctrl-single schema.

Reviewed-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20230802040347.2264339-1-nm@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-am64-tqma64xxl-mbax4xxl: add SD-card and WLAN overlays

As the SD-card and WLAN are connected to the same SDHC interface (with a
GPIO-controlled mux), they are mutually exclusive.

arm64: dts: ti: k3-am64-tqma64xxl-mbax4xxl: add SD-card and WLAN overlays

As the SD-card and WLAN are connected to the same SDHC interface (with a
GPIO-controlled mux), they are mutually exclusive. Provide Device Tree
overlays for both configurations.

Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Link: https://lore.kernel.org/r/8ff8a6f1fdbe6ebb478f88bb0737628054c43c5b.1690463382.git.matthias.schiffer@ew.tq-group.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: Add TQ-Systems TQMa64XxL SoM and MBaX4XxL carrier board Device Trees

The TQMa64XxL is an LGA SoM based on the TI AM64x SoC family. Add DTS(I)
for the AM642 (2x Cortex-A53) variant an

arm64: dts: ti: Add TQ-Systems TQMa64XxL SoM and MBaX4XxL carrier board Device Trees

The TQMa64XxL is an LGA SoM based on the TI AM64x SoC family. Add DTS(I)
for the AM642 (2x Cortex-A53) variant and its combination with our
MBaX4XxL carrier board.

Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Link: https://lore.kernel.org/r/2a635428c73b5ab0fe793e558db6b5d88edccf8c.1690463382.git.matthias.schiffer@ew.tq-group.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-j721s2: Add overlay to enable main CPSW2G with GESI

The MAIN CPSW2G instance of CPSW on J721S2 SoC can be enabled with the GESI
Expansion Board connected to the J7 Common-Proc-Boa

arm64: dts: ti: k3-j721s2: Add overlay to enable main CPSW2G with GESI

The MAIN CPSW2G instance of CPSW on J721S2 SoC can be enabled with the GESI
Expansion Board connected to the J7 Common-Proc-Board. Use the overlay
to enable this.

Add alias for the MAIN CPSW2G port to enable kernel to fetch MAC address
directly from U-Boot.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Link: https://lore.kernel.org/r/20230726065407.378455-3-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-j721s2-main: Add main CPSW2G devicetree node

TI's J721S2 SoC has a MAIN CPSW2G instance of the CPSW Ethernet Switch.
Add devicetree node for it.

Signed-off-by: Kishon Vijay Abrah

arm64: dts: ti: k3-j721s2-main: Add main CPSW2G devicetree node

TI's J721S2 SoC has a MAIN CPSW2G instance of the CPSW Ethernet Switch.
Add devicetree node for it.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Link: https://lore.kernel.org/r/20230726065407.378455-2-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-j721e: Add overlay to enable CPSW9G ports with GESI

The J7 GESI EXP board for J721E Common-Proc-Board supports RGMII mode.
Use the overlay to configure CPSW9G ports in RGMII-RXID

arm64: dts: ti: k3-j721e: Add overlay to enable CPSW9G ports with GESI

The J7 GESI EXP board for J721E Common-Proc-Board supports RGMII mode.
Use the overlay to configure CPSW9G ports in RGMII-RXID mode.

Add aliases for CPSW9G ports to enable kernel to fetch MAC addresses
directly from U-Boot.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Link: https://lore.kernel.org/r/20230725073057.96705-1-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-j784s4-evm: Add Support for UFS peripheral

J784S4 EVM board has 32GB Non-Volatile UFS Memory.
So enabling UFS at board level.

UFS flash details are documented in board data sheet

arm64: dts: ti: k3-j784s4-evm: Add Support for UFS peripheral

J784S4 EVM board has 32GB Non-Volatile UFS Memory.
So enabling UFS at board level.

UFS flash details are documented in board data sheet[1]
Section 1.2 Key Features and Interfaces.

[1] https://www.ti.com/lit/pdf/spruj62

Cc: Chai Wenle <Wenle.Chai@windriver.com>
Tested-by: Chai Wenle <Wenle.Chai@windriver.com>
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20230725133607.2021379-3-u-kumar1@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-j784s4-main: Add DT node for UFS

Add UFS support present in J784S4 SOC.

UFS is documented in J784S4 TRM[1]
Section 12.3.7 'Universal Flash Storage (UFS) Interface'

[1] http://ww

arm64: dts: ti: k3-j784s4-main: Add DT node for UFS

Add UFS support present in J784S4 SOC.

UFS is documented in J784S4 TRM[1]
Section 12.3.7 'Universal Flash Storage (UFS) Interface'

[1] http://www.ti.com/lit/zip/spruj52

Cc: Chai Wenle <Wenle.Chai@windriver.com>
Tested-by: Chai Wenle <Wenle.Chai@windriver.com>
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20230725133607.2021379-2-u-kumar1@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-j721s2-main: Add dts nodes for EHRPWMs

Add dts nodes for 6 EHRPWM instances on SoC. Disable EHRPWM nodes in the
dtsi files and only enable the ones that are actually pinned out on

arm64: dts: ti: k3-j721s2-main: Add dts nodes for EHRPWMs

Add dts nodes for 6 EHRPWM instances on SoC. Disable EHRPWM nodes in the
dtsi files and only enable the ones that are actually pinned out on a
given board in the board dts file.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
Link: https://lore.kernel.org/r/20230721082150.12599-1-sinthu.raja@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-j721s2: Add support for CAN instances 3 and 5 in main domain

CAN instances 3 and 5 in the main domain are brought on the common
processor board through header J27 and J28. The CAN

arm64: dts: ti: k3-j721s2: Add support for CAN instances 3 and 5 in main domain

CAN instances 3 and 5 in the main domain are brought on the common
processor board through header J27 and J28. The CAN High and Low lines
from the SoC are routed through a mux on the SoM. The select lines need
to be set for the CAN signals to get connected to the transceivers on
the common processor board. Threfore, add respective mux, transceiver
dt nodes to add support for these CAN instances.

Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Link: https://lore.kernel.org/r/20230725085939.536766-1-b-kapoor@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-pinctrl: Introduce debounce select mux macros

Introduce the debounce select mux macros to allow folks to setup
debounce configuration for pins. Each configuration selected maps
to

arm64: dts: ti: k3-pinctrl: Introduce debounce select mux macros

Introduce the debounce select mux macros to allow folks to setup
debounce configuration for pins. Each configuration selected maps
to a specific timing register as documented in appropriate Technical
Reference Manual (example:[1]).

[1] AM625x TRM (section 6.1.2.2): https://www.ti.com/lit/pdf/spruiv7

Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20230619131620.3286650-1-nm@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-am62-main: Remove power-domains from crypto node

Only SYSFW has control of SA3UL power.
From SYSFW 08.04.00.002, for security reasons, device ID for power
management of SA3UL has

arm64: dts: ti: k3-am62-main: Remove power-domains from crypto node

Only SYSFW has control of SA3UL power.
From SYSFW 08.04.00.002, for security reasons, device ID for power
management of SA3UL has been removed.

"power-domains" property in crypto node tries to access
the SA3UL, for which it gets NACK and hence, SA3UL driver doesn't
probe properly.

Fixes: 8af893654c02 ("arm64: dts: ti: k3-am62-main: Enable crypto accelerator")

Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
Link: https://lore.kernel.org/r/20230614-sa3ul-v5-2-29dd2366fba3@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: Use local header for SERDES MUX idle-state values

The DTS uses constants for SERDES MUX idle state values which were earlier
provided as bindings header. But they are unsuitable for

arm64: dts: ti: Use local header for SERDES MUX idle-state values

The DTS uses constants for SERDES MUX idle state values which were earlier
provided as bindings header. But they are unsuitable for bindings.
So move these constants in a header next to DTS.

Also add J784S4 SERDES4 lane definitions which were missed earlier.

Suggested-by: Nishanth Menon <nm@ti.com>
Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Suggested-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/linux-arm-kernel/b24c2124-fe3b-246c-9af9-3ecee9fb32d4@kernel.org/
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Roger Quadros <rogerq@kernel.org>
Acked-by: Peter Rosin <peda@axentia.se>
Link: https://lore.kernel.org/r/20230721125732.122421-2-j-choudhary@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: k3-j721e-som-p0: Remove Duplicated wkup_i2c0 node

wkup_i2c0 and associated eeprom device node were duplicated,
This patch fixes the node duplication.

Fixes: 4af0332876f9 ("arm64: dt

arm64: dts: ti: k3-j721e-som-p0: Remove Duplicated wkup_i2c0 node

wkup_i2c0 and associated eeprom device node were duplicated,
This patch fixes the node duplication.

Fixes: 4af0332876f9 ("arm64: dts: ti: k3-j721e-som-p0: Enable wakeup_i2c0 and eeprom")
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230721082344.1534094-1-u-kumar1@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: Fix compatible of ti,*-ehrpwm-tbclk

TI EHRPWM compatible is just ti,*-ehrpwm-tbclk without needing a
syscon compatibility.

Fixes the following dtbs_check warnings:
compatible: [''t

arm64: dts: ti: Fix compatible of ti,*-ehrpwm-tbclk

TI EHRPWM compatible is just ti,*-ehrpwm-tbclk without needing a
syscon compatibility.

Fixes the following dtbs_check warnings:
compatible: [''ti,am654-ehrpwm-tbclk, 'syscon'] is too long
compatible: ['ti,am64-epwm-tbclk', 'syscon'] is too long
compatible: ['ti,am62-epwm-tbclk', 'syscon'] is too long

Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20230713184759.3336536-1-nm@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: add missing space before {

Add missing whitespace between node name/label and opening {.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: David Lechn

arm64: dts: ti: add missing space before {

Add missing whitespace between node name/label and opening {.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: David Lechner <david@lechnology.com>
Link: https://lore.kernel.org/r/20230705145755.292927-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Nishanth Menon <nm@ti.com>

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arm64: dts: ti: minor whitespace cleanup around '='

The DTS code coding style expects exactly one space before and after '='
sign.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org

arm64: dts: ti: minor whitespace cleanup around '='

The DTS code coding style expects exactly one space before and after '='
sign.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230702185221.44319-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Nishanth Menon <nm@ti.com>

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