1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721S2 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/phy/phy-cadence.h> 9#include <dt-bindings/phy/phy-ti.h> 10 11/ { 12 serdes_refclk: clock-cmnrefclk { 13 #clock-cells = <0>; 14 compatible = "fixed-clock"; 15 clock-frequency = <0>; 16 }; 17}; 18 19&cbass_main { 20 msmc_ram: sram@70000000 { 21 compatible = "mmio-sram"; 22 reg = <0x0 0x70000000 0x0 0x400000>; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 ranges = <0x0 0x0 0x70000000 0x400000>; 26 27 atf-sram@0 { 28 reg = <0x0 0x20000>; 29 }; 30 31 tifs-sram@1f0000 { 32 reg = <0x1f0000 0x10000>; 33 }; 34 35 l3cache-sram@200000 { 36 reg = <0x200000 0x200000>; 37 }; 38 }; 39 40 scm_conf: syscon@104000 { 41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 42 reg = <0x00 0x00104000 0x00 0x18000>; 43 #address-cells = <1>; 44 #size-cells = <1>; 45 ranges = <0x00 0x00 0x00104000 0x18000>; 46 47 usb_serdes_mux: mux-controller@0 { 48 compatible = "mmio-mux"; 49 reg = <0x0 0x4>; 50 #mux-control-cells = <1>; 51 mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ 52 }; 53 54 serdes_ln_ctrl: mux-controller@80 { 55 compatible = "mmio-mux"; 56 reg = <0x80 0x10>; 57 #mux-control-cells = <1>; 58 mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */ 59 <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */ 60 }; 61 62 ehrpwm_tbclk: clock-controller@140 { 63 compatible = "ti,am654-ehrpwm-tbclk"; 64 reg = <0x140 0x18>; 65 #clock-cells = <1>; 66 }; 67 }; 68 69 main_ehrpwm0: pwm@3000000 { 70 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 71 #pwm-cells = <3>; 72 reg = <0x00 0x3000000 0x00 0x100>; 73 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; 74 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 160 0>; 75 clock-names = "tbclk", "fck"; 76 status = "disabled"; 77 }; 78 79 main_ehrpwm1: pwm@3010000 { 80 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 81 #pwm-cells = <3>; 82 reg = <0x00 0x3010000 0x00 0x100>; 83 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 84 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 161 0>; 85 clock-names = "tbclk", "fck"; 86 status = "disabled"; 87 }; 88 89 main_ehrpwm2: pwm@3020000 { 90 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 91 #pwm-cells = <3>; 92 reg = <0x00 0x3020000 0x00 0x100>; 93 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 94 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 162 0>; 95 clock-names = "tbclk", "fck"; 96 status = "disabled"; 97 }; 98 99 main_ehrpwm3: pwm@3030000 { 100 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 101 #pwm-cells = <3>; 102 reg = <0x00 0x3030000 0x00 0x100>; 103 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; 104 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 163 0>; 105 clock-names = "tbclk", "fck"; 106 status = "disabled"; 107 }; 108 109 main_ehrpwm4: pwm@3040000 { 110 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 111 #pwm-cells = <3>; 112 reg = <0x00 0x3040000 0x00 0x100>; 113 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; 114 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 164 0>; 115 clock-names = "tbclk", "fck"; 116 status = "disabled"; 117 }; 118 119 main_ehrpwm5: pwm@3050000 { 120 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 121 #pwm-cells = <3>; 122 reg = <0x00 0x3050000 0x00 0x100>; 123 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; 124 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 165 0>; 125 clock-names = "tbclk", "fck"; 126 status = "disabled"; 127 }; 128 129 gic500: interrupt-controller@1800000 { 130 compatible = "arm,gic-v3"; 131 #address-cells = <2>; 132 #size-cells = <2>; 133 ranges; 134 #interrupt-cells = <3>; 135 interrupt-controller; 136 reg = <0x00 0x01800000 0x00 0x100000>, /* GICD */ 137 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 138 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 139 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 140 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 141 142 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 143 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 144 145 gic_its: msi-controller@1820000 { 146 compatible = "arm,gic-v3-its"; 147 reg = <0x00 0x01820000 0x00 0x10000>; 148 socionext,synquacer-pre-its = <0x1000000 0x400000>; 149 msi-controller; 150 #msi-cells = <1>; 151 }; 152 }; 153 154 main_gpio_intr: interrupt-controller@a00000 { 155 compatible = "ti,sci-intr"; 156 reg = <0x00 0x00a00000 0x00 0x800>; 157 ti,intr-trigger-type = <1>; 158 interrupt-controller; 159 interrupt-parent = <&gic500>; 160 #interrupt-cells = <1>; 161 ti,sci = <&sms>; 162 ti,sci-dev-id = <148>; 163 ti,interrupt-ranges = <8 392 56>; 164 }; 165 166 main_pmx0: pinctrl@11c000 { 167 compatible = "pinctrl-single"; 168 /* Proxy 0 addressing */ 169 reg = <0x0 0x11c000 0x0 0x120>; 170 #pinctrl-cells = <1>; 171 pinctrl-single,register-width = <32>; 172 pinctrl-single,function-mask = <0xffffffff>; 173 }; 174 175 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 176 main_timerio_input: pinctrl@104200 { 177 compatible = "pinctrl-single"; 178 reg = <0x00 0x104200 0x00 0x50>; 179 #pinctrl-cells = <1>; 180 pinctrl-single,register-width = <32>; 181 pinctrl-single,function-mask = <0x00000007>; 182 }; 183 184 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 185 main_timerio_output: pinctrl@104280 { 186 compatible = "pinctrl-single"; 187 reg = <0x00 0x104280 0x00 0x20>; 188 #pinctrl-cells = <1>; 189 pinctrl-single,register-width = <32>; 190 pinctrl-single,function-mask = <0x0000001f>; 191 }; 192 193 main_crypto: crypto@4e00000 { 194 compatible = "ti,j721e-sa2ul"; 195 reg = <0x00 0x04e00000 0x00 0x1200>; 196 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; 197 #address-cells = <2>; 198 #size-cells = <2>; 199 ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; 200 201 dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, 202 <&main_udmap 0x4a41>; 203 dma-names = "tx", "rx1", "rx2"; 204 205 rng: rng@4e10000 { 206 compatible = "inside-secure,safexcel-eip76"; 207 reg = <0x00 0x04e10000 0x00 0x7d>; 208 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 209 }; 210 }; 211 212 main_timer0: timer@2400000 { 213 compatible = "ti,am654-timer"; 214 reg = <0x00 0x2400000 0x00 0x400>; 215 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&k3_clks 63 1>; 217 clock-names = "fck"; 218 assigned-clocks = <&k3_clks 63 1>; 219 assigned-clock-parents = <&k3_clks 63 2>; 220 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; 221 ti,timer-pwm; 222 }; 223 224 main_timer1: timer@2410000 { 225 compatible = "ti,am654-timer"; 226 reg = <0x00 0x2410000 0x00 0x400>; 227 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&k3_clks 64 1>; 229 clock-names = "fck"; 230 assigned-clocks = <&k3_clks 64 1>; 231 assigned-clock-parents = <&k3_clks 64 2>; 232 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; 233 ti,timer-pwm; 234 }; 235 236 main_timer2: timer@2420000 { 237 compatible = "ti,am654-timer"; 238 reg = <0x00 0x2420000 0x00 0x400>; 239 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&k3_clks 65 1>; 241 clock-names = "fck"; 242 assigned-clocks = <&k3_clks 65 1>; 243 assigned-clock-parents = <&k3_clks 65 2>; 244 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; 245 ti,timer-pwm; 246 }; 247 248 main_timer3: timer@2430000 { 249 compatible = "ti,am654-timer"; 250 reg = <0x00 0x2430000 0x00 0x400>; 251 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&k3_clks 66 1>; 253 clock-names = "fck"; 254 assigned-clocks = <&k3_clks 66 1>; 255 assigned-clock-parents = <&k3_clks 66 2>; 256 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; 257 ti,timer-pwm; 258 }; 259 260 main_timer4: timer@2440000 { 261 compatible = "ti,am654-timer"; 262 reg = <0x00 0x2440000 0x00 0x400>; 263 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 264 clocks = <&k3_clks 67 1>; 265 clock-names = "fck"; 266 assigned-clocks = <&k3_clks 67 1>; 267 assigned-clock-parents = <&k3_clks 67 2>; 268 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; 269 ti,timer-pwm; 270 }; 271 272 main_timer5: timer@2450000 { 273 compatible = "ti,am654-timer"; 274 reg = <0x00 0x2450000 0x00 0x400>; 275 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 276 clocks = <&k3_clks 68 1>; 277 clock-names = "fck"; 278 assigned-clocks = <&k3_clks 68 1>; 279 assigned-clock-parents = <&k3_clks 68 2>; 280 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; 281 ti,timer-pwm; 282 }; 283 284 main_timer6: timer@2460000 { 285 compatible = "ti,am654-timer"; 286 reg = <0x00 0x2460000 0x00 0x400>; 287 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 288 clocks = <&k3_clks 69 1>; 289 clock-names = "fck"; 290 assigned-clocks = <&k3_clks 69 1>; 291 assigned-clock-parents = <&k3_clks 69 2>; 292 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; 293 ti,timer-pwm; 294 }; 295 296 main_timer7: timer@2470000 { 297 compatible = "ti,am654-timer"; 298 reg = <0x00 0x2470000 0x00 0x400>; 299 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 300 clocks = <&k3_clks 70 1>; 301 clock-names = "fck"; 302 assigned-clocks = <&k3_clks 70 1>; 303 assigned-clock-parents = <&k3_clks 70 2>; 304 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; 305 ti,timer-pwm; 306 }; 307 308 main_timer8: timer@2480000 { 309 compatible = "ti,am654-timer"; 310 reg = <0x00 0x2480000 0x00 0x400>; 311 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&k3_clks 71 1>; 313 clock-names = "fck"; 314 assigned-clocks = <&k3_clks 71 1>; 315 assigned-clock-parents = <&k3_clks 71 2>; 316 power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; 317 ti,timer-pwm; 318 }; 319 320 main_timer9: timer@2490000 { 321 compatible = "ti,am654-timer"; 322 reg = <0x00 0x2490000 0x00 0x400>; 323 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&k3_clks 72 1>; 325 clock-names = "fck"; 326 assigned-clocks = <&k3_clks 72 1>; 327 assigned-clock-parents = <&k3_clks 72 2>; 328 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; 329 ti,timer-pwm; 330 }; 331 332 main_timer10: timer@24a0000 { 333 compatible = "ti,am654-timer"; 334 reg = <0x00 0x24a0000 0x00 0x400>; 335 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&k3_clks 73 1>; 337 clock-names = "fck"; 338 assigned-clocks = <&k3_clks 73 1>; 339 assigned-clock-parents = <&k3_clks 73 2>; 340 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; 341 ti,timer-pwm; 342 }; 343 344 main_timer11: timer@24b0000 { 345 compatible = "ti,am654-timer"; 346 reg = <0x00 0x24b0000 0x00 0x400>; 347 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&k3_clks 74 1>; 349 clock-names = "fck"; 350 assigned-clocks = <&k3_clks 74 1>; 351 assigned-clock-parents = <&k3_clks 74 2>; 352 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; 353 ti,timer-pwm; 354 }; 355 356 main_timer12: timer@24c0000 { 357 compatible = "ti,am654-timer"; 358 reg = <0x00 0x24c0000 0x00 0x400>; 359 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&k3_clks 75 1>; 361 clock-names = "fck"; 362 assigned-clocks = <&k3_clks 75 1>; 363 assigned-clock-parents = <&k3_clks 75 2>; 364 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 365 ti,timer-pwm; 366 }; 367 368 main_timer13: timer@24d0000 { 369 compatible = "ti,am654-timer"; 370 reg = <0x00 0x24d0000 0x00 0x400>; 371 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 372 clocks = <&k3_clks 76 1>; 373 clock-names = "fck"; 374 assigned-clocks = <&k3_clks 76 1>; 375 assigned-clock-parents = <&k3_clks 76 2>; 376 power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>; 377 ti,timer-pwm; 378 }; 379 380 main_timer14: timer@24e0000 { 381 compatible = "ti,am654-timer"; 382 reg = <0x00 0x24e0000 0x00 0x400>; 383 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 384 clocks = <&k3_clks 77 1>; 385 clock-names = "fck"; 386 assigned-clocks = <&k3_clks 77 1>; 387 assigned-clock-parents = <&k3_clks 77 2>; 388 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 389 ti,timer-pwm; 390 }; 391 392 main_timer15: timer@24f0000 { 393 compatible = "ti,am654-timer"; 394 reg = <0x00 0x24f0000 0x00 0x400>; 395 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&k3_clks 78 1>; 397 clock-names = "fck"; 398 assigned-clocks = <&k3_clks 78 1>; 399 assigned-clock-parents = <&k3_clks 78 2>; 400 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 401 ti,timer-pwm; 402 }; 403 404 main_timer16: timer@2500000 { 405 compatible = "ti,am654-timer"; 406 reg = <0x00 0x2500000 0x00 0x400>; 407 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&k3_clks 79 1>; 409 clock-names = "fck"; 410 assigned-clocks = <&k3_clks 79 1>; 411 assigned-clock-parents = <&k3_clks 79 2>; 412 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; 413 ti,timer-pwm; 414 }; 415 416 main_timer17: timer@2510000 { 417 compatible = "ti,am654-timer"; 418 reg = <0x00 0x2510000 0x00 0x400>; 419 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&k3_clks 80 1>; 421 clock-names = "fck"; 422 assigned-clocks = <&k3_clks 80 1>; 423 assigned-clock-parents = <&k3_clks 80 2>; 424 power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; 425 ti,timer-pwm; 426 }; 427 428 main_timer18: timer@2520000 { 429 compatible = "ti,am654-timer"; 430 reg = <0x00 0x2520000 0x00 0x400>; 431 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&k3_clks 81 1>; 433 clock-names = "fck"; 434 assigned-clocks = <&k3_clks 81 1>; 435 assigned-clock-parents = <&k3_clks 81 2>; 436 power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; 437 ti,timer-pwm; 438 }; 439 440 main_timer19: timer@2530000 { 441 compatible = "ti,am654-timer"; 442 reg = <0x00 0x2530000 0x00 0x400>; 443 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&k3_clks 82 1>; 445 clock-names = "fck"; 446 assigned-clocks = <&k3_clks 82 1>; 447 assigned-clock-parents = <&k3_clks 82 2>; 448 power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>; 449 ti,timer-pwm; 450 }; 451 452 main_uart0: serial@2800000 { 453 compatible = "ti,j721e-uart", "ti,am654-uart"; 454 reg = <0x00 0x02800000 0x00 0x200>; 455 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 456 current-speed = <115200>; 457 clocks = <&k3_clks 146 3>; 458 clock-names = "fclk"; 459 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 460 status = "disabled"; 461 }; 462 463 main_uart1: serial@2810000 { 464 compatible = "ti,j721e-uart", "ti,am654-uart"; 465 reg = <0x00 0x02810000 0x00 0x200>; 466 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 467 current-speed = <115200>; 468 clocks = <&k3_clks 350 3>; 469 clock-names = "fclk"; 470 power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>; 471 status = "disabled"; 472 }; 473 474 main_uart2: serial@2820000 { 475 compatible = "ti,j721e-uart", "ti,am654-uart"; 476 reg = <0x00 0x02820000 0x00 0x200>; 477 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 478 current-speed = <115200>; 479 clocks = <&k3_clks 351 3>; 480 clock-names = "fclk"; 481 power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>; 482 status = "disabled"; 483 }; 484 485 main_uart3: serial@2830000 { 486 compatible = "ti,j721e-uart", "ti,am654-uart"; 487 reg = <0x00 0x02830000 0x00 0x200>; 488 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 489 current-speed = <115200>; 490 clocks = <&k3_clks 352 3>; 491 clock-names = "fclk"; 492 power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; 493 status = "disabled"; 494 }; 495 496 main_uart4: serial@2840000 { 497 compatible = "ti,j721e-uart", "ti,am654-uart"; 498 reg = <0x00 0x02840000 0x00 0x200>; 499 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 500 current-speed = <115200>; 501 clocks = <&k3_clks 353 3>; 502 clock-names = "fclk"; 503 power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; 504 status = "disabled"; 505 }; 506 507 main_uart5: serial@2850000 { 508 compatible = "ti,j721e-uart", "ti,am654-uart"; 509 reg = <0x00 0x02850000 0x00 0x200>; 510 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 511 current-speed = <115200>; 512 clocks = <&k3_clks 354 3>; 513 clock-names = "fclk"; 514 power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; 515 status = "disabled"; 516 }; 517 518 main_uart6: serial@2860000 { 519 compatible = "ti,j721e-uart", "ti,am654-uart"; 520 reg = <0x00 0x02860000 0x00 0x200>; 521 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 522 current-speed = <115200>; 523 clocks = <&k3_clks 355 3>; 524 clock-names = "fclk"; 525 power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; 526 status = "disabled"; 527 }; 528 529 main_uart7: serial@2870000 { 530 compatible = "ti,j721e-uart", "ti,am654-uart"; 531 reg = <0x00 0x02870000 0x00 0x200>; 532 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 533 current-speed = <115200>; 534 clocks = <&k3_clks 356 3>; 535 clock-names = "fclk"; 536 power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>; 537 status = "disabled"; 538 }; 539 540 main_uart8: serial@2880000 { 541 compatible = "ti,j721e-uart", "ti,am654-uart"; 542 reg = <0x00 0x02880000 0x00 0x200>; 543 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 544 current-speed = <115200>; 545 clocks = <&k3_clks 357 3>; 546 clock-names = "fclk"; 547 power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>; 548 status = "disabled"; 549 }; 550 551 main_uart9: serial@2890000 { 552 compatible = "ti,j721e-uart", "ti,am654-uart"; 553 reg = <0x00 0x02890000 0x00 0x200>; 554 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 555 current-speed = <115200>; 556 clocks = <&k3_clks 358 3>; 557 clock-names = "fclk"; 558 power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>; 559 status = "disabled"; 560 }; 561 562 main_gpio0: gpio@600000 { 563 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 564 reg = <0x00 0x00600000 0x00 0x100>; 565 gpio-controller; 566 #gpio-cells = <2>; 567 interrupt-parent = <&main_gpio_intr>; 568 interrupts = <145>, <146>, <147>, <148>, <149>; 569 interrupt-controller; 570 #interrupt-cells = <2>; 571 ti,ngpio = <66>; 572 ti,davinci-gpio-unbanked = <0>; 573 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 574 clocks = <&k3_clks 111 0>; 575 clock-names = "gpio"; 576 }; 577 578 main_gpio2: gpio@610000 { 579 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 580 reg = <0x00 0x00610000 0x00 0x100>; 581 gpio-controller; 582 #gpio-cells = <2>; 583 interrupt-parent = <&main_gpio_intr>; 584 interrupts = <154>, <155>, <156>, <157>, <158>; 585 interrupt-controller; 586 #interrupt-cells = <2>; 587 ti,ngpio = <66>; 588 ti,davinci-gpio-unbanked = <0>; 589 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 590 clocks = <&k3_clks 112 0>; 591 clock-names = "gpio"; 592 }; 593 594 main_gpio4: gpio@620000 { 595 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 596 reg = <0x00 0x00620000 0x00 0x100>; 597 gpio-controller; 598 #gpio-cells = <2>; 599 interrupt-parent = <&main_gpio_intr>; 600 interrupts = <163>, <164>, <165>, <166>, <167>; 601 interrupt-controller; 602 #interrupt-cells = <2>; 603 ti,ngpio = <66>; 604 ti,davinci-gpio-unbanked = <0>; 605 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 606 clocks = <&k3_clks 113 0>; 607 clock-names = "gpio"; 608 }; 609 610 main_gpio6: gpio@630000 { 611 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 612 reg = <0x00 0x00630000 0x00 0x100>; 613 gpio-controller; 614 #gpio-cells = <2>; 615 interrupt-parent = <&main_gpio_intr>; 616 interrupts = <172>, <173>, <174>, <175>, <176>; 617 interrupt-controller; 618 #interrupt-cells = <2>; 619 ti,ngpio = <66>; 620 ti,davinci-gpio-unbanked = <0>; 621 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 622 clocks = <&k3_clks 114 0>; 623 clock-names = "gpio"; 624 }; 625 626 main_i2c0: i2c@2000000 { 627 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 628 reg = <0x00 0x02000000 0x00 0x100>; 629 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 630 #address-cells = <1>; 631 #size-cells = <0>; 632 clocks = <&k3_clks 214 1>; 633 clock-names = "fck"; 634 power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>; 635 }; 636 637 main_i2c1: i2c@2010000 { 638 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 639 reg = <0x00 0x02010000 0x00 0x100>; 640 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 641 #address-cells = <1>; 642 #size-cells = <0>; 643 clocks = <&k3_clks 215 1>; 644 clock-names = "fck"; 645 power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>; 646 status = "disabled"; 647 }; 648 649 main_i2c2: i2c@2020000 { 650 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 651 reg = <0x00 0x02020000 0x00 0x100>; 652 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 653 #address-cells = <1>; 654 #size-cells = <0>; 655 clocks = <&k3_clks 216 1>; 656 clock-names = "fck"; 657 power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>; 658 status = "disabled"; 659 }; 660 661 main_i2c3: i2c@2030000 { 662 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 663 reg = <0x00 0x02030000 0x00 0x100>; 664 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 665 #address-cells = <1>; 666 #size-cells = <0>; 667 clocks = <&k3_clks 217 1>; 668 clock-names = "fck"; 669 power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; 670 status = "disabled"; 671 }; 672 673 main_i2c4: i2c@2040000 { 674 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 675 reg = <0x00 0x02040000 0x00 0x100>; 676 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 677 #address-cells = <1>; 678 #size-cells = <0>; 679 clocks = <&k3_clks 218 1>; 680 clock-names = "fck"; 681 power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; 682 status = "disabled"; 683 }; 684 685 main_i2c5: i2c@2050000 { 686 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 687 reg = <0x00 0x02050000 0x00 0x100>; 688 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 689 #address-cells = <1>; 690 #size-cells = <0>; 691 clocks = <&k3_clks 219 1>; 692 clock-names = "fck"; 693 power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>; 694 status = "disabled"; 695 }; 696 697 main_i2c6: i2c@2060000 { 698 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 699 reg = <0x00 0x02060000 0x00 0x100>; 700 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 701 #address-cells = <1>; 702 #size-cells = <0>; 703 clocks = <&k3_clks 220 1>; 704 clock-names = "fck"; 705 power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>; 706 status = "disabled"; 707 }; 708 709 main_sdhci0: mmc@4f80000 { 710 compatible = "ti,j721e-sdhci-8bit"; 711 reg = <0x00 0x04f80000 0x00 0x1000>, 712 <0x00 0x04f88000 0x00 0x400>; 713 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 714 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 715 clocks = <&k3_clks 98 7>, <&k3_clks 98 1>; 716 clock-names = "clk_ahb", "clk_xin"; 717 assigned-clocks = <&k3_clks 98 1>; 718 assigned-clock-parents = <&k3_clks 98 2>; 719 bus-width = <8>; 720 ti,otap-del-sel-legacy = <0x0>; 721 ti,otap-del-sel-mmc-hs = <0x0>; 722 ti,otap-del-sel-ddr52 = <0x6>; 723 ti,otap-del-sel-hs200 = <0x8>; 724 ti,otap-del-sel-hs400 = <0x5>; 725 ti,itap-del-sel-legacy = <0x10>; 726 ti,itap-del-sel-mmc-hs = <0xa>; 727 ti,strobe-sel = <0x77>; 728 ti,clkbuf-sel = <0x7>; 729 ti,trm-icp = <0x8>; 730 mmc-ddr-1_8v; 731 mmc-hs200-1_8v; 732 mmc-hs400-1_8v; 733 dma-coherent; 734 }; 735 736 main_sdhci1: mmc@4fb0000 { 737 compatible = "ti,j721e-sdhci-4bit"; 738 reg = <0x00 0x04fb0000 0x00 0x1000>, 739 <0x00 0x04fb8000 0x00 0x400>; 740 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 741 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 742 clocks = <&k3_clks 99 8>, <&k3_clks 99 1>; 743 clock-names = "clk_ahb", "clk_xin"; 744 assigned-clocks = <&k3_clks 99 1>; 745 assigned-clock-parents = <&k3_clks 99 2>; 746 bus-width = <4>; 747 ti,otap-del-sel-legacy = <0x0>; 748 ti,otap-del-sel-sd-hs = <0x0>; 749 ti,otap-del-sel-sdr12 = <0xf>; 750 ti,otap-del-sel-sdr25 = <0xf>; 751 ti,otap-del-sel-sdr50 = <0xc>; 752 ti,otap-del-sel-sdr104 = <0x5>; 753 ti,otap-del-sel-ddr50 = <0xc>; 754 ti,itap-del-sel-legacy = <0x0>; 755 ti,itap-del-sel-sd-hs = <0x0>; 756 ti,itap-del-sel-sdr12 = <0x0>; 757 ti,itap-del-sel-sdr25 = <0x0>; 758 ti,clkbuf-sel = <0x7>; 759 ti,trm-icp = <0x8>; 760 dma-coherent; 761 /* Masking support for SDR104 capability */ 762 sdhci-caps-mask = <0x00000003 0x00000000>; 763 }; 764 765 main_navss: bus@30000000 { 766 compatible = "simple-mfd"; 767 #address-cells = <2>; 768 #size-cells = <2>; 769 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 770 ti,sci-dev-id = <224>; 771 dma-coherent; 772 dma-ranges; 773 774 main_navss_intr: interrupt-controller@310e0000 { 775 compatible = "ti,sci-intr"; 776 reg = <0x00 0x310e0000 0x00 0x4000>; 777 ti,intr-trigger-type = <4>; 778 interrupt-controller; 779 interrupt-parent = <&gic500>; 780 #interrupt-cells = <1>; 781 ti,sci = <&sms>; 782 ti,sci-dev-id = <227>; 783 ti,interrupt-ranges = <0 64 64>, 784 <64 448 64>, 785 <128 672 64>; 786 }; 787 788 main_udmass_inta: msi-controller@33d00000 { 789 compatible = "ti,sci-inta"; 790 reg = <0x00 0x33d00000 0x00 0x100000>; 791 interrupt-controller; 792 #interrupt-cells = <0>; 793 interrupt-parent = <&main_navss_intr>; 794 msi-controller; 795 ti,sci = <&sms>; 796 ti,sci-dev-id = <265>; 797 ti,interrupt-ranges = <0 0 256>; 798 }; 799 800 secure_proxy_main: mailbox@32c00000 { 801 compatible = "ti,am654-secure-proxy"; 802 #mbox-cells = <1>; 803 reg-names = "target_data", "rt", "scfg"; 804 reg = <0x00 0x32c00000 0x00 0x100000>, 805 <0x00 0x32400000 0x00 0x100000>, 806 <0x00 0x32800000 0x00 0x100000>; 807 interrupt-names = "rx_011"; 808 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 809 }; 810 811 hwspinlock: spinlock@30e00000 { 812 compatible = "ti,am654-hwspinlock"; 813 reg = <0x00 0x30e00000 0x00 0x1000>; 814 #hwlock-cells = <1>; 815 }; 816 817 mailbox0_cluster0: mailbox@31f80000 { 818 compatible = "ti,am654-mailbox"; 819 reg = <0x00 0x31f80000 0x00 0x200>; 820 #mbox-cells = <1>; 821 ti,mbox-num-users = <4>; 822 ti,mbox-num-fifos = <16>; 823 interrupt-parent = <&main_navss_intr>; 824 status = "disabled"; 825 }; 826 827 mailbox0_cluster1: mailbox@31f81000 { 828 compatible = "ti,am654-mailbox"; 829 reg = <0x00 0x31f81000 0x00 0x200>; 830 #mbox-cells = <1>; 831 ti,mbox-num-users = <4>; 832 ti,mbox-num-fifos = <16>; 833 interrupt-parent = <&main_navss_intr>; 834 status = "disabled"; 835 }; 836 837 mailbox0_cluster2: mailbox@31f82000 { 838 compatible = "ti,am654-mailbox"; 839 reg = <0x00 0x31f82000 0x00 0x200>; 840 #mbox-cells = <1>; 841 ti,mbox-num-users = <4>; 842 ti,mbox-num-fifos = <16>; 843 interrupt-parent = <&main_navss_intr>; 844 status = "disabled"; 845 }; 846 847 mailbox0_cluster3: mailbox@31f83000 { 848 compatible = "ti,am654-mailbox"; 849 reg = <0x00 0x31f83000 0x00 0x200>; 850 #mbox-cells = <1>; 851 ti,mbox-num-users = <4>; 852 ti,mbox-num-fifos = <16>; 853 interrupt-parent = <&main_navss_intr>; 854 status = "disabled"; 855 }; 856 857 mailbox0_cluster4: mailbox@31f84000 { 858 compatible = "ti,am654-mailbox"; 859 reg = <0x00 0x31f84000 0x00 0x200>; 860 #mbox-cells = <1>; 861 ti,mbox-num-users = <4>; 862 ti,mbox-num-fifos = <16>; 863 interrupt-parent = <&main_navss_intr>; 864 status = "disabled"; 865 }; 866 867 mailbox0_cluster5: mailbox@31f85000 { 868 compatible = "ti,am654-mailbox"; 869 reg = <0x00 0x31f85000 0x00 0x200>; 870 #mbox-cells = <1>; 871 ti,mbox-num-users = <4>; 872 ti,mbox-num-fifos = <16>; 873 interrupt-parent = <&main_navss_intr>; 874 status = "disabled"; 875 }; 876 877 mailbox0_cluster6: mailbox@31f86000 { 878 compatible = "ti,am654-mailbox"; 879 reg = <0x00 0x31f86000 0x00 0x200>; 880 #mbox-cells = <1>; 881 ti,mbox-num-users = <4>; 882 ti,mbox-num-fifos = <16>; 883 interrupt-parent = <&main_navss_intr>; 884 status = "disabled"; 885 }; 886 887 mailbox0_cluster7: mailbox@31f87000 { 888 compatible = "ti,am654-mailbox"; 889 reg = <0x00 0x31f87000 0x00 0x200>; 890 #mbox-cells = <1>; 891 ti,mbox-num-users = <4>; 892 ti,mbox-num-fifos = <16>; 893 interrupt-parent = <&main_navss_intr>; 894 status = "disabled"; 895 }; 896 897 mailbox0_cluster8: mailbox@31f88000 { 898 compatible = "ti,am654-mailbox"; 899 reg = <0x00 0x31f88000 0x00 0x200>; 900 #mbox-cells = <1>; 901 ti,mbox-num-users = <4>; 902 ti,mbox-num-fifos = <16>; 903 interrupt-parent = <&main_navss_intr>; 904 status = "disabled"; 905 }; 906 907 mailbox0_cluster9: mailbox@31f89000 { 908 compatible = "ti,am654-mailbox"; 909 reg = <0x00 0x31f89000 0x00 0x200>; 910 #mbox-cells = <1>; 911 ti,mbox-num-users = <4>; 912 ti,mbox-num-fifos = <16>; 913 interrupt-parent = <&main_navss_intr>; 914 status = "disabled"; 915 }; 916 917 mailbox0_cluster10: mailbox@31f8a000 { 918 compatible = "ti,am654-mailbox"; 919 reg = <0x00 0x31f8a000 0x00 0x200>; 920 #mbox-cells = <1>; 921 ti,mbox-num-users = <4>; 922 ti,mbox-num-fifos = <16>; 923 interrupt-parent = <&main_navss_intr>; 924 status = "disabled"; 925 }; 926 927 mailbox0_cluster11: mailbox@31f8b000 { 928 compatible = "ti,am654-mailbox"; 929 reg = <0x00 0x31f8b000 0x00 0x200>; 930 #mbox-cells = <1>; 931 ti,mbox-num-users = <4>; 932 ti,mbox-num-fifos = <16>; 933 interrupt-parent = <&main_navss_intr>; 934 status = "disabled"; 935 }; 936 937 mailbox1_cluster0: mailbox@31f90000 { 938 compatible = "ti,am654-mailbox"; 939 reg = <0x00 0x31f90000 0x00 0x200>; 940 #mbox-cells = <1>; 941 ti,mbox-num-users = <4>; 942 ti,mbox-num-fifos = <16>; 943 interrupt-parent = <&main_navss_intr>; 944 status = "disabled"; 945 }; 946 947 mailbox1_cluster1: mailbox@31f91000 { 948 compatible = "ti,am654-mailbox"; 949 reg = <0x00 0x31f91000 0x00 0x200>; 950 #mbox-cells = <1>; 951 ti,mbox-num-users = <4>; 952 ti,mbox-num-fifos = <16>; 953 interrupt-parent = <&main_navss_intr>; 954 status = "disabled"; 955 }; 956 957 mailbox1_cluster2: mailbox@31f92000 { 958 compatible = "ti,am654-mailbox"; 959 reg = <0x00 0x31f92000 0x00 0x200>; 960 #mbox-cells = <1>; 961 ti,mbox-num-users = <4>; 962 ti,mbox-num-fifos = <16>; 963 interrupt-parent = <&main_navss_intr>; 964 status = "disabled"; 965 }; 966 967 mailbox1_cluster3: mailbox@31f93000 { 968 compatible = "ti,am654-mailbox"; 969 reg = <0x00 0x31f93000 0x00 0x200>; 970 #mbox-cells = <1>; 971 ti,mbox-num-users = <4>; 972 ti,mbox-num-fifos = <16>; 973 interrupt-parent = <&main_navss_intr>; 974 status = "disabled"; 975 }; 976 977 mailbox1_cluster4: mailbox@31f94000 { 978 compatible = "ti,am654-mailbox"; 979 reg = <0x00 0x31f94000 0x00 0x200>; 980 #mbox-cells = <1>; 981 ti,mbox-num-users = <4>; 982 ti,mbox-num-fifos = <16>; 983 interrupt-parent = <&main_navss_intr>; 984 status = "disabled"; 985 }; 986 987 mailbox1_cluster5: mailbox@31f95000 { 988 compatible = "ti,am654-mailbox"; 989 reg = <0x00 0x31f95000 0x00 0x200>; 990 #mbox-cells = <1>; 991 ti,mbox-num-users = <4>; 992 ti,mbox-num-fifos = <16>; 993 interrupt-parent = <&main_navss_intr>; 994 status = "disabled"; 995 }; 996 997 mailbox1_cluster6: mailbox@31f96000 { 998 compatible = "ti,am654-mailbox"; 999 reg = <0x00 0x31f96000 0x00 0x200>; 1000 #mbox-cells = <1>; 1001 ti,mbox-num-users = <4>; 1002 ti,mbox-num-fifos = <16>; 1003 interrupt-parent = <&main_navss_intr>; 1004 status = "disabled"; 1005 }; 1006 1007 mailbox1_cluster7: mailbox@31f97000 { 1008 compatible = "ti,am654-mailbox"; 1009 reg = <0x00 0x31f97000 0x00 0x200>; 1010 #mbox-cells = <1>; 1011 ti,mbox-num-users = <4>; 1012 ti,mbox-num-fifos = <16>; 1013 interrupt-parent = <&main_navss_intr>; 1014 status = "disabled"; 1015 }; 1016 1017 mailbox1_cluster8: mailbox@31f98000 { 1018 compatible = "ti,am654-mailbox"; 1019 reg = <0x00 0x31f98000 0x00 0x200>; 1020 #mbox-cells = <1>; 1021 ti,mbox-num-users = <4>; 1022 ti,mbox-num-fifos = <16>; 1023 interrupt-parent = <&main_navss_intr>; 1024 status = "disabled"; 1025 }; 1026 1027 mailbox1_cluster9: mailbox@31f99000 { 1028 compatible = "ti,am654-mailbox"; 1029 reg = <0x00 0x31f99000 0x00 0x200>; 1030 #mbox-cells = <1>; 1031 ti,mbox-num-users = <4>; 1032 ti,mbox-num-fifos = <16>; 1033 interrupt-parent = <&main_navss_intr>; 1034 status = "disabled"; 1035 }; 1036 1037 mailbox1_cluster10: mailbox@31f9a000 { 1038 compatible = "ti,am654-mailbox"; 1039 reg = <0x00 0x31f9a000 0x00 0x200>; 1040 #mbox-cells = <1>; 1041 ti,mbox-num-users = <4>; 1042 ti,mbox-num-fifos = <16>; 1043 interrupt-parent = <&main_navss_intr>; 1044 status = "disabled"; 1045 }; 1046 1047 mailbox1_cluster11: mailbox@31f9b000 { 1048 compatible = "ti,am654-mailbox"; 1049 reg = <0x00 0x31f9b000 0x00 0x200>; 1050 #mbox-cells = <1>; 1051 ti,mbox-num-users = <4>; 1052 ti,mbox-num-fifos = <16>; 1053 interrupt-parent = <&main_navss_intr>; 1054 status = "disabled"; 1055 }; 1056 1057 main_ringacc: ringacc@3c000000 { 1058 compatible = "ti,am654-navss-ringacc"; 1059 reg = <0x0 0x3c000000 0x0 0x400000>, 1060 <0x0 0x38000000 0x0 0x400000>, 1061 <0x0 0x31120000 0x0 0x100>, 1062 <0x0 0x33000000 0x0 0x40000>; 1063 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 1064 ti,num-rings = <1024>; 1065 ti,sci-rm-range-gp-rings = <0x1>; 1066 ti,sci = <&sms>; 1067 ti,sci-dev-id = <259>; 1068 msi-parent = <&main_udmass_inta>; 1069 }; 1070 1071 main_udmap: dma-controller@31150000 { 1072 compatible = "ti,j721e-navss-main-udmap"; 1073 reg = <0x0 0x31150000 0x0 0x100>, 1074 <0x0 0x34000000 0x0 0x80000>, 1075 <0x0 0x35000000 0x0 0x200000>; 1076 reg-names = "gcfg", "rchanrt", "tchanrt"; 1077 msi-parent = <&main_udmass_inta>; 1078 #dma-cells = <1>; 1079 1080 ti,sci = <&sms>; 1081 ti,sci-dev-id = <263>; 1082 ti,ringacc = <&main_ringacc>; 1083 1084 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 1085 <0x0f>, /* TX_HCHAN */ 1086 <0x10>; /* TX_UHCHAN */ 1087 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 1088 <0x0b>, /* RX_HCHAN */ 1089 <0x0c>; /* RX_UHCHAN */ 1090 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 1091 }; 1092 1093 cpts@310d0000 { 1094 compatible = "ti,j721e-cpts"; 1095 reg = <0x0 0x310d0000 0x0 0x400>; 1096 reg-names = "cpts"; 1097 clocks = <&k3_clks 226 5>; 1098 clock-names = "cpts"; 1099 assigned-clocks = <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */ 1100 assigned-clock-parents = <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */ 1101 interrupts-extended = <&main_navss_intr 391>; 1102 interrupt-names = "cpts"; 1103 ti,cpts-periodic-outputs = <6>; 1104 ti,cpts-ext-ts-inputs = <8>; 1105 }; 1106 }; 1107 1108 usbss0: cdns-usb@4104000 { 1109 compatible = "ti,j721e-usb"; 1110 reg = <0x00 0x04104000 0x00 0x100>; 1111 clocks = <&k3_clks 360 16>, <&k3_clks 360 15>; 1112 clock-names = "ref", "lpm"; 1113 assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */ 1114 assigned-clock-parents = <&k3_clks 360 17>; 1115 power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; 1116 #address-cells = <2>; 1117 #size-cells = <2>; 1118 ranges; 1119 dma-coherent; 1120 1121 status = "disabled"; /* Needs pinmux */ 1122 1123 usb0: usb@6000000 { 1124 compatible = "cdns,usb3"; 1125 reg = <0x00 0x06000000 0x00 0x10000>, 1126 <0x00 0x06010000 0x00 0x10000>, 1127 <0x00 0x06020000 0x00 0x10000>; 1128 reg-names = "otg", "xhci", "dev"; 1129 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1130 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1132 interrupt-names = "host", "peripheral", "otg"; 1133 maximum-speed = "super-speed"; 1134 dr_mode = "otg"; 1135 }; 1136 }; 1137 1138 serdes_wiz0: wiz@5060000 { 1139 compatible = "ti,j721s2-wiz-10g"; 1140 #address-cells = <1>; 1141 #size-cells = <1>; 1142 power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; 1143 clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>; 1144 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 1145 num-lanes = <4>; 1146 #reset-cells = <1>; 1147 #clock-cells = <1>; 1148 ranges = <0x5060000 0x0 0x5060000 0x10000>; 1149 1150 assigned-clocks = <&k3_clks 365 3>; 1151 assigned-clock-parents = <&k3_clks 365 7>; 1152 1153 serdes0: serdes@5060000 { 1154 compatible = "ti,j721e-serdes-10g"; 1155 reg = <0x05060000 0x00010000>; 1156 reg-names = "torrent_phy"; 1157 resets = <&serdes_wiz0 0>; 1158 reset-names = "torrent_reset"; 1159 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1160 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; 1161 clock-names = "refclk", "phy_en_refclk"; 1162 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1163 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, 1164 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; 1165 assigned-clock-parents = <&k3_clks 365 3>, 1166 <&k3_clks 365 3>, 1167 <&k3_clks 365 3>; 1168 #address-cells = <1>; 1169 #size-cells = <0>; 1170 #clock-cells = <1>; 1171 1172 status = "disabled"; /* Needs lane config */ 1173 }; 1174 }; 1175 1176 pcie1_rc: pcie@2910000 { 1177 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; 1178 reg = <0x00 0x02910000 0x00 0x1000>, 1179 <0x00 0x02917000 0x00 0x400>, 1180 <0x00 0x0d800000 0x00 0x800000>, 1181 <0x00 0x18000000 0x00 0x1000>; 1182 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1183 interrupt-names = "link_state"; 1184 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 1185 device_type = "pci"; 1186 ti,syscon-pcie-ctrl = <&scm_conf 0x074>; 1187 max-link-speed = <3>; 1188 num-lanes = <4>; 1189 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 1190 clocks = <&k3_clks 276 41>; 1191 clock-names = "fck"; 1192 #address-cells = <3>; 1193 #size-cells = <2>; 1194 bus-range = <0x0 0xff>; 1195 vendor-id = <0x104c>; 1196 device-id = <0xb013>; 1197 msi-map = <0x0 &gic_its 0x0 0x10000>; 1198 dma-coherent; 1199 ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, 1200 <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; 1201 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 1202 #interrupt-cells = <1>; 1203 interrupt-map-mask = <0 0 0 7>; 1204 interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */ 1205 <0 0 0 2 &pcie1_intc 0>, /* INT B */ 1206 <0 0 0 3 &pcie1_intc 0>, /* INT C */ 1207 <0 0 0 4 &pcie1_intc 0>; /* INT D */ 1208 1209 status = "disabled"; /* Needs gpio and serdes info */ 1210 1211 pcie1_intc: interrupt-controller { 1212 interrupt-controller; 1213 #interrupt-cells = <1>; 1214 interrupt-parent = <&gic500>; 1215 interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>; 1216 }; 1217 }; 1218 1219 main_mcan0: can@2701000 { 1220 compatible = "bosch,m_can"; 1221 reg = <0x00 0x02701000 0x00 0x200>, 1222 <0x00 0x02708000 0x00 0x8000>; 1223 reg-names = "m_can", "message_ram"; 1224 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1225 clocks = <&k3_clks 182 0>, <&k3_clks 182 1>; 1226 clock-names = "hclk", "cclk"; 1227 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1229 interrupt-names = "int0", "int1"; 1230 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1231 status = "disabled"; 1232 }; 1233 1234 main_mcan1: can@2711000 { 1235 compatible = "bosch,m_can"; 1236 reg = <0x00 0x02711000 0x00 0x200>, 1237 <0x00 0x02718000 0x00 0x8000>; 1238 reg-names = "m_can", "message_ram"; 1239 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; 1240 clocks = <&k3_clks 183 0>, <&k3_clks 183 1>; 1241 clock-names = "hclk", "cclk"; 1242 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 1244 interrupt-names = "int0", "int1"; 1245 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1246 status = "disabled"; 1247 }; 1248 1249 main_mcan2: can@2721000 { 1250 compatible = "bosch,m_can"; 1251 reg = <0x00 0x02721000 0x00 0x200>, 1252 <0x00 0x02728000 0x00 0x8000>; 1253 reg-names = "m_can", "message_ram"; 1254 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 1255 clocks = <&k3_clks 184 0>, <&k3_clks 184 1>; 1256 clock-names = "hclk", "cclk"; 1257 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1258 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1259 interrupt-names = "int0", "int1"; 1260 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1261 status = "disabled"; 1262 }; 1263 1264 main_mcan3: can@2731000 { 1265 compatible = "bosch,m_can"; 1266 reg = <0x00 0x02731000 0x00 0x200>, 1267 <0x00 0x02738000 0x00 0x8000>; 1268 reg-names = "m_can", "message_ram"; 1269 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1270 clocks = <&k3_clks 185 0>, <&k3_clks 185 1>; 1271 clock-names = "hclk", "cclk"; 1272 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1274 interrupt-names = "int0", "int1"; 1275 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1276 status = "disabled"; 1277 }; 1278 1279 main_mcan4: can@2741000 { 1280 compatible = "bosch,m_can"; 1281 reg = <0x00 0x02741000 0x00 0x200>, 1282 <0x00 0x02748000 0x00 0x8000>; 1283 reg-names = "m_can", "message_ram"; 1284 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; 1285 clocks = <&k3_clks 186 0>, <&k3_clks 186 1>; 1286 clock-names = "hclk", "cclk"; 1287 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1288 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1289 interrupt-names = "int0", "int1"; 1290 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1291 status = "disabled"; 1292 }; 1293 1294 main_mcan5: can@2751000 { 1295 compatible = "bosch,m_can"; 1296 reg = <0x00 0x02751000 0x00 0x200>, 1297 <0x00 0x02758000 0x00 0x8000>; 1298 reg-names = "m_can", "message_ram"; 1299 power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>; 1300 clocks = <&k3_clks 187 0>, <&k3_clks 187 1>; 1301 clock-names = "hclk", "cclk"; 1302 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1303 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1304 interrupt-names = "int0", "int1"; 1305 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1306 status = "disabled"; 1307 }; 1308 1309 main_mcan6: can@2761000 { 1310 compatible = "bosch,m_can"; 1311 reg = <0x00 0x02761000 0x00 0x200>, 1312 <0x00 0x02768000 0x00 0x8000>; 1313 reg-names = "m_can", "message_ram"; 1314 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 1315 clocks = <&k3_clks 188 0>, <&k3_clks 188 1>; 1316 clock-names = "hclk", "cclk"; 1317 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1318 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1319 interrupt-names = "int0", "int1"; 1320 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1321 status = "disabled"; 1322 }; 1323 1324 main_mcan7: can@2771000 { 1325 compatible = "bosch,m_can"; 1326 reg = <0x00 0x02771000 0x00 0x200>, 1327 <0x00 0x02778000 0x00 0x8000>; 1328 reg-names = "m_can", "message_ram"; 1329 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 1330 clocks = <&k3_clks 189 0>, <&k3_clks 189 1>; 1331 clock-names = "hclk", "cclk"; 1332 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1333 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1334 interrupt-names = "int0", "int1"; 1335 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1336 status = "disabled"; 1337 }; 1338 1339 main_mcan8: can@2781000 { 1340 compatible = "bosch,m_can"; 1341 reg = <0x00 0x02781000 0x00 0x200>, 1342 <0x00 0x02788000 0x00 0x8000>; 1343 reg-names = "m_can", "message_ram"; 1344 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 1345 clocks = <&k3_clks 190 0>, <&k3_clks 190 1>; 1346 clock-names = "hclk", "cclk"; 1347 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 1348 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 1349 interrupt-names = "int0", "int1"; 1350 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1351 status = "disabled"; 1352 }; 1353 1354 main_mcan9: can@2791000 { 1355 compatible = "bosch,m_can"; 1356 reg = <0x00 0x02791000 0x00 0x200>, 1357 <0x00 0x02798000 0x00 0x8000>; 1358 reg-names = "m_can", "message_ram"; 1359 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1360 clocks = <&k3_clks 191 0>, <&k3_clks 191 1>; 1361 clock-names = "hclk", "cclk"; 1362 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, 1363 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 1364 interrupt-names = "int0", "int1"; 1365 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1366 status = "disabled"; 1367 }; 1368 1369 main_mcan10: can@27a1000 { 1370 compatible = "bosch,m_can"; 1371 reg = <0x00 0x027a1000 0x00 0x200>, 1372 <0x00 0x027a8000 0x00 0x8000>; 1373 reg-names = "m_can", "message_ram"; 1374 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1375 clocks = <&k3_clks 192 0>, <&k3_clks 192 1>; 1376 clock-names = "hclk", "cclk"; 1377 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1379 interrupt-names = "int0", "int1"; 1380 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1381 status = "disabled"; 1382 }; 1383 1384 main_mcan11: can@27b1000 { 1385 compatible = "bosch,m_can"; 1386 reg = <0x00 0x027b1000 0x00 0x200>, 1387 <0x00 0x027b8000 0x00 0x8000>; 1388 reg-names = "m_can", "message_ram"; 1389 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 1390 clocks = <&k3_clks 193 0>, <&k3_clks 193 1>; 1391 clock-names = "hclk", "cclk"; 1392 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 1393 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1394 interrupt-names = "int0", "int1"; 1395 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1396 status = "disabled"; 1397 }; 1398 1399 main_mcan12: can@27c1000 { 1400 compatible = "bosch,m_can"; 1401 reg = <0x00 0x027c1000 0x00 0x200>, 1402 <0x00 0x027c8000 0x00 0x8000>; 1403 reg-names = "m_can", "message_ram"; 1404 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; 1405 clocks = <&k3_clks 194 0>, <&k3_clks 194 1>; 1406 clock-names = "hclk", "cclk"; 1407 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1408 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 1409 interrupt-names = "int0", "int1"; 1410 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1411 status = "disabled"; 1412 }; 1413 1414 main_mcan13: can@27d1000 { 1415 compatible = "bosch,m_can"; 1416 reg = <0x00 0x027d1000 0x00 0x200>, 1417 <0x00 0x027d8000 0x00 0x8000>; 1418 reg-names = "m_can", "message_ram"; 1419 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; 1420 clocks = <&k3_clks 195 0>, <&k3_clks 195 1>; 1421 clock-names = "hclk", "cclk"; 1422 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1423 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 1424 interrupt-names = "int0", "int1"; 1425 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1426 status = "disabled"; 1427 }; 1428 1429 main_mcan14: can@2681000 { 1430 compatible = "bosch,m_can"; 1431 reg = <0x00 0x02681000 0x00 0x200>, 1432 <0x00 0x02688000 0x00 0x8000>; 1433 reg-names = "m_can", "message_ram"; 1434 power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>; 1435 clocks = <&k3_clks 197 0>, <&k3_clks 197 1>; 1436 clock-names = "hclk", "cclk"; 1437 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1438 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>; 1439 interrupt-names = "int0", "int1"; 1440 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1441 status = "disabled"; 1442 }; 1443 1444 main_mcan15: can@2691000 { 1445 compatible = "bosch,m_can"; 1446 reg = <0x00 0x02691000 0x00 0x200>, 1447 <0x00 0x02698000 0x00 0x8000>; 1448 reg-names = "m_can", "message_ram"; 1449 power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>; 1450 clocks = <&k3_clks 199 0>, <&k3_clks 199 1>; 1451 clock-names = "hclk", "cclk"; 1452 interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>; 1454 interrupt-names = "int0", "int1"; 1455 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1456 status = "disabled"; 1457 }; 1458 1459 main_mcan16: can@26a1000 { 1460 compatible = "bosch,m_can"; 1461 reg = <0x00 0x026a1000 0x00 0x200>, 1462 <0x00 0x026a8000 0x00 0x8000>; 1463 reg-names = "m_can", "message_ram"; 1464 power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>; 1465 clocks = <&k3_clks 201 0>, <&k3_clks 201 1>; 1466 clock-names = "hclk", "cclk"; 1467 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 1469 interrupt-names = "int0", "int1"; 1470 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1471 status = "disabled"; 1472 }; 1473 1474 main_mcan17: can@26b1000 { 1475 compatible = "bosch,m_can"; 1476 reg = <0x00 0x026b1000 0x00 0x200>, 1477 <0x00 0x026b8000 0x00 0x8000>; 1478 reg-names = "m_can", "message_ram"; 1479 power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>; 1480 clocks = <&k3_clks 206 0>, <&k3_clks 206 1>; 1481 clock-names = "hclk", "cclk"; 1482 interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>; 1484 interrupt-names = "int0", "int1"; 1485 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1486 status = "disabled"; 1487 }; 1488 1489 main_spi0: spi@2100000 { 1490 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1491 reg = <0x00 0x02100000 0x00 0x400>; 1492 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1493 #address-cells = <1>; 1494 #size-cells = <0>; 1495 power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>; 1496 clocks = <&k3_clks 339 1>; 1497 status = "disabled"; 1498 }; 1499 1500 main_spi1: spi@2110000 { 1501 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1502 reg = <0x00 0x02110000 0x00 0x400>; 1503 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1504 #address-cells = <1>; 1505 #size-cells = <0>; 1506 power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>; 1507 clocks = <&k3_clks 340 1>; 1508 status = "disabled"; 1509 }; 1510 1511 main_spi2: spi@2120000 { 1512 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1513 reg = <0x00 0x02120000 0x00 0x400>; 1514 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1515 #address-cells = <1>; 1516 #size-cells = <0>; 1517 power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>; 1518 clocks = <&k3_clks 341 1>; 1519 status = "disabled"; 1520 }; 1521 1522 main_spi3: spi@2130000 { 1523 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1524 reg = <0x00 0x02130000 0x00 0x400>; 1525 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1526 #address-cells = <1>; 1527 #size-cells = <0>; 1528 power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>; 1529 clocks = <&k3_clks 342 1>; 1530 status = "disabled"; 1531 }; 1532 1533 main_spi4: spi@2140000 { 1534 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1535 reg = <0x00 0x02140000 0x00 0x400>; 1536 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1537 #address-cells = <1>; 1538 #size-cells = <0>; 1539 power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>; 1540 clocks = <&k3_clks 343 1>; 1541 status = "disabled"; 1542 }; 1543 1544 main_spi5: spi@2150000 { 1545 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1546 reg = <0x00 0x02150000 0x00 0x400>; 1547 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1548 #address-cells = <1>; 1549 #size-cells = <0>; 1550 power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>; 1551 clocks = <&k3_clks 344 1>; 1552 status = "disabled"; 1553 }; 1554 1555 main_spi6: spi@2160000 { 1556 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1557 reg = <0x00 0x02160000 0x00 0x400>; 1558 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1559 #address-cells = <1>; 1560 #size-cells = <0>; 1561 power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>; 1562 clocks = <&k3_clks 345 1>; 1563 status = "disabled"; 1564 }; 1565 1566 main_spi7: spi@2170000 { 1567 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1568 reg = <0x00 0x02170000 0x00 0x400>; 1569 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1570 #address-cells = <1>; 1571 #size-cells = <0>; 1572 power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>; 1573 clocks = <&k3_clks 346 1>; 1574 status = "disabled"; 1575 }; 1576}; 1577