1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721E SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7#include <dt-bindings/phy/phy.h> 8#include <dt-bindings/phy/phy-ti.h> 9#include <dt-bindings/mux/mux.h> 10 11#include "k3-serdes.h" 12 13/ { 14 cmn_refclk: clock-cmnrefclk { 15 #clock-cells = <0>; 16 compatible = "fixed-clock"; 17 clock-frequency = <0>; 18 }; 19 20 cmn_refclk1: clock-cmnrefclk1 { 21 #clock-cells = <0>; 22 compatible = "fixed-clock"; 23 clock-frequency = <0>; 24 }; 25}; 26 27&cbass_main { 28 msmc_ram: sram@70000000 { 29 compatible = "mmio-sram"; 30 reg = <0x0 0x70000000 0x0 0x800000>; 31 #address-cells = <1>; 32 #size-cells = <1>; 33 ranges = <0x0 0x0 0x70000000 0x800000>; 34 35 atf-sram@0 { 36 reg = <0x0 0x20000>; 37 }; 38 }; 39 40 scm_conf: scm-conf@100000 { 41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 42 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ 43 #address-cells = <1>; 44 #size-cells = <1>; 45 ranges = <0x0 0x0 0x00100000 0x1c000>; 46 47 serdes_ln_ctrl: mux-controller@4080 { 48 compatible = "mmio-mux"; 49 reg = <0x00004080 0x50>; 50 #mux-control-cells = <1>; 51 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 52 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ 53 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ 54 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ 55 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; 56 /* SERDES4 lane0/1/2/3 select */ 57 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, 58 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 59 <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, 60 <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>, 61 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 62 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 63 }; 64 65 cpsw0_phy_gmii_sel: phy@4044 { 66 compatible = "ti,j721e-cpsw9g-phy-gmii-sel"; 67 ti,qsgmii-main-ports = <2>, <2>; 68 reg = <0x4044 0x20>; 69 #phy-cells = <1>; 70 }; 71 72 usb_serdes_mux: mux-controller@4000 { 73 compatible = "mmio-mux"; 74 #mux-control-cells = <1>; 75 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ 76 <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ 77 }; 78 79 ehrpwm_tbclk: clock-controller@4140 { 80 compatible = "ti,am654-ehrpwm-tbclk"; 81 reg = <0x4140 0x18>; 82 #clock-cells = <1>; 83 }; 84 }; 85 86 main_ehrpwm0: pwm@3000000 { 87 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 88 #pwm-cells = <3>; 89 reg = <0x00 0x3000000 0x00 0x100>; 90 power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; 91 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>; 92 clock-names = "tbclk", "fck"; 93 status = "disabled"; 94 }; 95 96 main_ehrpwm1: pwm@3010000 { 97 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 98 #pwm-cells = <3>; 99 reg = <0x00 0x3010000 0x00 0x100>; 100 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; 101 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>; 102 clock-names = "tbclk", "fck"; 103 status = "disabled"; 104 }; 105 106 main_ehrpwm2: pwm@3020000 { 107 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 108 #pwm-cells = <3>; 109 reg = <0x00 0x3020000 0x00 0x100>; 110 power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; 111 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>; 112 clock-names = "tbclk", "fck"; 113 status = "disabled"; 114 }; 115 116 main_ehrpwm3: pwm@3030000 { 117 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 118 #pwm-cells = <3>; 119 reg = <0x00 0x3030000 0x00 0x100>; 120 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 121 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>; 122 clock-names = "tbclk", "fck"; 123 status = "disabled"; 124 }; 125 126 main_ehrpwm4: pwm@3040000 { 127 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 128 #pwm-cells = <3>; 129 reg = <0x00 0x3040000 0x00 0x100>; 130 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 131 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>; 132 clock-names = "tbclk", "fck"; 133 status = "disabled"; 134 }; 135 136 main_ehrpwm5: pwm@3050000 { 137 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 138 #pwm-cells = <3>; 139 reg = <0x00 0x3050000 0x00 0x100>; 140 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 141 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>; 142 clock-names = "tbclk", "fck"; 143 status = "disabled"; 144 }; 145 146 gic500: interrupt-controller@1800000 { 147 compatible = "arm,gic-v3"; 148 #address-cells = <2>; 149 #size-cells = <2>; 150 ranges; 151 #interrupt-cells = <3>; 152 interrupt-controller; 153 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 154 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 155 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 156 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 157 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 158 159 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 160 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 161 162 gic_its: msi-controller@1820000 { 163 compatible = "arm,gic-v3-its"; 164 reg = <0x00 0x01820000 0x00 0x10000>; 165 socionext,synquacer-pre-its = <0x1000000 0x400000>; 166 msi-controller; 167 #msi-cells = <1>; 168 }; 169 }; 170 171 main_gpio_intr: interrupt-controller@a00000 { 172 compatible = "ti,sci-intr"; 173 reg = <0x00 0x00a00000 0x00 0x800>; 174 ti,intr-trigger-type = <1>; 175 interrupt-controller; 176 interrupt-parent = <&gic500>; 177 #interrupt-cells = <1>; 178 ti,sci = <&dmsc>; 179 ti,sci-dev-id = <131>; 180 ti,interrupt-ranges = <8 392 56>; 181 }; 182 183 main_navss: bus@30000000 { 184 compatible = "simple-mfd"; 185 #address-cells = <2>; 186 #size-cells = <2>; 187 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 188 dma-coherent; 189 dma-ranges; 190 191 ti,sci-dev-id = <199>; 192 193 main_navss_intr: interrupt-controller@310e0000 { 194 compatible = "ti,sci-intr"; 195 reg = <0x0 0x310e0000 0x0 0x4000>; 196 ti,intr-trigger-type = <4>; 197 interrupt-controller; 198 interrupt-parent = <&gic500>; 199 #interrupt-cells = <1>; 200 ti,sci = <&dmsc>; 201 ti,sci-dev-id = <213>; 202 ti,interrupt-ranges = <0 64 64>, 203 <64 448 64>, 204 <128 672 64>; 205 }; 206 207 main_udmass_inta: interrupt-controller@33d00000 { 208 compatible = "ti,sci-inta"; 209 reg = <0x0 0x33d00000 0x0 0x100000>; 210 interrupt-controller; 211 interrupt-parent = <&main_navss_intr>; 212 msi-controller; 213 #interrupt-cells = <0>; 214 ti,sci = <&dmsc>; 215 ti,sci-dev-id = <209>; 216 ti,interrupt-ranges = <0 0 256>; 217 }; 218 219 secure_proxy_main: mailbox@32c00000 { 220 compatible = "ti,am654-secure-proxy"; 221 #mbox-cells = <1>; 222 reg-names = "target_data", "rt", "scfg"; 223 reg = <0x00 0x32c00000 0x00 0x100000>, 224 <0x00 0x32400000 0x00 0x100000>, 225 <0x00 0x32800000 0x00 0x100000>; 226 interrupt-names = "rx_011"; 227 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 228 }; 229 230 smmu0: iommu@36600000 { 231 compatible = "arm,smmu-v3"; 232 reg = <0x0 0x36600000 0x0 0x100000>; 233 interrupt-parent = <&gic500>; 234 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 235 <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>; 236 interrupt-names = "eventq", "gerror"; 237 #iommu-cells = <1>; 238 }; 239 240 hwspinlock: spinlock@30e00000 { 241 compatible = "ti,am654-hwspinlock"; 242 reg = <0x00 0x30e00000 0x00 0x1000>; 243 #hwlock-cells = <1>; 244 }; 245 246 mailbox0_cluster0: mailbox@31f80000 { 247 compatible = "ti,am654-mailbox"; 248 reg = <0x00 0x31f80000 0x00 0x200>; 249 #mbox-cells = <1>; 250 ti,mbox-num-users = <4>; 251 ti,mbox-num-fifos = <16>; 252 interrupt-parent = <&main_navss_intr>; 253 status = "disabled"; 254 }; 255 256 mailbox0_cluster1: mailbox@31f81000 { 257 compatible = "ti,am654-mailbox"; 258 reg = <0x00 0x31f81000 0x00 0x200>; 259 #mbox-cells = <1>; 260 ti,mbox-num-users = <4>; 261 ti,mbox-num-fifos = <16>; 262 interrupt-parent = <&main_navss_intr>; 263 status = "disabled"; 264 }; 265 266 mailbox0_cluster2: mailbox@31f82000 { 267 compatible = "ti,am654-mailbox"; 268 reg = <0x00 0x31f82000 0x00 0x200>; 269 #mbox-cells = <1>; 270 ti,mbox-num-users = <4>; 271 ti,mbox-num-fifos = <16>; 272 interrupt-parent = <&main_navss_intr>; 273 status = "disabled"; 274 }; 275 276 mailbox0_cluster3: mailbox@31f83000 { 277 compatible = "ti,am654-mailbox"; 278 reg = <0x00 0x31f83000 0x00 0x200>; 279 #mbox-cells = <1>; 280 ti,mbox-num-users = <4>; 281 ti,mbox-num-fifos = <16>; 282 interrupt-parent = <&main_navss_intr>; 283 status = "disabled"; 284 }; 285 286 mailbox0_cluster4: mailbox@31f84000 { 287 compatible = "ti,am654-mailbox"; 288 reg = <0x00 0x31f84000 0x00 0x200>; 289 #mbox-cells = <1>; 290 ti,mbox-num-users = <4>; 291 ti,mbox-num-fifos = <16>; 292 interrupt-parent = <&main_navss_intr>; 293 status = "disabled"; 294 }; 295 296 mailbox0_cluster5: mailbox@31f85000 { 297 compatible = "ti,am654-mailbox"; 298 reg = <0x00 0x31f85000 0x00 0x200>; 299 #mbox-cells = <1>; 300 ti,mbox-num-users = <4>; 301 ti,mbox-num-fifos = <16>; 302 interrupt-parent = <&main_navss_intr>; 303 status = "disabled"; 304 }; 305 306 mailbox0_cluster6: mailbox@31f86000 { 307 compatible = "ti,am654-mailbox"; 308 reg = <0x00 0x31f86000 0x00 0x200>; 309 #mbox-cells = <1>; 310 ti,mbox-num-users = <4>; 311 ti,mbox-num-fifos = <16>; 312 interrupt-parent = <&main_navss_intr>; 313 status = "disabled"; 314 }; 315 316 mailbox0_cluster7: mailbox@31f87000 { 317 compatible = "ti,am654-mailbox"; 318 reg = <0x00 0x31f87000 0x00 0x200>; 319 #mbox-cells = <1>; 320 ti,mbox-num-users = <4>; 321 ti,mbox-num-fifos = <16>; 322 interrupt-parent = <&main_navss_intr>; 323 status = "disabled"; 324 }; 325 326 mailbox0_cluster8: mailbox@31f88000 { 327 compatible = "ti,am654-mailbox"; 328 reg = <0x00 0x31f88000 0x00 0x200>; 329 #mbox-cells = <1>; 330 ti,mbox-num-users = <4>; 331 ti,mbox-num-fifos = <16>; 332 interrupt-parent = <&main_navss_intr>; 333 status = "disabled"; 334 }; 335 336 mailbox0_cluster9: mailbox@31f89000 { 337 compatible = "ti,am654-mailbox"; 338 reg = <0x00 0x31f89000 0x00 0x200>; 339 #mbox-cells = <1>; 340 ti,mbox-num-users = <4>; 341 ti,mbox-num-fifos = <16>; 342 interrupt-parent = <&main_navss_intr>; 343 status = "disabled"; 344 }; 345 346 mailbox0_cluster10: mailbox@31f8a000 { 347 compatible = "ti,am654-mailbox"; 348 reg = <0x00 0x31f8a000 0x00 0x200>; 349 #mbox-cells = <1>; 350 ti,mbox-num-users = <4>; 351 ti,mbox-num-fifos = <16>; 352 interrupt-parent = <&main_navss_intr>; 353 status = "disabled"; 354 }; 355 356 mailbox0_cluster11: mailbox@31f8b000 { 357 compatible = "ti,am654-mailbox"; 358 reg = <0x00 0x31f8b000 0x00 0x200>; 359 #mbox-cells = <1>; 360 ti,mbox-num-users = <4>; 361 ti,mbox-num-fifos = <16>; 362 interrupt-parent = <&main_navss_intr>; 363 status = "disabled"; 364 }; 365 366 main_ringacc: ringacc@3c000000 { 367 compatible = "ti,am654-navss-ringacc"; 368 reg = <0x0 0x3c000000 0x0 0x400000>, 369 <0x0 0x38000000 0x0 0x400000>, 370 <0x0 0x31120000 0x0 0x100>, 371 <0x0 0x33000000 0x0 0x40000>; 372 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 373 ti,num-rings = <1024>; 374 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 375 ti,sci = <&dmsc>; 376 ti,sci-dev-id = <211>; 377 msi-parent = <&main_udmass_inta>; 378 }; 379 380 main_udmap: dma-controller@31150000 { 381 compatible = "ti,j721e-navss-main-udmap"; 382 reg = <0x0 0x31150000 0x0 0x100>, 383 <0x0 0x34000000 0x0 0x100000>, 384 <0x0 0x35000000 0x0 0x100000>; 385 reg-names = "gcfg", "rchanrt", "tchanrt"; 386 msi-parent = <&main_udmass_inta>; 387 #dma-cells = <1>; 388 389 ti,sci = <&dmsc>; 390 ti,sci-dev-id = <212>; 391 ti,ringacc = <&main_ringacc>; 392 393 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 394 <0x0f>, /* TX_HCHAN */ 395 <0x10>; /* TX_UHCHAN */ 396 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 397 <0x0b>, /* RX_HCHAN */ 398 <0x0c>; /* RX_UHCHAN */ 399 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 400 }; 401 402 cpts@310d0000 { 403 compatible = "ti,j721e-cpts"; 404 reg = <0x0 0x310d0000 0x0 0x400>; 405 reg-names = "cpts"; 406 clocks = <&k3_clks 201 1>; 407 clock-names = "cpts"; 408 interrupts-extended = <&main_navss_intr 391>; 409 interrupt-names = "cpts"; 410 ti,cpts-periodic-outputs = <6>; 411 ti,cpts-ext-ts-inputs = <8>; 412 }; 413 }; 414 415 cpsw0: ethernet@c000000 { 416 compatible = "ti,j721e-cpswxg-nuss"; 417 #address-cells = <2>; 418 #size-cells = <2>; 419 reg = <0x0 0xc000000 0x0 0x200000>; 420 reg-names = "cpsw_nuss"; 421 ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>; 422 clocks = <&k3_clks 19 89>; 423 clock-names = "fck"; 424 power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; 425 426 dmas = <&main_udmap 0xca00>, 427 <&main_udmap 0xca01>, 428 <&main_udmap 0xca02>, 429 <&main_udmap 0xca03>, 430 <&main_udmap 0xca04>, 431 <&main_udmap 0xca05>, 432 <&main_udmap 0xca06>, 433 <&main_udmap 0xca07>, 434 <&main_udmap 0x4a00>; 435 dma-names = "tx0", "tx1", "tx2", "tx3", 436 "tx4", "tx5", "tx6", "tx7", 437 "rx"; 438 439 status = "disabled"; 440 441 ethernet-ports { 442 #address-cells = <1>; 443 #size-cells = <0>; 444 cpsw0_port1: port@1 { 445 reg = <1>; 446 ti,mac-only; 447 label = "port1"; 448 status = "disabled"; 449 }; 450 451 cpsw0_port2: port@2 { 452 reg = <2>; 453 ti,mac-only; 454 label = "port2"; 455 status = "disabled"; 456 }; 457 458 cpsw0_port3: port@3 { 459 reg = <3>; 460 ti,mac-only; 461 label = "port3"; 462 status = "disabled"; 463 }; 464 465 cpsw0_port4: port@4 { 466 reg = <4>; 467 ti,mac-only; 468 label = "port4"; 469 status = "disabled"; 470 }; 471 472 cpsw0_port5: port@5 { 473 reg = <5>; 474 ti,mac-only; 475 label = "port5"; 476 status = "disabled"; 477 }; 478 479 cpsw0_port6: port@6 { 480 reg = <6>; 481 ti,mac-only; 482 label = "port6"; 483 status = "disabled"; 484 }; 485 486 cpsw0_port7: port@7 { 487 reg = <7>; 488 ti,mac-only; 489 label = "port7"; 490 status = "disabled"; 491 }; 492 493 cpsw0_port8: port@8 { 494 reg = <8>; 495 ti,mac-only; 496 label = "port8"; 497 status = "disabled"; 498 }; 499 }; 500 501 cpsw9g_mdio: mdio@f00 { 502 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 503 reg = <0x0 0xf00 0x0 0x100>; 504 #address-cells = <1>; 505 #size-cells = <0>; 506 clocks = <&k3_clks 19 89>; 507 clock-names = "fck"; 508 bus_freq = <1000000>; 509 status = "disabled"; 510 }; 511 512 cpts@3d000 { 513 compatible = "ti,j721e-cpts"; 514 reg = <0x0 0x3d000 0x0 0x400>; 515 clocks = <&k3_clks 19 16>; 516 clock-names = "cpts"; 517 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 518 interrupt-names = "cpts"; 519 ti,cpts-ext-ts-inputs = <4>; 520 ti,cpts-periodic-outputs = <2>; 521 }; 522 }; 523 524 main_crypto: crypto@4e00000 { 525 compatible = "ti,j721e-sa2ul"; 526 reg = <0x0 0x4e00000 0x0 0x1200>; 527 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; 528 #address-cells = <2>; 529 #size-cells = <2>; 530 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; 531 532 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, 533 <&main_udmap 0x4001>; 534 dma-names = "tx", "rx1", "rx2"; 535 536 rng: rng@4e10000 { 537 compatible = "inside-secure,safexcel-eip76"; 538 reg = <0x0 0x4e10000 0x0 0x7d>; 539 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 540 }; 541 }; 542 543 main_pmx0: pinctrl@11c000 { 544 compatible = "pinctrl-single"; 545 /* Proxy 0 addressing */ 546 reg = <0x0 0x11c000 0x0 0x2b4>; 547 #pinctrl-cells = <1>; 548 pinctrl-single,register-width = <32>; 549 pinctrl-single,function-mask = <0xffffffff>; 550 }; 551 552 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 553 main_timerio_input: pinctrl@104200 { 554 compatible = "pinctrl-single"; 555 reg = <0x00 0x104200 0x00 0x50>; 556 #pinctrl-cells = <1>; 557 pinctrl-single,register-width = <32>; 558 pinctrl-single,function-mask = <0x00000007>; 559 }; 560 561 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 562 main_timerio_output: pinctrl@104280 { 563 compatible = "pinctrl-single"; 564 reg = <0x00 0x104280 0x00 0x20>; 565 #pinctrl-cells = <1>; 566 pinctrl-single,register-width = <32>; 567 pinctrl-single,function-mask = <0x0000001f>; 568 }; 569 570 serdes_wiz0: wiz@5000000 { 571 compatible = "ti,j721e-wiz-16g"; 572 #address-cells = <1>; 573 #size-cells = <1>; 574 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 575 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>; 576 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 577 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; 578 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; 579 num-lanes = <2>; 580 #reset-cells = <1>; 581 ranges = <0x5000000 0x0 0x5000000 0x10000>; 582 583 wiz0_pll0_refclk: pll0-refclk { 584 clocks = <&k3_clks 292 11>, <&cmn_refclk>; 585 #clock-cells = <0>; 586 assigned-clocks = <&wiz0_pll0_refclk>; 587 assigned-clock-parents = <&k3_clks 292 11>; 588 }; 589 590 wiz0_pll1_refclk: pll1-refclk { 591 clocks = <&k3_clks 292 0>, <&cmn_refclk1>; 592 #clock-cells = <0>; 593 assigned-clocks = <&wiz0_pll1_refclk>; 594 assigned-clock-parents = <&k3_clks 292 0>; 595 }; 596 597 wiz0_refclk_dig: refclk-dig { 598 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>; 599 #clock-cells = <0>; 600 assigned-clocks = <&wiz0_refclk_dig>; 601 assigned-clock-parents = <&k3_clks 292 11>; 602 }; 603 604 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 605 clocks = <&wiz0_refclk_dig>; 606 #clock-cells = <0>; 607 }; 608 609 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 610 clocks = <&wiz0_pll1_refclk>; 611 #clock-cells = <0>; 612 }; 613 614 serdes0: serdes@5000000 { 615 compatible = "ti,sierra-phy-t0"; 616 reg-names = "serdes"; 617 reg = <0x5000000 0x10000>; 618 #address-cells = <1>; 619 #size-cells = <0>; 620 #clock-cells = <1>; 621 resets = <&serdes_wiz0 0>; 622 reset-names = "sierra_reset"; 623 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, 624 <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>; 625 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 626 "pll0_refclk", "pll1_refclk"; 627 }; 628 }; 629 630 serdes_wiz1: wiz@5010000 { 631 compatible = "ti,j721e-wiz-16g"; 632 #address-cells = <1>; 633 #size-cells = <1>; 634 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; 635 clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>; 636 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 637 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; 638 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; 639 num-lanes = <2>; 640 #reset-cells = <1>; 641 ranges = <0x5010000 0x0 0x5010000 0x10000>; 642 643 wiz1_pll0_refclk: pll0-refclk { 644 clocks = <&k3_clks 293 13>, <&cmn_refclk>; 645 #clock-cells = <0>; 646 assigned-clocks = <&wiz1_pll0_refclk>; 647 assigned-clock-parents = <&k3_clks 293 13>; 648 }; 649 650 wiz1_pll1_refclk: pll1-refclk { 651 clocks = <&k3_clks 293 0>, <&cmn_refclk1>; 652 #clock-cells = <0>; 653 assigned-clocks = <&wiz1_pll1_refclk>; 654 assigned-clock-parents = <&k3_clks 293 0>; 655 }; 656 657 wiz1_refclk_dig: refclk-dig { 658 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>; 659 #clock-cells = <0>; 660 assigned-clocks = <&wiz1_refclk_dig>; 661 assigned-clock-parents = <&k3_clks 293 13>; 662 }; 663 664 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div { 665 clocks = <&wiz1_refclk_dig>; 666 #clock-cells = <0>; 667 }; 668 669 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 670 clocks = <&wiz1_pll1_refclk>; 671 #clock-cells = <0>; 672 }; 673 674 serdes1: serdes@5010000 { 675 compatible = "ti,sierra-phy-t0"; 676 reg-names = "serdes"; 677 reg = <0x5010000 0x10000>; 678 #address-cells = <1>; 679 #size-cells = <0>; 680 #clock-cells = <1>; 681 resets = <&serdes_wiz1 0>; 682 reset-names = "sierra_reset"; 683 clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>, 684 <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>; 685 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 686 "pll0_refclk", "pll1_refclk"; 687 }; 688 }; 689 690 serdes_wiz2: wiz@5020000 { 691 compatible = "ti,j721e-wiz-16g"; 692 #address-cells = <1>; 693 #size-cells = <1>; 694 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; 695 clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>; 696 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 697 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; 698 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; 699 num-lanes = <2>; 700 #reset-cells = <1>; 701 ranges = <0x5020000 0x0 0x5020000 0x10000>; 702 703 wiz2_pll0_refclk: pll0-refclk { 704 clocks = <&k3_clks 294 11>, <&cmn_refclk>; 705 #clock-cells = <0>; 706 assigned-clocks = <&wiz2_pll0_refclk>; 707 assigned-clock-parents = <&k3_clks 294 11>; 708 }; 709 710 wiz2_pll1_refclk: pll1-refclk { 711 clocks = <&k3_clks 294 0>, <&cmn_refclk1>; 712 #clock-cells = <0>; 713 assigned-clocks = <&wiz2_pll1_refclk>; 714 assigned-clock-parents = <&k3_clks 294 0>; 715 }; 716 717 wiz2_refclk_dig: refclk-dig { 718 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>; 719 #clock-cells = <0>; 720 assigned-clocks = <&wiz2_refclk_dig>; 721 assigned-clock-parents = <&k3_clks 294 11>; 722 }; 723 724 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div { 725 clocks = <&wiz2_refclk_dig>; 726 #clock-cells = <0>; 727 }; 728 729 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 730 clocks = <&wiz2_pll1_refclk>; 731 #clock-cells = <0>; 732 }; 733 734 serdes2: serdes@5020000 { 735 compatible = "ti,sierra-phy-t0"; 736 reg-names = "serdes"; 737 reg = <0x5020000 0x10000>; 738 #address-cells = <1>; 739 #size-cells = <0>; 740 #clock-cells = <1>; 741 resets = <&serdes_wiz2 0>; 742 reset-names = "sierra_reset"; 743 clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>, 744 <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>; 745 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 746 "pll0_refclk", "pll1_refclk"; 747 }; 748 }; 749 750 serdes_wiz3: wiz@5030000 { 751 compatible = "ti,j721e-wiz-16g"; 752 #address-cells = <1>; 753 #size-cells = <1>; 754 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; 755 clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>; 756 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 757 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; 758 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; 759 num-lanes = <2>; 760 #reset-cells = <1>; 761 ranges = <0x5030000 0x0 0x5030000 0x10000>; 762 763 wiz3_pll0_refclk: pll0-refclk { 764 clocks = <&k3_clks 295 9>, <&cmn_refclk>; 765 #clock-cells = <0>; 766 assigned-clocks = <&wiz3_pll0_refclk>; 767 assigned-clock-parents = <&k3_clks 295 9>; 768 }; 769 770 wiz3_pll1_refclk: pll1-refclk { 771 clocks = <&k3_clks 295 0>, <&cmn_refclk1>; 772 #clock-cells = <0>; 773 assigned-clocks = <&wiz3_pll1_refclk>; 774 assigned-clock-parents = <&k3_clks 295 0>; 775 }; 776 777 wiz3_refclk_dig: refclk-dig { 778 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>; 779 #clock-cells = <0>; 780 assigned-clocks = <&wiz3_refclk_dig>; 781 assigned-clock-parents = <&k3_clks 295 9>; 782 }; 783 784 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div { 785 clocks = <&wiz3_refclk_dig>; 786 #clock-cells = <0>; 787 }; 788 789 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 790 clocks = <&wiz3_pll1_refclk>; 791 #clock-cells = <0>; 792 }; 793 794 serdes3: serdes@5030000 { 795 compatible = "ti,sierra-phy-t0"; 796 reg-names = "serdes"; 797 reg = <0x5030000 0x10000>; 798 #address-cells = <1>; 799 #size-cells = <0>; 800 #clock-cells = <1>; 801 resets = <&serdes_wiz3 0>; 802 reset-names = "sierra_reset"; 803 clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>, 804 <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>; 805 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 806 "pll0_refclk", "pll1_refclk"; 807 }; 808 }; 809 810 pcie0_rc: pcie@2900000 { 811 compatible = "ti,j721e-pcie-host"; 812 reg = <0x00 0x02900000 0x00 0x1000>, 813 <0x00 0x02907000 0x00 0x400>, 814 <0x00 0x0d000000 0x00 0x00800000>, 815 <0x00 0x10000000 0x00 0x00001000>; 816 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 817 interrupt-names = "link_state"; 818 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 819 device_type = "pci"; 820 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; 821 max-link-speed = <3>; 822 num-lanes = <2>; 823 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; 824 clocks = <&k3_clks 239 1>; 825 clock-names = "fck"; 826 #address-cells = <3>; 827 #size-cells = <2>; 828 bus-range = <0x0 0xff>; 829 vendor-id = <0x104c>; 830 device-id = <0xb00d>; 831 msi-map = <0x0 &gic_its 0x0 0x10000>; 832 dma-coherent; 833 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, 834 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; 835 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 836 status = "disabled"; 837 }; 838 839 pcie1_rc: pcie@2910000 { 840 compatible = "ti,j721e-pcie-host"; 841 reg = <0x00 0x02910000 0x00 0x1000>, 842 <0x00 0x02917000 0x00 0x400>, 843 <0x00 0x0d800000 0x00 0x00800000>, 844 <0x00 0x18000000 0x00 0x00001000>; 845 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 846 interrupt-names = "link_state"; 847 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 848 device_type = "pci"; 849 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 850 max-link-speed = <3>; 851 num-lanes = <2>; 852 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 853 clocks = <&k3_clks 240 1>; 854 clock-names = "fck"; 855 #address-cells = <3>; 856 #size-cells = <2>; 857 bus-range = <0x0 0xff>; 858 vendor-id = <0x104c>; 859 device-id = <0xb00d>; 860 msi-map = <0x0 &gic_its 0x10000 0x10000>; 861 dma-coherent; 862 ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, 863 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; 864 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 865 status = "disabled"; 866 }; 867 868 pcie2_rc: pcie@2920000 { 869 compatible = "ti,j721e-pcie-host"; 870 reg = <0x00 0x02920000 0x00 0x1000>, 871 <0x00 0x02927000 0x00 0x400>, 872 <0x00 0x0e000000 0x00 0x00800000>, 873 <0x44 0x00000000 0x00 0x00001000>; 874 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 875 interrupt-names = "link_state"; 876 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; 877 device_type = "pci"; 878 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; 879 max-link-speed = <3>; 880 num-lanes = <2>; 881 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 882 clocks = <&k3_clks 241 1>; 883 clock-names = "fck"; 884 #address-cells = <3>; 885 #size-cells = <2>; 886 bus-range = <0x0 0xff>; 887 vendor-id = <0x104c>; 888 device-id = <0xb00d>; 889 msi-map = <0x0 &gic_its 0x20000 0x10000>; 890 dma-coherent; 891 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, 892 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; 893 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 894 status = "disabled"; 895 }; 896 897 pcie3_rc: pcie@2930000 { 898 compatible = "ti,j721e-pcie-host"; 899 reg = <0x00 0x02930000 0x00 0x1000>, 900 <0x00 0x02937000 0x00 0x400>, 901 <0x00 0x0e800000 0x00 0x00800000>, 902 <0x44 0x10000000 0x00 0x00001000>; 903 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 904 interrupt-names = "link_state"; 905 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; 906 device_type = "pci"; 907 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; 908 max-link-speed = <3>; 909 num-lanes = <2>; 910 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 911 clocks = <&k3_clks 242 1>; 912 clock-names = "fck"; 913 #address-cells = <3>; 914 #size-cells = <2>; 915 bus-range = <0x0 0xff>; 916 vendor-id = <0x104c>; 917 device-id = <0xb00d>; 918 msi-map = <0x0 &gic_its 0x30000 0x10000>; 919 dma-coherent; 920 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, 921 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; 922 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 923 status = "disabled"; 924 }; 925 926 serdes_wiz4: wiz@5050000 { 927 compatible = "ti,am64-wiz-10g"; 928 #address-cells = <1>; 929 #size-cells = <1>; 930 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; 931 clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>; 932 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 933 assigned-clocks = <&k3_clks 297 9>; 934 assigned-clock-parents = <&k3_clks 297 10>; 935 assigned-clock-rates = <19200000>; 936 num-lanes = <4>; 937 #reset-cells = <1>; 938 #clock-cells = <1>; 939 ranges = <0x05050000 0x00 0x05050000 0x010000>, 940 <0x0a030a00 0x00 0x0a030a00 0x40>; 941 942 serdes4: serdes@5050000 { 943 /* 944 * Note: we also map DPTX PHY registers as the Torrent 945 * needs to manage those. 946 */ 947 compatible = "ti,j721e-serdes-10g"; 948 reg = <0x05050000 0x010000>, 949 <0x0a030a00 0x40>; /* DPTX PHY */ 950 reg-names = "torrent_phy", "dptx_phy"; 951 952 resets = <&serdes_wiz4 0>; 953 reset-names = "torrent_reset"; 954 clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>; 955 clock-names = "refclk"; 956 assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, 957 <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, 958 <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; 959 assigned-clock-parents = <&k3_clks 297 9>, 960 <&k3_clks 297 9>, 961 <&k3_clks 297 9>; 962 #address-cells = <1>; 963 #size-cells = <0>; 964 }; 965 }; 966 967 main_timer0: timer@2400000 { 968 compatible = "ti,am654-timer"; 969 reg = <0x00 0x2400000 0x00 0x400>; 970 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 971 clocks = <&k3_clks 49 1>; 972 clock-names = "fck"; 973 assigned-clocks = <&k3_clks 49 1>; 974 assigned-clock-parents = <&k3_clks 49 2>; 975 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; 976 ti,timer-pwm; 977 }; 978 979 main_timer1: timer@2410000 { 980 compatible = "ti,am654-timer"; 981 reg = <0x00 0x2410000 0x00 0x400>; 982 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 983 clocks = <&k3_clks 50 1>; 984 clock-names = "fck"; 985 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>; 986 assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 327 1>; 987 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; 988 ti,timer-pwm; 989 }; 990 991 main_timer2: timer@2420000 { 992 compatible = "ti,am654-timer"; 993 reg = <0x00 0x2420000 0x00 0x400>; 994 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 995 clocks = <&k3_clks 51 1>; 996 clock-names = "fck"; 997 assigned-clocks = <&k3_clks 51 1>; 998 assigned-clock-parents = <&k3_clks 51 2>; 999 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 1000 ti,timer-pwm; 1001 }; 1002 1003 main_timer3: timer@2430000 { 1004 compatible = "ti,am654-timer"; 1005 reg = <0x00 0x2430000 0x00 0x400>; 1006 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 1007 clocks = <&k3_clks 52 1>; 1008 clock-names = "fck"; 1009 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>; 1010 assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 328 1>; 1011 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 1012 ti,timer-pwm; 1013 }; 1014 1015 main_timer4: timer@2440000 { 1016 compatible = "ti,am654-timer"; 1017 reg = <0x00 0x2440000 0x00 0x400>; 1018 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 1019 clocks = <&k3_clks 53 1>; 1020 clock-names = "fck"; 1021 assigned-clocks = <&k3_clks 53 1>; 1022 assigned-clock-parents = <&k3_clks 53 2>; 1023 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 1024 ti,timer-pwm; 1025 }; 1026 1027 main_timer5: timer@2450000 { 1028 compatible = "ti,am654-timer"; 1029 reg = <0x00 0x2450000 0x00 0x400>; 1030 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 1031 clocks = <&k3_clks 54 1>; 1032 clock-names = "fck"; 1033 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>; 1034 assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 329 1>; 1035 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; 1036 ti,timer-pwm; 1037 }; 1038 1039 main_timer6: timer@2460000 { 1040 compatible = "ti,am654-timer"; 1041 reg = <0x00 0x2460000 0x00 0x400>; 1042 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 1043 clocks = <&k3_clks 55 1>; 1044 clock-names = "fck"; 1045 assigned-clocks = <&k3_clks 55 1>; 1046 assigned-clock-parents = <&k3_clks 55 2>; 1047 power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>; 1048 ti,timer-pwm; 1049 }; 1050 1051 main_timer7: timer@2470000 { 1052 compatible = "ti,am654-timer"; 1053 reg = <0x00 0x2470000 0x00 0x400>; 1054 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 1055 clocks = <&k3_clks 57 1>; 1056 clock-names = "fck"; 1057 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>; 1058 assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 330 1>; 1059 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 1060 ti,timer-pwm; 1061 }; 1062 1063 main_timer8: timer@2480000 { 1064 compatible = "ti,am654-timer"; 1065 reg = <0x00 0x2480000 0x00 0x400>; 1066 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 1067 clocks = <&k3_clks 58 1>; 1068 clock-names = "fck"; 1069 assigned-clocks = <&k3_clks 58 1>; 1070 assigned-clock-parents = <&k3_clks 58 2>; 1071 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 1072 ti,timer-pwm; 1073 }; 1074 1075 main_timer9: timer@2490000 { 1076 compatible = "ti,am654-timer"; 1077 reg = <0x00 0x2490000 0x00 0x400>; 1078 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 1079 clocks = <&k3_clks 59 1>; 1080 clock-names = "fck"; 1081 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>; 1082 assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 331 1>; 1083 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; 1084 ti,timer-pwm; 1085 }; 1086 1087 main_timer10: timer@24a0000 { 1088 compatible = "ti,am654-timer"; 1089 reg = <0x00 0x24a0000 0x00 0x400>; 1090 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 1091 clocks = <&k3_clks 60 1>; 1092 clock-names = "fck"; 1093 assigned-clocks = <&k3_clks 60 1>; 1094 assigned-clock-parents = <&k3_clks 60 2>; 1095 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; 1096 ti,timer-pwm; 1097 }; 1098 1099 main_timer11: timer@24b0000 { 1100 compatible = "ti,am654-timer"; 1101 reg = <0x00 0x24b0000 0x00 0x400>; 1102 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 1103 clocks = <&k3_clks 62 1>; 1104 clock-names = "fck"; 1105 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>; 1106 assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 332 1>; 1107 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 1108 ti,timer-pwm; 1109 }; 1110 1111 main_timer12: timer@24c0000 { 1112 compatible = "ti,am654-timer"; 1113 reg = <0x00 0x24c0000 0x00 0x400>; 1114 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 1115 clocks = <&k3_clks 63 1>; 1116 clock-names = "fck"; 1117 assigned-clocks = <&k3_clks 63 1>; 1118 assigned-clock-parents = <&k3_clks 63 2>; 1119 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; 1120 ti,timer-pwm; 1121 }; 1122 1123 main_timer13: timer@24d0000 { 1124 compatible = "ti,am654-timer"; 1125 reg = <0x00 0x24d0000 0x00 0x400>; 1126 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 1127 clocks = <&k3_clks 64 1>; 1128 clock-names = "fck"; 1129 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>; 1130 assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 333 1>; 1131 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; 1132 ti,timer-pwm; 1133 }; 1134 1135 main_timer14: timer@24e0000 { 1136 compatible = "ti,am654-timer"; 1137 reg = <0x00 0x24e0000 0x00 0x400>; 1138 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1139 clocks = <&k3_clks 65 1>; 1140 clock-names = "fck"; 1141 assigned-clocks = <&k3_clks 65 1>; 1142 assigned-clock-parents = <&k3_clks 65 2>; 1143 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; 1144 ti,timer-pwm; 1145 }; 1146 1147 main_timer15: timer@24f0000 { 1148 compatible = "ti,am654-timer"; 1149 reg = <0x00 0x24f0000 0x00 0x400>; 1150 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1151 clocks = <&k3_clks 66 1>; 1152 clock-names = "fck"; 1153 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>; 1154 assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 334 1>; 1155 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; 1156 ti,timer-pwm; 1157 }; 1158 1159 main_timer16: timer@2500000 { 1160 compatible = "ti,am654-timer"; 1161 reg = <0x00 0x2500000 0x00 0x400>; 1162 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1163 clocks = <&k3_clks 67 1>; 1164 clock-names = "fck"; 1165 assigned-clocks = <&k3_clks 67 1>; 1166 assigned-clock-parents = <&k3_clks 67 2>; 1167 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; 1168 ti,timer-pwm; 1169 }; 1170 1171 main_timer17: timer@2510000 { 1172 compatible = "ti,am654-timer"; 1173 reg = <0x00 0x2510000 0x00 0x400>; 1174 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1175 clocks = <&k3_clks 68 1>; 1176 clock-names = "fck"; 1177 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>; 1178 assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 335 1>; 1179 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; 1180 ti,timer-pwm; 1181 }; 1182 1183 main_timer18: timer@2520000 { 1184 compatible = "ti,am654-timer"; 1185 reg = <0x00 0x2520000 0x00 0x400>; 1186 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1187 clocks = <&k3_clks 69 1>; 1188 clock-names = "fck"; 1189 assigned-clocks = <&k3_clks 69 1>; 1190 assigned-clock-parents = <&k3_clks 69 2>; 1191 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; 1192 ti,timer-pwm; 1193 }; 1194 1195 main_timer19: timer@2530000 { 1196 compatible = "ti,am654-timer"; 1197 reg = <0x00 0x2530000 0x00 0x400>; 1198 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1199 clocks = <&k3_clks 70 1>; 1200 clock-names = "fck"; 1201 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>; 1202 assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 336 1>; 1203 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; 1204 ti,timer-pwm; 1205 }; 1206 1207 main_uart0: serial@2800000 { 1208 compatible = "ti,j721e-uart", "ti,am654-uart"; 1209 reg = <0x00 0x02800000 0x00 0x100>; 1210 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 1211 clock-frequency = <48000000>; 1212 current-speed = <115200>; 1213 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 1214 clocks = <&k3_clks 146 0>; 1215 clock-names = "fclk"; 1216 status = "disabled"; 1217 }; 1218 1219 main_uart1: serial@2810000 { 1220 compatible = "ti,j721e-uart", "ti,am654-uart"; 1221 reg = <0x00 0x02810000 0x00 0x100>; 1222 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 1223 clock-frequency = <48000000>; 1224 current-speed = <115200>; 1225 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 1226 clocks = <&k3_clks 278 0>; 1227 clock-names = "fclk"; 1228 status = "disabled"; 1229 }; 1230 1231 main_uart2: serial@2820000 { 1232 compatible = "ti,j721e-uart", "ti,am654-uart"; 1233 reg = <0x00 0x02820000 0x00 0x100>; 1234 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 1235 clock-frequency = <48000000>; 1236 current-speed = <115200>; 1237 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 1238 clocks = <&k3_clks 279 0>; 1239 clock-names = "fclk"; 1240 status = "disabled"; 1241 }; 1242 1243 main_uart3: serial@2830000 { 1244 compatible = "ti,j721e-uart", "ti,am654-uart"; 1245 reg = <0x00 0x02830000 0x00 0x100>; 1246 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 1247 clock-frequency = <48000000>; 1248 current-speed = <115200>; 1249 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 1250 clocks = <&k3_clks 280 0>; 1251 clock-names = "fclk"; 1252 status = "disabled"; 1253 }; 1254 1255 main_uart4: serial@2840000 { 1256 compatible = "ti,j721e-uart", "ti,am654-uart"; 1257 reg = <0x00 0x02840000 0x00 0x100>; 1258 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 1259 clock-frequency = <48000000>; 1260 current-speed = <115200>; 1261 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 1262 clocks = <&k3_clks 281 0>; 1263 clock-names = "fclk"; 1264 status = "disabled"; 1265 }; 1266 1267 main_uart5: serial@2850000 { 1268 compatible = "ti,j721e-uart", "ti,am654-uart"; 1269 reg = <0x00 0x02850000 0x00 0x100>; 1270 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1271 clock-frequency = <48000000>; 1272 current-speed = <115200>; 1273 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 1274 clocks = <&k3_clks 282 0>; 1275 clock-names = "fclk"; 1276 status = "disabled"; 1277 }; 1278 1279 main_uart6: serial@2860000 { 1280 compatible = "ti,j721e-uart", "ti,am654-uart"; 1281 reg = <0x00 0x02860000 0x00 0x100>; 1282 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 1283 clock-frequency = <48000000>; 1284 current-speed = <115200>; 1285 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 1286 clocks = <&k3_clks 283 0>; 1287 clock-names = "fclk"; 1288 status = "disabled"; 1289 }; 1290 1291 main_uart7: serial@2870000 { 1292 compatible = "ti,j721e-uart", "ti,am654-uart"; 1293 reg = <0x00 0x02870000 0x00 0x100>; 1294 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 1295 clock-frequency = <48000000>; 1296 current-speed = <115200>; 1297 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 1298 clocks = <&k3_clks 284 0>; 1299 clock-names = "fclk"; 1300 status = "disabled"; 1301 }; 1302 1303 main_uart8: serial@2880000 { 1304 compatible = "ti,j721e-uart", "ti,am654-uart"; 1305 reg = <0x00 0x02880000 0x00 0x100>; 1306 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 1307 clock-frequency = <48000000>; 1308 current-speed = <115200>; 1309 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 1310 clocks = <&k3_clks 285 0>; 1311 clock-names = "fclk"; 1312 status = "disabled"; 1313 }; 1314 1315 main_uart9: serial@2890000 { 1316 compatible = "ti,j721e-uart", "ti,am654-uart"; 1317 reg = <0x00 0x02890000 0x00 0x100>; 1318 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 1319 clock-frequency = <48000000>; 1320 current-speed = <115200>; 1321 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 1322 clocks = <&k3_clks 286 0>; 1323 clock-names = "fclk"; 1324 status = "disabled"; 1325 }; 1326 1327 main_gpio0: gpio@600000 { 1328 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1329 reg = <0x0 0x00600000 0x0 0x100>; 1330 gpio-controller; 1331 #gpio-cells = <2>; 1332 interrupt-parent = <&main_gpio_intr>; 1333 interrupts = <256>, <257>, <258>, <259>, 1334 <260>, <261>, <262>, <263>; 1335 interrupt-controller; 1336 #interrupt-cells = <2>; 1337 ti,ngpio = <128>; 1338 ti,davinci-gpio-unbanked = <0>; 1339 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 1340 clocks = <&k3_clks 105 0>; 1341 clock-names = "gpio"; 1342 }; 1343 1344 main_gpio1: gpio@601000 { 1345 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1346 reg = <0x0 0x00601000 0x0 0x100>; 1347 gpio-controller; 1348 #gpio-cells = <2>; 1349 interrupt-parent = <&main_gpio_intr>; 1350 interrupts = <288>, <289>, <290>; 1351 interrupt-controller; 1352 #interrupt-cells = <2>; 1353 ti,ngpio = <36>; 1354 ti,davinci-gpio-unbanked = <0>; 1355 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 1356 clocks = <&k3_clks 106 0>; 1357 clock-names = "gpio"; 1358 }; 1359 1360 main_gpio2: gpio@610000 { 1361 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1362 reg = <0x0 0x00610000 0x0 0x100>; 1363 gpio-controller; 1364 #gpio-cells = <2>; 1365 interrupt-parent = <&main_gpio_intr>; 1366 interrupts = <264>, <265>, <266>, <267>, 1367 <268>, <269>, <270>, <271>; 1368 interrupt-controller; 1369 #interrupt-cells = <2>; 1370 ti,ngpio = <128>; 1371 ti,davinci-gpio-unbanked = <0>; 1372 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 1373 clocks = <&k3_clks 107 0>; 1374 clock-names = "gpio"; 1375 }; 1376 1377 main_gpio3: gpio@611000 { 1378 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1379 reg = <0x0 0x00611000 0x0 0x100>; 1380 gpio-controller; 1381 #gpio-cells = <2>; 1382 interrupt-parent = <&main_gpio_intr>; 1383 interrupts = <292>, <293>, <294>; 1384 interrupt-controller; 1385 #interrupt-cells = <2>; 1386 ti,ngpio = <36>; 1387 ti,davinci-gpio-unbanked = <0>; 1388 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 1389 clocks = <&k3_clks 108 0>; 1390 clock-names = "gpio"; 1391 }; 1392 1393 main_gpio4: gpio@620000 { 1394 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1395 reg = <0x0 0x00620000 0x0 0x100>; 1396 gpio-controller; 1397 #gpio-cells = <2>; 1398 interrupt-parent = <&main_gpio_intr>; 1399 interrupts = <272>, <273>, <274>, <275>, 1400 <276>, <277>, <278>, <279>; 1401 interrupt-controller; 1402 #interrupt-cells = <2>; 1403 ti,ngpio = <128>; 1404 ti,davinci-gpio-unbanked = <0>; 1405 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 1406 clocks = <&k3_clks 109 0>; 1407 clock-names = "gpio"; 1408 }; 1409 1410 main_gpio5: gpio@621000 { 1411 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1412 reg = <0x0 0x00621000 0x0 0x100>; 1413 gpio-controller; 1414 #gpio-cells = <2>; 1415 interrupt-parent = <&main_gpio_intr>; 1416 interrupts = <296>, <297>, <298>; 1417 interrupt-controller; 1418 #interrupt-cells = <2>; 1419 ti,ngpio = <36>; 1420 ti,davinci-gpio-unbanked = <0>; 1421 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 1422 clocks = <&k3_clks 110 0>; 1423 clock-names = "gpio"; 1424 }; 1425 1426 main_gpio6: gpio@630000 { 1427 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1428 reg = <0x0 0x00630000 0x0 0x100>; 1429 gpio-controller; 1430 #gpio-cells = <2>; 1431 interrupt-parent = <&main_gpio_intr>; 1432 interrupts = <280>, <281>, <282>, <283>, 1433 <284>, <285>, <286>, <287>; 1434 interrupt-controller; 1435 #interrupt-cells = <2>; 1436 ti,ngpio = <128>; 1437 ti,davinci-gpio-unbanked = <0>; 1438 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 1439 clocks = <&k3_clks 111 0>; 1440 clock-names = "gpio"; 1441 }; 1442 1443 main_gpio7: gpio@631000 { 1444 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1445 reg = <0x0 0x00631000 0x0 0x100>; 1446 gpio-controller; 1447 #gpio-cells = <2>; 1448 interrupt-parent = <&main_gpio_intr>; 1449 interrupts = <300>, <301>, <302>; 1450 interrupt-controller; 1451 #interrupt-cells = <2>; 1452 ti,ngpio = <36>; 1453 ti,davinci-gpio-unbanked = <0>; 1454 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 1455 clocks = <&k3_clks 112 0>; 1456 clock-names = "gpio"; 1457 }; 1458 1459 main_sdhci0: mmc@4f80000 { 1460 compatible = "ti,j721e-sdhci-8bit"; 1461 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; 1462 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1463 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 1464 clock-names = "clk_ahb", "clk_xin"; 1465 clocks = <&k3_clks 91 0>, <&k3_clks 91 1>; 1466 assigned-clocks = <&k3_clks 91 1>; 1467 assigned-clock-parents = <&k3_clks 91 2>; 1468 bus-width = <8>; 1469 mmc-hs200-1_8v; 1470 mmc-ddr-1_8v; 1471 ti,otap-del-sel-legacy = <0x0>; 1472 ti,otap-del-sel-mmc-hs = <0x0>; 1473 ti,otap-del-sel-ddr52 = <0x5>; 1474 ti,otap-del-sel-hs200 = <0x6>; 1475 ti,otap-del-sel-hs400 = <0x0>; 1476 ti,itap-del-sel-legacy = <0x10>; 1477 ti,itap-del-sel-mmc-hs = <0xa>; 1478 ti,itap-del-sel-ddr52 = <0x3>; 1479 ti,trm-icp = <0x8>; 1480 dma-coherent; 1481 }; 1482 1483 main_sdhci1: mmc@4fb0000 { 1484 compatible = "ti,j721e-sdhci-4bit"; 1485 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; 1486 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1487 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 1488 clock-names = "clk_ahb", "clk_xin"; 1489 clocks = <&k3_clks 92 5>, <&k3_clks 92 0>; 1490 assigned-clocks = <&k3_clks 92 0>; 1491 assigned-clock-parents = <&k3_clks 92 1>; 1492 ti,otap-del-sel-legacy = <0x0>; 1493 ti,otap-del-sel-sd-hs = <0x0>; 1494 ti,otap-del-sel-sdr12 = <0xf>; 1495 ti,otap-del-sel-sdr25 = <0xf>; 1496 ti,otap-del-sel-sdr50 = <0xc>; 1497 ti,otap-del-sel-ddr50 = <0xc>; 1498 ti,otap-del-sel-sdr104 = <0x5>; 1499 ti,itap-del-sel-legacy = <0x0>; 1500 ti,itap-del-sel-sd-hs = <0x0>; 1501 ti,itap-del-sel-sdr12 = <0x0>; 1502 ti,itap-del-sel-sdr25 = <0x0>; 1503 ti,itap-del-sel-ddr50 = <0x2>; 1504 ti,trm-icp = <0x8>; 1505 ti,clkbuf-sel = <0x7>; 1506 dma-coherent; 1507 sdhci-caps-mask = <0x2 0x0>; 1508 }; 1509 1510 main_sdhci2: mmc@4f98000 { 1511 compatible = "ti,j721e-sdhci-4bit"; 1512 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; 1513 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1514 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 1515 clock-names = "clk_ahb", "clk_xin"; 1516 clocks = <&k3_clks 93 5>, <&k3_clks 93 0>; 1517 assigned-clocks = <&k3_clks 93 0>; 1518 assigned-clock-parents = <&k3_clks 93 1>; 1519 ti,otap-del-sel-legacy = <0x0>; 1520 ti,otap-del-sel-sd-hs = <0x0>; 1521 ti,otap-del-sel-sdr12 = <0xf>; 1522 ti,otap-del-sel-sdr25 = <0xf>; 1523 ti,otap-del-sel-sdr50 = <0xc>; 1524 ti,otap-del-sel-ddr50 = <0xc>; 1525 ti,otap-del-sel-sdr104 = <0x5>; 1526 ti,itap-del-sel-legacy = <0x0>; 1527 ti,itap-del-sel-sd-hs = <0x0>; 1528 ti,itap-del-sel-sdr12 = <0x0>; 1529 ti,itap-del-sel-sdr25 = <0x0>; 1530 ti,itap-del-sel-ddr50 = <0x2>; 1531 ti,trm-icp = <0x8>; 1532 ti,clkbuf-sel = <0x7>; 1533 dma-coherent; 1534 sdhci-caps-mask = <0x2 0x0>; 1535 }; 1536 1537 usbss0: cdns-usb@4104000 { 1538 compatible = "ti,j721e-usb"; 1539 reg = <0x00 0x4104000 0x00 0x100>; 1540 dma-coherent; 1541 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 1542 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; 1543 clock-names = "ref", "lpm"; 1544 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ 1545 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ 1546 #address-cells = <2>; 1547 #size-cells = <2>; 1548 ranges; 1549 1550 usb0: usb@6000000 { 1551 compatible = "cdns,usb3"; 1552 reg = <0x00 0x6000000 0x00 0x10000>, 1553 <0x00 0x6010000 0x00 0x10000>, 1554 <0x00 0x6020000 0x00 0x10000>; 1555 reg-names = "otg", "xhci", "dev"; 1556 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1557 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1558 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1559 interrupt-names = "host", 1560 "peripheral", 1561 "otg"; 1562 maximum-speed = "super-speed"; 1563 dr_mode = "otg"; 1564 }; 1565 }; 1566 1567 usbss1: cdns-usb@4114000 { 1568 compatible = "ti,j721e-usb"; 1569 reg = <0x00 0x4114000 0x00 0x100>; 1570 dma-coherent; 1571 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; 1572 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; 1573 clock-names = "ref", "lpm"; 1574 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ 1575 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ 1576 #address-cells = <2>; 1577 #size-cells = <2>; 1578 ranges; 1579 1580 usb1: usb@6400000 { 1581 compatible = "cdns,usb3"; 1582 reg = <0x00 0x6400000 0x00 0x10000>, 1583 <0x00 0x6410000 0x00 0x10000>, 1584 <0x00 0x6420000 0x00 0x10000>; 1585 reg-names = "otg", "xhci", "dev"; 1586 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1587 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1588 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1589 interrupt-names = "host", 1590 "peripheral", 1591 "otg"; 1592 maximum-speed = "super-speed"; 1593 dr_mode = "otg"; 1594 }; 1595 }; 1596 1597 main_i2c0: i2c@2000000 { 1598 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1599 reg = <0x0 0x2000000 0x0 0x100>; 1600 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 1601 #address-cells = <1>; 1602 #size-cells = <0>; 1603 clock-names = "fck"; 1604 clocks = <&k3_clks 187 0>; 1605 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 1606 status = "disabled"; 1607 }; 1608 1609 main_i2c1: i2c@2010000 { 1610 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1611 reg = <0x0 0x2010000 0x0 0x100>; 1612 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 1613 #address-cells = <1>; 1614 #size-cells = <0>; 1615 clock-names = "fck"; 1616 clocks = <&k3_clks 188 0>; 1617 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 1618 status = "disabled"; 1619 }; 1620 1621 main_i2c2: i2c@2020000 { 1622 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1623 reg = <0x0 0x2020000 0x0 0x100>; 1624 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1625 #address-cells = <1>; 1626 #size-cells = <0>; 1627 clock-names = "fck"; 1628 clocks = <&k3_clks 189 0>; 1629 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 1630 status = "disabled"; 1631 }; 1632 1633 main_i2c3: i2c@2030000 { 1634 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1635 reg = <0x0 0x2030000 0x0 0x100>; 1636 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 1637 #address-cells = <1>; 1638 #size-cells = <0>; 1639 clock-names = "fck"; 1640 clocks = <&k3_clks 190 0>; 1641 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 1642 status = "disabled"; 1643 }; 1644 1645 main_i2c4: i2c@2040000 { 1646 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1647 reg = <0x0 0x2040000 0x0 0x100>; 1648 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 1649 #address-cells = <1>; 1650 #size-cells = <0>; 1651 clock-names = "fck"; 1652 clocks = <&k3_clks 191 0>; 1653 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1654 status = "disabled"; 1655 }; 1656 1657 main_i2c5: i2c@2050000 { 1658 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1659 reg = <0x0 0x2050000 0x0 0x100>; 1660 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 1661 #address-cells = <1>; 1662 #size-cells = <0>; 1663 clock-names = "fck"; 1664 clocks = <&k3_clks 192 0>; 1665 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1666 status = "disabled"; 1667 }; 1668 1669 main_i2c6: i2c@2060000 { 1670 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1671 reg = <0x0 0x2060000 0x0 0x100>; 1672 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1673 #address-cells = <1>; 1674 #size-cells = <0>; 1675 clock-names = "fck"; 1676 clocks = <&k3_clks 193 0>; 1677 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 1678 status = "disabled"; 1679 }; 1680 1681 ufs_wrapper: ufs-wrapper@4e80000 { 1682 compatible = "ti,j721e-ufs"; 1683 reg = <0x0 0x4e80000 0x0 0x100>; 1684 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; 1685 clocks = <&k3_clks 277 1>; 1686 assigned-clocks = <&k3_clks 277 1>; 1687 assigned-clock-parents = <&k3_clks 277 4>; 1688 ranges; 1689 #address-cells = <2>; 1690 #size-cells = <2>; 1691 1692 ufs@4e84000 { 1693 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 1694 reg = <0x0 0x4e84000 0x0 0x10000>; 1695 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1696 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>; 1697 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>; 1698 clock-names = "core_clk", "phy_clk", "ref_clk"; 1699 dma-coherent; 1700 }; 1701 }; 1702 1703 mhdp: dp-bridge@a000000 { 1704 compatible = "ti,j721e-mhdp8546"; 1705 /* 1706 * Note: we do not map DPTX PHY area, as that is handled by 1707 * the PHY driver. 1708 */ 1709 reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */ 1710 <0x00 0x04f40000 0x00 0x20>; /* DSS_EDP0_INTG_CFG_VP */ 1711 reg-names = "mhdptx", "j721e-intg"; 1712 1713 clocks = <&k3_clks 151 36>; 1714 1715 interrupt-parent = <&gic500>; 1716 interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; 1717 1718 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; 1719 1720 dp0_ports: ports { 1721 #address-cells = <1>; 1722 #size-cells = <0>; 1723 1724 port@0 { 1725 reg = <0>; 1726 }; 1727 1728 port@4 { 1729 reg = <4>; 1730 }; 1731 }; 1732 }; 1733 1734 dss: dss@4a00000 { 1735 compatible = "ti,j721e-dss"; 1736 reg = 1737 <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 1738 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 1739 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 1740 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 1741 1742 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 1743 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 1744 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 1745 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 1746 1747 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 1748 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 1749 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 1750 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 1751 1752 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 1753 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ 1754 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ 1755 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 1756 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 1757 1758 reg-names = "common_m", "common_s0", 1759 "common_s1", "common_s2", 1760 "vidl1", "vidl2","vid1","vid2", 1761 "ovr1", "ovr2", "ovr3", "ovr4", 1762 "vp1", "vp2", "vp3", "vp4", 1763 "wb"; 1764 1765 clocks = <&k3_clks 152 0>, 1766 <&k3_clks 152 1>, 1767 <&k3_clks 152 4>, 1768 <&k3_clks 152 9>, 1769 <&k3_clks 152 13>; 1770 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 1771 1772 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 1773 1774 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1778 interrupt-names = "common_m", 1779 "common_s0", 1780 "common_s1", 1781 "common_s2"; 1782 1783 dss_ports: ports { 1784 }; 1785 }; 1786 1787 mcasp0: mcasp@2b00000 { 1788 compatible = "ti,am33xx-mcasp-audio"; 1789 reg = <0x0 0x02b00000 0x0 0x2000>, 1790 <0x0 0x02b08000 0x0 0x1000>; 1791 reg-names = "mpu","dat"; 1792 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 1793 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; 1794 interrupt-names = "tx", "rx"; 1795 1796 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 1797 dma-names = "tx", "rx"; 1798 1799 clocks = <&k3_clks 174 1>; 1800 clock-names = "fck"; 1801 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; 1802 status = "disabled"; 1803 }; 1804 1805 mcasp1: mcasp@2b10000 { 1806 compatible = "ti,am33xx-mcasp-audio"; 1807 reg = <0x0 0x02b10000 0x0 0x2000>, 1808 <0x0 0x02b18000 0x0 0x1000>; 1809 reg-names = "mpu","dat"; 1810 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, 1811 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 1812 interrupt-names = "tx", "rx"; 1813 1814 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 1815 dma-names = "tx", "rx"; 1816 1817 clocks = <&k3_clks 175 1>; 1818 clock-names = "fck"; 1819 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; 1820 status = "disabled"; 1821 }; 1822 1823 mcasp2: mcasp@2b20000 { 1824 compatible = "ti,am33xx-mcasp-audio"; 1825 reg = <0x0 0x02b20000 0x0 0x2000>, 1826 <0x0 0x02b28000 0x0 0x1000>; 1827 reg-names = "mpu","dat"; 1828 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 1830 interrupt-names = "tx", "rx"; 1831 1832 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 1833 dma-names = "tx", "rx"; 1834 1835 clocks = <&k3_clks 176 1>; 1836 clock-names = "fck"; 1837 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; 1838 status = "disabled"; 1839 }; 1840 1841 mcasp3: mcasp@2b30000 { 1842 compatible = "ti,am33xx-mcasp-audio"; 1843 reg = <0x0 0x02b30000 0x0 0x2000>, 1844 <0x0 0x02b38000 0x0 0x1000>; 1845 reg-names = "mpu","dat"; 1846 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1848 interrupt-names = "tx", "rx"; 1849 1850 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 1851 dma-names = "tx", "rx"; 1852 1853 clocks = <&k3_clks 177 1>; 1854 clock-names = "fck"; 1855 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; 1856 status = "disabled"; 1857 }; 1858 1859 mcasp4: mcasp@2b40000 { 1860 compatible = "ti,am33xx-mcasp-audio"; 1861 reg = <0x0 0x02b40000 0x0 0x2000>, 1862 <0x0 0x02b48000 0x0 0x1000>; 1863 reg-names = "mpu","dat"; 1864 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 1866 interrupt-names = "tx", "rx"; 1867 1868 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>; 1869 dma-names = "tx", "rx"; 1870 1871 clocks = <&k3_clks 178 1>; 1872 clock-names = "fck"; 1873 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 1874 status = "disabled"; 1875 }; 1876 1877 mcasp5: mcasp@2b50000 { 1878 compatible = "ti,am33xx-mcasp-audio"; 1879 reg = <0x0 0x02b50000 0x0 0x2000>, 1880 <0x0 0x02b58000 0x0 0x1000>; 1881 reg-names = "mpu","dat"; 1882 interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>, 1883 <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>; 1884 interrupt-names = "tx", "rx"; 1885 1886 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>; 1887 dma-names = "tx", "rx"; 1888 1889 clocks = <&k3_clks 179 1>; 1890 clock-names = "fck"; 1891 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 1892 status = "disabled"; 1893 }; 1894 1895 mcasp6: mcasp@2b60000 { 1896 compatible = "ti,am33xx-mcasp-audio"; 1897 reg = <0x0 0x02b60000 0x0 0x2000>, 1898 <0x0 0x02b68000 0x0 0x1000>; 1899 reg-names = "mpu","dat"; 1900 interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>, 1901 <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>; 1902 interrupt-names = "tx", "rx"; 1903 1904 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>; 1905 dma-names = "tx", "rx"; 1906 1907 clocks = <&k3_clks 180 1>; 1908 clock-names = "fck"; 1909 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; 1910 status = "disabled"; 1911 }; 1912 1913 mcasp7: mcasp@2b70000 { 1914 compatible = "ti,am33xx-mcasp-audio"; 1915 reg = <0x0 0x02b70000 0x0 0x2000>, 1916 <0x0 0x02b78000 0x0 0x1000>; 1917 reg-names = "mpu","dat"; 1918 interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>, 1919 <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>; 1920 interrupt-names = "tx", "rx"; 1921 1922 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>; 1923 dma-names = "tx", "rx"; 1924 1925 clocks = <&k3_clks 181 1>; 1926 clock-names = "fck"; 1927 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; 1928 status = "disabled"; 1929 }; 1930 1931 mcasp8: mcasp@2b80000 { 1932 compatible = "ti,am33xx-mcasp-audio"; 1933 reg = <0x0 0x02b80000 0x0 0x2000>, 1934 <0x0 0x02b88000 0x0 0x1000>; 1935 reg-names = "mpu","dat"; 1936 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>, 1937 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; 1938 interrupt-names = "tx", "rx"; 1939 1940 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>; 1941 dma-names = "tx", "rx"; 1942 1943 clocks = <&k3_clks 182 1>; 1944 clock-names = "fck"; 1945 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1946 status = "disabled"; 1947 }; 1948 1949 mcasp9: mcasp@2b90000 { 1950 compatible = "ti,am33xx-mcasp-audio"; 1951 reg = <0x0 0x02b90000 0x0 0x2000>, 1952 <0x0 0x02b98000 0x0 0x1000>; 1953 reg-names = "mpu","dat"; 1954 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>, 1955 <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>; 1956 interrupt-names = "tx", "rx"; 1957 1958 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>; 1959 dma-names = "tx", "rx"; 1960 1961 clocks = <&k3_clks 183 1>; 1962 clock-names = "fck"; 1963 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; 1964 status = "disabled"; 1965 }; 1966 1967 mcasp10: mcasp@2ba0000 { 1968 compatible = "ti,am33xx-mcasp-audio"; 1969 reg = <0x0 0x02ba0000 0x0 0x2000>, 1970 <0x0 0x02ba8000 0x0 0x1000>; 1971 reg-names = "mpu","dat"; 1972 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>, 1973 <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; 1974 interrupt-names = "tx", "rx"; 1975 1976 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>; 1977 dma-names = "tx", "rx"; 1978 1979 clocks = <&k3_clks 184 1>; 1980 clock-names = "fck"; 1981 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 1982 status = "disabled"; 1983 }; 1984 1985 mcasp11: mcasp@2bb0000 { 1986 compatible = "ti,am33xx-mcasp-audio"; 1987 reg = <0x0 0x02bb0000 0x0 0x2000>, 1988 <0x0 0x02bb8000 0x0 0x1000>; 1989 reg-names = "mpu","dat"; 1990 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>, 1991 <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>; 1992 interrupt-names = "tx", "rx"; 1993 1994 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>; 1995 dma-names = "tx", "rx"; 1996 1997 clocks = <&k3_clks 185 1>; 1998 clock-names = "fck"; 1999 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 2000 status = "disabled"; 2001 }; 2002 2003 watchdog0: watchdog@2200000 { 2004 compatible = "ti,j7-rti-wdt"; 2005 reg = <0x0 0x2200000 0x0 0x100>; 2006 clocks = <&k3_clks 252 1>; 2007 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 2008 assigned-clocks = <&k3_clks 252 1>; 2009 assigned-clock-parents = <&k3_clks 252 5>; 2010 }; 2011 2012 watchdog1: watchdog@2210000 { 2013 compatible = "ti,j7-rti-wdt"; 2014 reg = <0x0 0x2210000 0x0 0x100>; 2015 clocks = <&k3_clks 253 1>; 2016 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 2017 assigned-clocks = <&k3_clks 253 1>; 2018 assigned-clock-parents = <&k3_clks 253 5>; 2019 }; 2020 2021 main_r5fss0: r5fss@5c00000 { 2022 compatible = "ti,j721e-r5fss"; 2023 ti,cluster-mode = <1>; 2024 #address-cells = <1>; 2025 #size-cells = <1>; 2026 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 2027 <0x5d00000 0x00 0x5d00000 0x20000>; 2028 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; 2029 2030 main_r5fss0_core0: r5f@5c00000 { 2031 compatible = "ti,j721e-r5f"; 2032 reg = <0x5c00000 0x00008000>, 2033 <0x5c10000 0x00008000>; 2034 reg-names = "atcm", "btcm"; 2035 ti,sci = <&dmsc>; 2036 ti,sci-dev-id = <245>; 2037 ti,sci-proc-ids = <0x06 0xff>; 2038 resets = <&k3_reset 245 1>; 2039 firmware-name = "j7-main-r5f0_0-fw"; 2040 ti,atcm-enable = <1>; 2041 ti,btcm-enable = <1>; 2042 ti,loczrama = <1>; 2043 }; 2044 2045 main_r5fss0_core1: r5f@5d00000 { 2046 compatible = "ti,j721e-r5f"; 2047 reg = <0x5d00000 0x00008000>, 2048 <0x5d10000 0x00008000>; 2049 reg-names = "atcm", "btcm"; 2050 ti,sci = <&dmsc>; 2051 ti,sci-dev-id = <246>; 2052 ti,sci-proc-ids = <0x07 0xff>; 2053 resets = <&k3_reset 246 1>; 2054 firmware-name = "j7-main-r5f0_1-fw"; 2055 ti,atcm-enable = <1>; 2056 ti,btcm-enable = <1>; 2057 ti,loczrama = <1>; 2058 }; 2059 }; 2060 2061 main_r5fss1: r5fss@5e00000 { 2062 compatible = "ti,j721e-r5fss"; 2063 ti,cluster-mode = <1>; 2064 #address-cells = <1>; 2065 #size-cells = <1>; 2066 ranges = <0x5e00000 0x00 0x5e00000 0x20000>, 2067 <0x5f00000 0x00 0x5f00000 0x20000>; 2068 power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; 2069 2070 main_r5fss1_core0: r5f@5e00000 { 2071 compatible = "ti,j721e-r5f"; 2072 reg = <0x5e00000 0x00008000>, 2073 <0x5e10000 0x00008000>; 2074 reg-names = "atcm", "btcm"; 2075 ti,sci = <&dmsc>; 2076 ti,sci-dev-id = <247>; 2077 ti,sci-proc-ids = <0x08 0xff>; 2078 resets = <&k3_reset 247 1>; 2079 firmware-name = "j7-main-r5f1_0-fw"; 2080 ti,atcm-enable = <1>; 2081 ti,btcm-enable = <1>; 2082 ti,loczrama = <1>; 2083 }; 2084 2085 main_r5fss1_core1: r5f@5f00000 { 2086 compatible = "ti,j721e-r5f"; 2087 reg = <0x5f00000 0x00008000>, 2088 <0x5f10000 0x00008000>; 2089 reg-names = "atcm", "btcm"; 2090 ti,sci = <&dmsc>; 2091 ti,sci-dev-id = <248>; 2092 ti,sci-proc-ids = <0x09 0xff>; 2093 resets = <&k3_reset 248 1>; 2094 firmware-name = "j7-main-r5f1_1-fw"; 2095 ti,atcm-enable = <1>; 2096 ti,btcm-enable = <1>; 2097 ti,loczrama = <1>; 2098 }; 2099 }; 2100 2101 c66_0: dsp@4d80800000 { 2102 compatible = "ti,j721e-c66-dsp"; 2103 reg = <0x4d 0x80800000 0x00 0x00048000>, 2104 <0x4d 0x80e00000 0x00 0x00008000>, 2105 <0x4d 0x80f00000 0x00 0x00008000>; 2106 reg-names = "l2sram", "l1pram", "l1dram"; 2107 ti,sci = <&dmsc>; 2108 ti,sci-dev-id = <142>; 2109 ti,sci-proc-ids = <0x03 0xff>; 2110 resets = <&k3_reset 142 1>; 2111 firmware-name = "j7-c66_0-fw"; 2112 }; 2113 2114 c66_1: dsp@4d81800000 { 2115 compatible = "ti,j721e-c66-dsp"; 2116 reg = <0x4d 0x81800000 0x00 0x00048000>, 2117 <0x4d 0x81e00000 0x00 0x00008000>, 2118 <0x4d 0x81f00000 0x00 0x00008000>; 2119 reg-names = "l2sram", "l1pram", "l1dram"; 2120 ti,sci = <&dmsc>; 2121 ti,sci-dev-id = <143>; 2122 ti,sci-proc-ids = <0x04 0xff>; 2123 resets = <&k3_reset 143 1>; 2124 firmware-name = "j7-c66_1-fw"; 2125 }; 2126 2127 c71_0: dsp@64800000 { 2128 compatible = "ti,j721e-c71-dsp"; 2129 reg = <0x00 0x64800000 0x00 0x00080000>, 2130 <0x00 0x64e00000 0x00 0x0000c000>; 2131 reg-names = "l2sram", "l1dram"; 2132 ti,sci = <&dmsc>; 2133 ti,sci-dev-id = <15>; 2134 ti,sci-proc-ids = <0x30 0xff>; 2135 resets = <&k3_reset 15 1>; 2136 firmware-name = "j7-c71_0-fw"; 2137 }; 2138 2139 icssg0: icssg@b000000 { 2140 compatible = "ti,j721e-icssg"; 2141 reg = <0x00 0xb000000 0x00 0x80000>; 2142 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; 2143 #address-cells = <1>; 2144 #size-cells = <1>; 2145 ranges = <0x0 0x00 0x0b000000 0x100000>; 2146 2147 icssg0_mem: memories@0 { 2148 reg = <0x0 0x2000>, 2149 <0x2000 0x2000>, 2150 <0x10000 0x10000>; 2151 reg-names = "dram0", "dram1", 2152 "shrdram2"; 2153 }; 2154 2155 icssg0_cfg: cfg@26000 { 2156 compatible = "ti,pruss-cfg", "syscon"; 2157 reg = <0x26000 0x200>; 2158 #address-cells = <1>; 2159 #size-cells = <1>; 2160 ranges = <0x0 0x26000 0x2000>; 2161 2162 clocks { 2163 #address-cells = <1>; 2164 #size-cells = <0>; 2165 2166 icssg0_coreclk_mux: coreclk-mux@3c { 2167 reg = <0x3c>; 2168 #clock-cells = <0>; 2169 clocks = <&k3_clks 119 24>, /* icssg0_core_clk */ 2170 <&k3_clks 119 1>; /* icssg0_iclk */ 2171 assigned-clocks = <&icssg0_coreclk_mux>; 2172 assigned-clock-parents = <&k3_clks 119 1>; 2173 }; 2174 2175 icssg0_iepclk_mux: iepclk-mux@30 { 2176 reg = <0x30>; 2177 #clock-cells = <0>; 2178 clocks = <&k3_clks 119 3>, /* icssg0_iep_clk */ 2179 <&icssg0_coreclk_mux>; /* core_clk */ 2180 assigned-clocks = <&icssg0_iepclk_mux>; 2181 assigned-clock-parents = <&icssg0_coreclk_mux>; 2182 }; 2183 }; 2184 }; 2185 2186 icssg0_mii_rt: mii-rt@32000 { 2187 compatible = "ti,pruss-mii", "syscon"; 2188 reg = <0x32000 0x100>; 2189 }; 2190 2191 icssg0_mii_g_rt: mii-g-rt@33000 { 2192 compatible = "ti,pruss-mii-g", "syscon"; 2193 reg = <0x33000 0x1000>; 2194 }; 2195 2196 icssg0_intc: interrupt-controller@20000 { 2197 compatible = "ti,icssg-intc"; 2198 reg = <0x20000 0x2000>; 2199 interrupt-controller; 2200 #interrupt-cells = <3>; 2201 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 2202 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 2203 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2204 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 2205 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 2206 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 2207 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2208 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 2209 interrupt-names = "host_intr0", "host_intr1", 2210 "host_intr2", "host_intr3", 2211 "host_intr4", "host_intr5", 2212 "host_intr6", "host_intr7"; 2213 }; 2214 2215 pru0_0: pru@34000 { 2216 compatible = "ti,j721e-pru"; 2217 reg = <0x34000 0x3000>, 2218 <0x22000 0x100>, 2219 <0x22400 0x100>; 2220 reg-names = "iram", "control", "debug"; 2221 firmware-name = "j7-pru0_0-fw"; 2222 }; 2223 2224 rtu0_0: rtu@4000 { 2225 compatible = "ti,j721e-rtu"; 2226 reg = <0x4000 0x2000>, 2227 <0x23000 0x100>, 2228 <0x23400 0x100>; 2229 reg-names = "iram", "control", "debug"; 2230 firmware-name = "j7-rtu0_0-fw"; 2231 }; 2232 2233 tx_pru0_0: txpru@a000 { 2234 compatible = "ti,j721e-tx-pru"; 2235 reg = <0xa000 0x1800>, 2236 <0x25000 0x100>, 2237 <0x25400 0x100>; 2238 reg-names = "iram", "control", "debug"; 2239 firmware-name = "j7-txpru0_0-fw"; 2240 }; 2241 2242 pru0_1: pru@38000 { 2243 compatible = "ti,j721e-pru"; 2244 reg = <0x38000 0x3000>, 2245 <0x24000 0x100>, 2246 <0x24400 0x100>; 2247 reg-names = "iram", "control", "debug"; 2248 firmware-name = "j7-pru0_1-fw"; 2249 }; 2250 2251 rtu0_1: rtu@6000 { 2252 compatible = "ti,j721e-rtu"; 2253 reg = <0x6000 0x2000>, 2254 <0x23800 0x100>, 2255 <0x23c00 0x100>; 2256 reg-names = "iram", "control", "debug"; 2257 firmware-name = "j7-rtu0_1-fw"; 2258 }; 2259 2260 tx_pru0_1: txpru@c000 { 2261 compatible = "ti,j721e-tx-pru"; 2262 reg = <0xc000 0x1800>, 2263 <0x25800 0x100>, 2264 <0x25c00 0x100>; 2265 reg-names = "iram", "control", "debug"; 2266 firmware-name = "j7-txpru0_1-fw"; 2267 }; 2268 2269 icssg0_mdio: mdio@32400 { 2270 compatible = "ti,davinci_mdio"; 2271 reg = <0x32400 0x100>; 2272 clocks = <&k3_clks 119 1>; 2273 clock-names = "fck"; 2274 #address-cells = <1>; 2275 #size-cells = <0>; 2276 bus_freq = <1000000>; 2277 status = "disabled"; 2278 }; 2279 }; 2280 2281 icssg1: icssg@b100000 { 2282 compatible = "ti,j721e-icssg"; 2283 reg = <0x00 0xb100000 0x00 0x80000>; 2284 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 2285 #address-cells = <1>; 2286 #size-cells = <1>; 2287 ranges = <0x0 0x00 0x0b100000 0x100000>; 2288 2289 icssg1_mem: memories@b100000 { 2290 reg = <0x0 0x2000>, 2291 <0x2000 0x2000>, 2292 <0x10000 0x10000>; 2293 reg-names = "dram0", "dram1", 2294 "shrdram2"; 2295 }; 2296 2297 icssg1_cfg: cfg@26000 { 2298 compatible = "ti,pruss-cfg", "syscon"; 2299 reg = <0x26000 0x200>; 2300 #address-cells = <1>; 2301 #size-cells = <1>; 2302 ranges = <0x0 0x26000 0x2000>; 2303 2304 clocks { 2305 #address-cells = <1>; 2306 #size-cells = <0>; 2307 2308 icssg1_coreclk_mux: coreclk-mux@3c { 2309 reg = <0x3c>; 2310 #clock-cells = <0>; 2311 clocks = <&k3_clks 120 54>, /* icssg1_core_clk */ 2312 <&k3_clks 120 4>; /* icssg1_iclk */ 2313 assigned-clocks = <&icssg1_coreclk_mux>; 2314 assigned-clock-parents = <&k3_clks 120 4>; 2315 }; 2316 2317 icssg1_iepclk_mux: iepclk-mux@30 { 2318 reg = <0x30>; 2319 #clock-cells = <0>; 2320 clocks = <&k3_clks 120 9>, /* icssg1_iep_clk */ 2321 <&icssg1_coreclk_mux>; /* core_clk */ 2322 assigned-clocks = <&icssg1_iepclk_mux>; 2323 assigned-clock-parents = <&icssg1_coreclk_mux>; 2324 }; 2325 }; 2326 }; 2327 2328 icssg1_mii_rt: mii-rt@32000 { 2329 compatible = "ti,pruss-mii", "syscon"; 2330 reg = <0x32000 0x100>; 2331 }; 2332 2333 icssg1_mii_g_rt: mii-g-rt@33000 { 2334 compatible = "ti,pruss-mii-g", "syscon"; 2335 reg = <0x33000 0x1000>; 2336 }; 2337 2338 icssg1_intc: interrupt-controller@20000 { 2339 compatible = "ti,icssg-intc"; 2340 reg = <0x20000 0x2000>; 2341 interrupt-controller; 2342 #interrupt-cells = <3>; 2343 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2344 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2345 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 2346 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 2347 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2348 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2349 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2350 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 2351 interrupt-names = "host_intr0", "host_intr1", 2352 "host_intr2", "host_intr3", 2353 "host_intr4", "host_intr5", 2354 "host_intr6", "host_intr7"; 2355 }; 2356 2357 pru1_0: pru@34000 { 2358 compatible = "ti,j721e-pru"; 2359 reg = <0x34000 0x4000>, 2360 <0x22000 0x100>, 2361 <0x22400 0x100>; 2362 reg-names = "iram", "control", "debug"; 2363 firmware-name = "j7-pru1_0-fw"; 2364 }; 2365 2366 rtu1_0: rtu@4000 { 2367 compatible = "ti,j721e-rtu"; 2368 reg = <0x4000 0x2000>, 2369 <0x23000 0x100>, 2370 <0x23400 0x100>; 2371 reg-names = "iram", "control", "debug"; 2372 firmware-name = "j7-rtu1_0-fw"; 2373 }; 2374 2375 tx_pru1_0: txpru@a000 { 2376 compatible = "ti,j721e-tx-pru"; 2377 reg = <0xa000 0x1800>, 2378 <0x25000 0x100>, 2379 <0x25400 0x100>; 2380 reg-names = "iram", "control", "debug"; 2381 firmware-name = "j7-txpru1_0-fw"; 2382 }; 2383 2384 pru1_1: pru@38000 { 2385 compatible = "ti,j721e-pru"; 2386 reg = <0x38000 0x4000>, 2387 <0x24000 0x100>, 2388 <0x24400 0x100>; 2389 reg-names = "iram", "control", "debug"; 2390 firmware-name = "j7-pru1_1-fw"; 2391 }; 2392 2393 rtu1_1: rtu@6000 { 2394 compatible = "ti,j721e-rtu"; 2395 reg = <0x6000 0x2000>, 2396 <0x23800 0x100>, 2397 <0x23c00 0x100>; 2398 reg-names = "iram", "control", "debug"; 2399 firmware-name = "j7-rtu1_1-fw"; 2400 }; 2401 2402 tx_pru1_1: txpru@c000 { 2403 compatible = "ti,j721e-tx-pru"; 2404 reg = <0xc000 0x1800>, 2405 <0x25800 0x100>, 2406 <0x25c00 0x100>; 2407 reg-names = "iram", "control", "debug"; 2408 firmware-name = "j7-txpru1_1-fw"; 2409 }; 2410 2411 icssg1_mdio: mdio@32400 { 2412 compatible = "ti,davinci_mdio"; 2413 reg = <0x32400 0x100>; 2414 clocks = <&k3_clks 120 4>; 2415 clock-names = "fck"; 2416 #address-cells = <1>; 2417 #size-cells = <0>; 2418 bus_freq = <1000000>; 2419 status = "disabled"; 2420 }; 2421 }; 2422 2423 main_mcan0: can@2701000 { 2424 compatible = "bosch,m_can"; 2425 reg = <0x00 0x02701000 0x00 0x200>, 2426 <0x00 0x02708000 0x00 0x8000>; 2427 reg-names = "m_can", "message_ram"; 2428 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 2429 clocks = <&k3_clks 156 0>, <&k3_clks 156 1>; 2430 clock-names = "hclk", "cclk"; 2431 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 2432 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2433 interrupt-names = "int0", "int1"; 2434 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2435 status = "disabled"; 2436 }; 2437 2438 main_mcan1: can@2711000 { 2439 compatible = "bosch,m_can"; 2440 reg = <0x00 0x02711000 0x00 0x200>, 2441 <0x00 0x02718000 0x00 0x8000>; 2442 reg-names = "m_can", "message_ram"; 2443 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 2444 clocks = <&k3_clks 158 0>, <&k3_clks 158 1>; 2445 clock-names = "hclk", "cclk"; 2446 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 2447 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 2448 interrupt-names = "int0", "int1"; 2449 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2450 status = "disabled"; 2451 }; 2452 2453 main_mcan2: can@2721000 { 2454 compatible = "bosch,m_can"; 2455 reg = <0x00 0x02721000 0x00 0x200>, 2456 <0x00 0x02728000 0x00 0x8000>; 2457 reg-names = "m_can", "message_ram"; 2458 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; 2459 clocks = <&k3_clks 160 0>, <&k3_clks 160 1>; 2460 clock-names = "hclk", "cclk"; 2461 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2462 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 2463 interrupt-names = "int0", "int1"; 2464 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2465 status = "disabled"; 2466 }; 2467 2468 main_mcan3: can@2731000 { 2469 compatible = "bosch,m_can"; 2470 reg = <0x00 0x02731000 0x00 0x200>, 2471 <0x00 0x02738000 0x00 0x8000>; 2472 reg-names = "m_can", "message_ram"; 2473 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 2474 clocks = <&k3_clks 161 0>, <&k3_clks 161 1>; 2475 clock-names = "hclk", "cclk"; 2476 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 2477 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 2478 interrupt-names = "int0", "int1"; 2479 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2480 status = "disabled"; 2481 }; 2482 2483 main_mcan4: can@2741000 { 2484 compatible = "bosch,m_can"; 2485 reg = <0x00 0x02741000 0x00 0x200>, 2486 <0x00 0x02748000 0x00 0x8000>; 2487 reg-names = "m_can", "message_ram"; 2488 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 2489 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>; 2490 clock-names = "hclk", "cclk"; 2491 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2492 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 2493 interrupt-names = "int0", "int1"; 2494 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2495 status = "disabled"; 2496 }; 2497 2498 main_mcan5: can@2751000 { 2499 compatible = "bosch,m_can"; 2500 reg = <0x00 0x02751000 0x00 0x200>, 2501 <0x00 0x02758000 0x00 0x8000>; 2502 reg-names = "m_can", "message_ram"; 2503 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; 2504 clocks = <&k3_clks 163 0>, <&k3_clks 163 1>; 2505 clock-names = "hclk", "cclk"; 2506 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 2507 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2508 interrupt-names = "int0", "int1"; 2509 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2510 status = "disabled"; 2511 }; 2512 2513 main_mcan6: can@2761000 { 2514 compatible = "bosch,m_can"; 2515 reg = <0x00 0x02761000 0x00 0x200>, 2516 <0x00 0x02768000 0x00 0x8000>; 2517 reg-names = "m_can", "message_ram"; 2518 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; 2519 clocks = <&k3_clks 164 0>, <&k3_clks 164 1>; 2520 clock-names = "hclk", "cclk"; 2521 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2522 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 2523 interrupt-names = "int0", "int1"; 2524 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2525 status = "disabled"; 2526 }; 2527 2528 main_mcan7: can@2771000 { 2529 compatible = "bosch,m_can"; 2530 reg = <0x00 0x02771000 0x00 0x200>, 2531 <0x00 0x02778000 0x00 0x8000>; 2532 reg-names = "m_can", "message_ram"; 2533 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; 2534 clocks = <&k3_clks 165 0>, <&k3_clks 165 1>; 2535 clock-names = "hclk", "cclk"; 2536 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2537 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 2538 interrupt-names = "int0", "int1"; 2539 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2540 status = "disabled"; 2541 }; 2542 2543 main_mcan8: can@2781000 { 2544 compatible = "bosch,m_can"; 2545 reg = <0x00 0x02781000 0x00 0x200>, 2546 <0x00 0x02788000 0x00 0x8000>; 2547 reg-names = "m_can", "message_ram"; 2548 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; 2549 clocks = <&k3_clks 166 0>, <&k3_clks 166 1>; 2550 clock-names = "hclk", "cclk"; 2551 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 2552 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 2553 interrupt-names = "int0", "int1"; 2554 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2555 status = "disabled"; 2556 }; 2557 2558 main_mcan9: can@2791000 { 2559 compatible = "bosch,m_can"; 2560 reg = <0x00 0x02791000 0x00 0x200>, 2561 <0x00 0x02798000 0x00 0x8000>; 2562 reg-names = "m_can", "message_ram"; 2563 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>; 2564 clocks = <&k3_clks 167 0>, <&k3_clks 167 1>; 2565 clock-names = "hclk", "cclk"; 2566 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, 2567 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 2568 interrupt-names = "int0", "int1"; 2569 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2570 status = "disabled"; 2571 }; 2572 2573 main_mcan10: can@27a1000 { 2574 compatible = "bosch,m_can"; 2575 reg = <0x00 0x027a1000 0x00 0x200>, 2576 <0x00 0x027a8000 0x00 0x8000>; 2577 reg-names = "m_can", "message_ram"; 2578 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>; 2579 clocks = <&k3_clks 168 0>, <&k3_clks 168 1>; 2580 clock-names = "hclk", "cclk"; 2581 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, 2582 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2583 interrupt-names = "int0", "int1"; 2584 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2585 status = "disabled"; 2586 }; 2587 2588 main_mcan11: can@27b1000 { 2589 compatible = "bosch,m_can"; 2590 reg = <0x00 0x027b1000 0x00 0x200>, 2591 <0x00 0x027b8000 0x00 0x8000>; 2592 reg-names = "m_can", "message_ram"; 2593 power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>; 2594 clocks = <&k3_clks 169 0>, <&k3_clks 169 1>; 2595 clock-names = "hclk", "cclk"; 2596 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 2597 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2598 interrupt-names = "int0", "int1"; 2599 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2600 status = "disabled"; 2601 }; 2602 2603 main_mcan12: can@27c1000 { 2604 compatible = "bosch,m_can"; 2605 reg = <0x00 0x027c1000 0x00 0x200>, 2606 <0x00 0x027c8000 0x00 0x8000>; 2607 reg-names = "m_can", "message_ram"; 2608 power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>; 2609 clocks = <&k3_clks 170 0>, <&k3_clks 170 1>; 2610 clock-names = "hclk", "cclk"; 2611 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 2612 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 2613 interrupt-names = "int0", "int1"; 2614 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2615 status = "disabled"; 2616 }; 2617 2618 main_mcan13: can@27d1000 { 2619 compatible = "bosch,m_can"; 2620 reg = <0x00 0x027d1000 0x00 0x200>, 2621 <0x00 0x027d8000 0x00 0x8000>; 2622 reg-names = "m_can", "message_ram"; 2623 power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>; 2624 clocks = <&k3_clks 171 0>, <&k3_clks 171 1>; 2625 clock-names = "hclk", "cclk"; 2626 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 2627 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 2628 interrupt-names = "int0", "int1"; 2629 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2630 status = "disabled"; 2631 }; 2632 2633 main_spi0: spi@2100000 { 2634 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2635 reg = <0x00 0x02100000 0x00 0x400>; 2636 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 2637 #address-cells = <1>; 2638 #size-cells = <0>; 2639 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; 2640 clocks = <&k3_clks 266 1>; 2641 status = "disabled"; 2642 }; 2643 2644 main_spi1: spi@2110000 { 2645 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2646 reg = <0x00 0x02110000 0x00 0x400>; 2647 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 2648 #address-cells = <1>; 2649 #size-cells = <0>; 2650 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; 2651 clocks = <&k3_clks 267 1>; 2652 status = "disabled"; 2653 }; 2654 2655 main_spi2: spi@2120000 { 2656 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2657 reg = <0x00 0x02120000 0x00 0x400>; 2658 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 2659 #address-cells = <1>; 2660 #size-cells = <0>; 2661 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; 2662 clocks = <&k3_clks 268 1>; 2663 status = "disabled"; 2664 }; 2665 2666 main_spi3: spi@2130000 { 2667 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2668 reg = <0x00 0x02130000 0x00 0x400>; 2669 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 2670 #address-cells = <1>; 2671 #size-cells = <0>; 2672 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; 2673 clocks = <&k3_clks 269 1>; 2674 status = "disabled"; 2675 }; 2676 2677 main_spi4: spi@2140000 { 2678 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2679 reg = <0x00 0x02140000 0x00 0x400>; 2680 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 2681 #address-cells = <1>; 2682 #size-cells = <0>; 2683 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; 2684 clocks = <&k3_clks 270 1>; 2685 status = "disabled"; 2686 }; 2687 2688 main_spi5: spi@2150000 { 2689 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2690 reg = <0x00 0x02150000 0x00 0x400>; 2691 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 2692 #address-cells = <1>; 2693 #size-cells = <0>; 2694 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; 2695 clocks = <&k3_clks 271 1>; 2696 status = "disabled"; 2697 }; 2698 2699 main_spi6: spi@2160000 { 2700 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2701 reg = <0x00 0x02160000 0x00 0x400>; 2702 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 2703 #address-cells = <1>; 2704 #size-cells = <0>; 2705 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; 2706 clocks = <&k3_clks 272 1>; 2707 status = "disabled"; 2708 }; 2709 2710 main_spi7: spi@2170000 { 2711 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2712 reg = <0x00 0x02170000 0x00 0x400>; 2713 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 2714 #address-cells = <1>; 2715 #size-cells = <0>; 2716 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; 2717 clocks = <&k3_clks 273 1>; 2718 status = "disabled"; 2719 }; 2720 2721 main_esm: esm@700000 { 2722 compatible = "ti,j721e-esm"; 2723 reg = <0x0 0x700000 0x0 0x1000>; 2724 ti,esm-pins = <344>, <345>; 2725 }; 2726}; 2727