1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM625 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 oc_sram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x00 0x70000000 0x00 0x10000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x0 0x00 0x70000000 0x10000>; 15 }; 16 17 gic500: interrupt-controller@1800000 { 18 compatible = "arm,gic-v3"; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 ranges; 22 #interrupt-cells = <3>; 23 interrupt-controller; 24 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 25 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 26 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 27 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 28 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 29 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 30 /* 31 * vcpumntirq: 32 * virtual CPU interface maintenance interrupt 33 */ 34 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 35 36 gic_its: msi-controller@1820000 { 37 compatible = "arm,gic-v3-its"; 38 reg = <0x00 0x01820000 0x00 0x10000>; 39 socionext,synquacer-pre-its = <0x1000000 0x400000>; 40 msi-controller; 41 #msi-cells = <1>; 42 }; 43 }; 44 45 main_conf: syscon@100000 { 46 compatible = "syscon", "simple-mfd"; 47 reg = <0x00 0x00100000 0x00 0x20000>; 48 #address-cells = <1>; 49 #size-cells = <1>; 50 ranges = <0x0 0x00 0x00100000 0x20000>; 51 52 phy_gmii_sel: phy@4044 { 53 compatible = "ti,am654-phy-gmii-sel"; 54 reg = <0x4044 0x8>; 55 #phy-cells = <1>; 56 }; 57 58 epwm_tbclk: clock@4130 { 59 compatible = "ti,am62-epwm-tbclk"; 60 reg = <0x4130 0x4>; 61 #clock-cells = <1>; 62 }; 63 }; 64 65 dmss: bus@48000000 { 66 compatible = "simple-mfd"; 67 #address-cells = <2>; 68 #size-cells = <2>; 69 dma-ranges; 70 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; 71 72 ti,sci-dev-id = <25>; 73 74 secure_proxy_main: mailbox@4d000000 { 75 compatible = "ti,am654-secure-proxy"; 76 #mbox-cells = <1>; 77 reg-names = "target_data", "rt", "scfg"; 78 reg = <0x00 0x4d000000 0x00 0x80000>, 79 <0x00 0x4a600000 0x00 0x80000>, 80 <0x00 0x4a400000 0x00 0x80000>; 81 interrupt-names = "rx_012"; 82 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 83 }; 84 85 inta_main_dmss: interrupt-controller@48000000 { 86 compatible = "ti,sci-inta"; 87 reg = <0x00 0x48000000 0x00 0x100000>; 88 #interrupt-cells = <0>; 89 interrupt-controller; 90 interrupt-parent = <&gic500>; 91 msi-controller; 92 ti,sci = <&dmsc>; 93 ti,sci-dev-id = <28>; 94 ti,interrupt-ranges = <4 68 36>; 95 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 96 }; 97 98 main_bcdma: dma-controller@485c0100 { 99 compatible = "ti,am64-dmss-bcdma"; 100 reg = <0x00 0x485c0100 0x00 0x100>, 101 <0x00 0x4c000000 0x00 0x20000>, 102 <0x00 0x4a820000 0x00 0x20000>, 103 <0x00 0x4aa40000 0x00 0x20000>, 104 <0x00 0x4bc00000 0x00 0x100000>; 105 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; 106 msi-parent = <&inta_main_dmss>; 107 #dma-cells = <3>; 108 109 ti,sci = <&dmsc>; 110 ti,sci-dev-id = <26>; 111 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 112 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 113 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 114 }; 115 116 main_pktdma: dma-controller@485c0000 { 117 compatible = "ti,am64-dmss-pktdma"; 118 reg = <0x00 0x485c0000 0x00 0x100>, 119 <0x00 0x4a800000 0x00 0x20000>, 120 <0x00 0x4aa00000 0x00 0x40000>, 121 <0x00 0x4b800000 0x00 0x400000>; 122 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 123 msi-parent = <&inta_main_dmss>; 124 #dma-cells = <2>; 125 126 ti,sci = <&dmsc>; 127 ti,sci-dev-id = <30>; 128 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 129 <0x24>, /* CPSW_TX_CHAN */ 130 <0x25>, /* SAUL_TX_0_CHAN */ 131 <0x26>; /* SAUL_TX_1_CHAN */ 132 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 133 <0x11>, /* RING_CPSW_TX_CHAN */ 134 <0x12>, /* RING_SAUL_TX_0_CHAN */ 135 <0x13>; /* RING_SAUL_TX_1_CHAN */ 136 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 137 <0x2b>, /* CPSW_RX_CHAN */ 138 <0x2d>, /* SAUL_RX_0_CHAN */ 139 <0x2f>, /* SAUL_RX_1_CHAN */ 140 <0x31>, /* SAUL_RX_2_CHAN */ 141 <0x33>; /* SAUL_RX_3_CHAN */ 142 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 143 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 144 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 145 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ 146 }; 147 }; 148 149 dmsc: system-controller@44043000 { 150 compatible = "ti,k2g-sci"; 151 ti,host-id = <12>; 152 mbox-names = "rx", "tx"; 153 mboxes = <&secure_proxy_main 12>, 154 <&secure_proxy_main 13>; 155 reg-names = "debug_messages"; 156 reg = <0x00 0x44043000 0x00 0xfe0>; 157 158 k3_pds: power-controller { 159 compatible = "ti,sci-pm-domain"; 160 #power-domain-cells = <2>; 161 }; 162 163 k3_clks: clock-controller { 164 compatible = "ti,k2g-sci-clk"; 165 #clock-cells = <2>; 166 }; 167 168 k3_reset: reset-controller { 169 compatible = "ti,sci-reset"; 170 #reset-cells = <2>; 171 }; 172 }; 173 174 crypto: crypto@40900000 { 175 compatible = "ti,am62-sa3ul"; 176 reg = <0x00 0x40900000 0x00 0x1200>; 177 #address-cells = <2>; 178 #size-cells = <2>; 179 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; 180 181 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, 182 <&main_pktdma 0x7507 0>; 183 dma-names = "tx", "rx1", "rx2"; 184 }; 185 186 secure_proxy_sa3: mailbox@43600000 { 187 compatible = "ti,am654-secure-proxy"; 188 #mbox-cells = <1>; 189 reg-names = "target_data", "rt", "scfg"; 190 reg = <0x00 0x43600000 0x00 0x10000>, 191 <0x00 0x44880000 0x00 0x20000>, 192 <0x00 0x44860000 0x00 0x20000>; 193 /* 194 * Marked Disabled: 195 * Node is incomplete as it is meant for bootloaders and 196 * firmware on non-MPU processors 197 */ 198 status = "disabled"; 199 }; 200 201 main_pmx0: pinctrl@f4000 { 202 compatible = "pinctrl-single"; 203 reg = <0x00 0xf4000 0x00 0x2ac>; 204 #pinctrl-cells = <1>; 205 pinctrl-single,register-width = <32>; 206 pinctrl-single,function-mask = <0xffffffff>; 207 }; 208 209 main_esm: esm@420000 { 210 compatible = "ti,j721e-esm"; 211 reg = <0x00 0x420000 0x00 0x1000>; 212 ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>; 213 }; 214 215 main_timer0: timer@2400000 { 216 compatible = "ti,am654-timer"; 217 reg = <0x00 0x2400000 0x00 0x400>; 218 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 219 clocks = <&k3_clks 36 2>; 220 clock-names = "fck"; 221 assigned-clocks = <&k3_clks 36 2>; 222 assigned-clock-parents = <&k3_clks 36 3>; 223 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 224 ti,timer-pwm; 225 }; 226 227 main_timer1: timer@2410000 { 228 compatible = "ti,am654-timer"; 229 reg = <0x00 0x2410000 0x00 0x400>; 230 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&k3_clks 37 2>; 232 clock-names = "fck"; 233 assigned-clocks = <&k3_clks 37 2>; 234 assigned-clock-parents = <&k3_clks 37 3>; 235 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; 236 ti,timer-pwm; 237 }; 238 239 main_timer2: timer@2420000 { 240 compatible = "ti,am654-timer"; 241 reg = <0x00 0x2420000 0x00 0x400>; 242 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&k3_clks 38 2>; 244 clock-names = "fck"; 245 assigned-clocks = <&k3_clks 38 2>; 246 assigned-clock-parents = <&k3_clks 38 3>; 247 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 248 ti,timer-pwm; 249 }; 250 251 main_timer3: timer@2430000 { 252 compatible = "ti,am654-timer"; 253 reg = <0x00 0x2430000 0x00 0x400>; 254 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 255 clocks = <&k3_clks 39 2>; 256 clock-names = "fck"; 257 assigned-clocks = <&k3_clks 39 2>; 258 assigned-clock-parents = <&k3_clks 39 3>; 259 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 260 ti,timer-pwm; 261 }; 262 263 main_timer4: timer@2440000 { 264 compatible = "ti,am654-timer"; 265 reg = <0x00 0x2440000 0x00 0x400>; 266 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&k3_clks 40 2>; 268 clock-names = "fck"; 269 assigned-clocks = <&k3_clks 40 2>; 270 assigned-clock-parents = <&k3_clks 40 3>; 271 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 272 ti,timer-pwm; 273 }; 274 275 main_timer5: timer@2450000 { 276 compatible = "ti,am654-timer"; 277 reg = <0x00 0x2450000 0x00 0x400>; 278 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&k3_clks 41 2>; 280 clock-names = "fck"; 281 assigned-clocks = <&k3_clks 41 2>; 282 assigned-clock-parents = <&k3_clks 41 3>; 283 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 284 ti,timer-pwm; 285 }; 286 287 main_timer6: timer@2460000 { 288 compatible = "ti,am654-timer"; 289 reg = <0x00 0x2460000 0x00 0x400>; 290 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&k3_clks 42 2>; 292 clock-names = "fck"; 293 assigned-clocks = <&k3_clks 42 2>; 294 assigned-clock-parents = <&k3_clks 42 3>; 295 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 296 ti,timer-pwm; 297 }; 298 299 main_timer7: timer@2470000 { 300 compatible = "ti,am654-timer"; 301 reg = <0x00 0x2470000 0x00 0x400>; 302 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 303 clocks = <&k3_clks 43 2>; 304 clock-names = "fck"; 305 assigned-clocks = <&k3_clks 43 2>; 306 assigned-clock-parents = <&k3_clks 43 3>; 307 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 308 ti,timer-pwm; 309 }; 310 311 main_uart0: serial@2800000 { 312 compatible = "ti,am64-uart", "ti,am654-uart"; 313 reg = <0x00 0x02800000 0x00 0x100>; 314 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 315 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 316 clocks = <&k3_clks 146 0>; 317 clock-names = "fclk"; 318 status = "disabled"; 319 }; 320 321 main_uart1: serial@2810000 { 322 compatible = "ti,am64-uart", "ti,am654-uart"; 323 reg = <0x00 0x02810000 0x00 0x100>; 324 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 325 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 326 clocks = <&k3_clks 152 0>; 327 clock-names = "fclk"; 328 status = "disabled"; 329 }; 330 331 main_uart2: serial@2820000 { 332 compatible = "ti,am64-uart", "ti,am654-uart"; 333 reg = <0x00 0x02820000 0x00 0x100>; 334 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 335 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 336 clocks = <&k3_clks 153 0>; 337 clock-names = "fclk"; 338 status = "disabled"; 339 }; 340 341 main_uart3: serial@2830000 { 342 compatible = "ti,am64-uart", "ti,am654-uart"; 343 reg = <0x00 0x02830000 0x00 0x100>; 344 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 345 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 346 clocks = <&k3_clks 154 0>; 347 clock-names = "fclk"; 348 status = "disabled"; 349 }; 350 351 main_uart4: serial@2840000 { 352 compatible = "ti,am64-uart", "ti,am654-uart"; 353 reg = <0x00 0x02840000 0x00 0x100>; 354 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 355 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 356 clocks = <&k3_clks 155 0>; 357 clock-names = "fclk"; 358 status = "disabled"; 359 }; 360 361 main_uart5: serial@2850000 { 362 compatible = "ti,am64-uart", "ti,am654-uart"; 363 reg = <0x00 0x02850000 0x00 0x100>; 364 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 365 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 366 clocks = <&k3_clks 156 0>; 367 clock-names = "fclk"; 368 status = "disabled"; 369 }; 370 371 main_uart6: serial@2860000 { 372 compatible = "ti,am64-uart", "ti,am654-uart"; 373 reg = <0x00 0x02860000 0x00 0x100>; 374 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 375 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 376 clocks = <&k3_clks 158 0>; 377 clock-names = "fclk"; 378 status = "disabled"; 379 }; 380 381 main_i2c0: i2c@20000000 { 382 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 383 reg = <0x00 0x20000000 0x00 0x100>; 384 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 385 #address-cells = <1>; 386 #size-cells = <0>; 387 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 388 clocks = <&k3_clks 102 2>; 389 clock-names = "fck"; 390 status = "disabled"; 391 }; 392 393 main_i2c1: i2c@20010000 { 394 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 395 reg = <0x00 0x20010000 0x00 0x100>; 396 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 397 #address-cells = <1>; 398 #size-cells = <0>; 399 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 400 clocks = <&k3_clks 103 2>; 401 clock-names = "fck"; 402 status = "disabled"; 403 }; 404 405 main_i2c2: i2c@20020000 { 406 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 407 reg = <0x00 0x20020000 0x00 0x100>; 408 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 412 clocks = <&k3_clks 104 2>; 413 clock-names = "fck"; 414 status = "disabled"; 415 }; 416 417 main_i2c3: i2c@20030000 { 418 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 419 reg = <0x00 0x20030000 0x00 0x100>; 420 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 421 #address-cells = <1>; 422 #size-cells = <0>; 423 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 424 clocks = <&k3_clks 105 2>; 425 clock-names = "fck"; 426 status = "disabled"; 427 }; 428 429 main_spi0: spi@20100000 { 430 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 431 reg = <0x00 0x20100000 0x00 0x400>; 432 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 433 #address-cells = <1>; 434 #size-cells = <0>; 435 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 436 clocks = <&k3_clks 141 0>; 437 status = "disabled"; 438 }; 439 440 main_spi1: spi@20110000 { 441 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 442 reg = <0x00 0x20110000 0x00 0x400>; 443 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 447 clocks = <&k3_clks 142 0>; 448 status = "disabled"; 449 }; 450 451 main_spi2: spi@20120000 { 452 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 453 reg = <0x00 0x20120000 0x00 0x400>; 454 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 458 clocks = <&k3_clks 143 0>; 459 status = "disabled"; 460 }; 461 462 main_gpio_intr: interrupt-controller@a00000 { 463 compatible = "ti,sci-intr"; 464 reg = <0x00 0x00a00000 0x00 0x800>; 465 ti,intr-trigger-type = <1>; 466 interrupt-controller; 467 interrupt-parent = <&gic500>; 468 #interrupt-cells = <1>; 469 ti,sci = <&dmsc>; 470 ti,sci-dev-id = <3>; 471 ti,interrupt-ranges = <0 32 16>; 472 }; 473 474 main_gpio0: gpio@600000 { 475 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 476 reg = <0x0 0x00600000 0x0 0x100>; 477 gpio-controller; 478 #gpio-cells = <2>; 479 interrupt-parent = <&main_gpio_intr>; 480 interrupts = <190>, <191>, <192>, 481 <193>, <194>, <195>; 482 interrupt-controller; 483 #interrupt-cells = <2>; 484 ti,ngpio = <92>; 485 ti,davinci-gpio-unbanked = <0>; 486 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 487 clocks = <&k3_clks 77 0>; 488 clock-names = "gpio"; 489 }; 490 491 main_gpio1: gpio@601000 { 492 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 493 reg = <0x0 0x00601000 0x0 0x100>; 494 gpio-controller; 495 #gpio-cells = <2>; 496 interrupt-parent = <&main_gpio_intr>; 497 interrupts = <180>, <181>, <182>, 498 <183>, <184>, <185>; 499 interrupt-controller; 500 #interrupt-cells = <2>; 501 ti,ngpio = <52>; 502 ti,davinci-gpio-unbanked = <0>; 503 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 504 clocks = <&k3_clks 78 0>; 505 clock-names = "gpio"; 506 }; 507 508 sdhci0: mmc@fa10000 { 509 compatible = "ti,am62-sdhci"; 510 reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>; 511 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 512 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 513 clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; 514 clock-names = "clk_ahb", "clk_xin"; 515 assigned-clocks = <&k3_clks 57 6>; 516 assigned-clock-parents = <&k3_clks 57 8>; 517 mmc-ddr-1_8v; 518 mmc-hs200-1_8v; 519 ti,trm-icp = <0x2>; 520 bus-width = <8>; 521 ti,clkbuf-sel = <0x7>; 522 ti,otap-del-sel-legacy = <0x0>; 523 ti,otap-del-sel-mmc-hs = <0x0>; 524 ti,otap-del-sel-ddr52 = <0x5>; 525 ti,otap-del-sel-hs200 = <0x5>; 526 ti,itap-del-sel-legacy = <0xa>; 527 ti,itap-del-sel-mmc-hs = <0x1>; 528 status = "disabled"; 529 }; 530 531 sdhci1: mmc@fa00000 { 532 compatible = "ti,am62-sdhci"; 533 reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>; 534 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 535 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 536 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; 537 clock-names = "clk_ahb", "clk_xin"; 538 ti,trm-icp = <0x2>; 539 ti,otap-del-sel-legacy = <0x8>; 540 ti,otap-del-sel-sd-hs = <0x0>; 541 ti,otap-del-sel-sdr12 = <0x0>; 542 ti,otap-del-sel-sdr25 = <0x0>; 543 ti,otap-del-sel-sdr50 = <0x8>; 544 ti,otap-del-sel-sdr104 = <0x7>; 545 ti,otap-del-sel-ddr50 = <0x4>; 546 ti,itap-del-sel-legacy = <0xa>; 547 ti,itap-del-sel-sd-hs = <0x1>; 548 ti,itap-del-sel-sdr12 = <0xa>; 549 ti,itap-del-sel-sdr25 = <0x1>; 550 ti,clkbuf-sel = <0x7>; 551 bus-width = <4>; 552 status = "disabled"; 553 }; 554 555 sdhci2: mmc@fa20000 { 556 compatible = "ti,am62-sdhci"; 557 reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>; 558 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 559 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 560 clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; 561 clock-names = "clk_ahb", "clk_xin"; 562 ti,trm-icp = <0x2>; 563 ti,otap-del-sel-legacy = <0x8>; 564 ti,otap-del-sel-sd-hs = <0x0>; 565 ti,otap-del-sel-sdr12 = <0x0>; 566 ti,otap-del-sel-sdr25 = <0x0>; 567 ti,otap-del-sel-sdr50 = <0x8>; 568 ti,otap-del-sel-sdr104 = <0x7>; 569 ti,otap-del-sel-ddr50 = <0x8>; 570 ti,itap-del-sel-legacy = <0xa>; 571 ti,itap-del-sel-sd-hs = <0xa>; 572 ti,itap-del-sel-sdr12 = <0xa>; 573 ti,itap-del-sel-sdr25 = <0x1>; 574 ti,clkbuf-sel = <0x7>; 575 status = "disabled"; 576 }; 577 578 usbss0: dwc3-usb@f900000 { 579 compatible = "ti,am62-usb"; 580 reg = <0x00 0x0f900000 0x00 0x800>; 581 clocks = <&k3_clks 161 3>; 582 clock-names = "ref"; 583 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>; 584 #address-cells = <2>; 585 #size-cells = <2>; 586 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 587 ranges; 588 status = "disabled"; 589 590 usb0: usb@31000000 { 591 compatible = "snps,dwc3"; 592 reg = <0x00 0x31000000 0x00 0x50000>; 593 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 594 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 595 interrupt-names = "host", "peripheral"; 596 maximum-speed = "high-speed"; 597 dr_mode = "otg"; 598 }; 599 }; 600 601 usbss1: dwc3-usb@f910000 { 602 compatible = "ti,am62-usb"; 603 reg = <0x00 0x0f910000 0x00 0x800>; 604 clocks = <&k3_clks 162 3>; 605 clock-names = "ref"; 606 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>; 607 #address-cells = <2>; 608 #size-cells = <2>; 609 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 610 ranges; 611 status = "disabled"; 612 613 usb1: usb@31100000 { 614 compatible = "snps,dwc3"; 615 reg = <0x00 0x31100000 0x00 0x50000>; 616 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 617 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 618 interrupt-names = "host", "peripheral"; 619 maximum-speed = "high-speed"; 620 dr_mode = "otg"; 621 }; 622 }; 623 624 fss: bus@fc00000 { 625 compatible = "simple-bus"; 626 reg = <0x00 0x0fc00000 0x00 0x70000>; 627 #address-cells = <2>; 628 #size-cells = <2>; 629 ranges; 630 631 ospi0: spi@fc40000 { 632 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 633 reg = <0x00 0x0fc40000 0x00 0x100>, 634 <0x05 0x00000000 0x01 0x00000000>; 635 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 636 cdns,fifo-depth = <256>; 637 cdns,fifo-width = <4>; 638 cdns,trigger-address = <0x0>; 639 clocks = <&k3_clks 75 7>; 640 assigned-clocks = <&k3_clks 75 7>; 641 assigned-clock-parents = <&k3_clks 75 8>; 642 assigned-clock-rates = <166666666>; 643 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 644 #address-cells = <1>; 645 #size-cells = <0>; 646 status = "disabled"; 647 }; 648 }; 649 650 cpsw3g: ethernet@8000000 { 651 compatible = "ti,am642-cpsw-nuss"; 652 #address-cells = <2>; 653 #size-cells = <2>; 654 reg = <0x00 0x08000000 0x00 0x200000>; 655 reg-names = "cpsw_nuss"; 656 ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>; 657 clocks = <&k3_clks 13 0>; 658 assigned-clocks = <&k3_clks 13 3>; 659 assigned-clock-parents = <&k3_clks 13 11>; 660 clock-names = "fck"; 661 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 662 663 dmas = <&main_pktdma 0xc600 15>, 664 <&main_pktdma 0xc601 15>, 665 <&main_pktdma 0xc602 15>, 666 <&main_pktdma 0xc603 15>, 667 <&main_pktdma 0xc604 15>, 668 <&main_pktdma 0xc605 15>, 669 <&main_pktdma 0xc606 15>, 670 <&main_pktdma 0xc607 15>, 671 <&main_pktdma 0x4600 15>; 672 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 673 "tx7", "rx"; 674 675 ethernet-ports { 676 #address-cells = <1>; 677 #size-cells = <0>; 678 679 cpsw_port1: port@1 { 680 reg = <1>; 681 ti,mac-only; 682 label = "port1"; 683 phys = <&phy_gmii_sel 1>; 684 mac-address = [00 00 00 00 00 00]; 685 ti,syscon-efuse = <&wkup_conf 0x200>; 686 }; 687 688 cpsw_port2: port@2 { 689 reg = <2>; 690 ti,mac-only; 691 label = "port2"; 692 phys = <&phy_gmii_sel 2>; 693 mac-address = [00 00 00 00 00 00]; 694 }; 695 }; 696 697 cpsw3g_mdio: mdio@f00 { 698 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 699 reg = <0x00 0xf00 0x00 0x100>; 700 #address-cells = <1>; 701 #size-cells = <0>; 702 clocks = <&k3_clks 13 0>; 703 clock-names = "fck"; 704 bus_freq = <1000000>; 705 status = "disabled"; 706 }; 707 708 cpts@3d000 { 709 compatible = "ti,j721e-cpts"; 710 reg = <0x00 0x3d000 0x00 0x400>; 711 clocks = <&k3_clks 13 3>; 712 clock-names = "cpts"; 713 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 714 interrupt-names = "cpts"; 715 ti,cpts-ext-ts-inputs = <4>; 716 ti,cpts-periodic-outputs = <2>; 717 }; 718 }; 719 720 hwspinlock: spinlock@2a000000 { 721 compatible = "ti,am64-hwspinlock"; 722 reg = <0x00 0x2a000000 0x00 0x1000>; 723 #hwlock-cells = <1>; 724 }; 725 726 mailbox0_cluster0: mailbox@29000000 { 727 compatible = "ti,am64-mailbox"; 728 reg = <0x00 0x29000000 0x00 0x200>; 729 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 731 #mbox-cells = <1>; 732 ti,mbox-num-users = <4>; 733 ti,mbox-num-fifos = <16>; 734 }; 735 736 ecap0: pwm@23100000 { 737 compatible = "ti,am3352-ecap"; 738 #pwm-cells = <3>; 739 reg = <0x00 0x23100000 0x00 0x100>; 740 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 741 clocks = <&k3_clks 51 0>; 742 clock-names = "fck"; 743 status = "disabled"; 744 }; 745 746 ecap1: pwm@23110000 { 747 compatible = "ti,am3352-ecap"; 748 #pwm-cells = <3>; 749 reg = <0x00 0x23110000 0x00 0x100>; 750 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 751 clocks = <&k3_clks 52 0>; 752 clock-names = "fck"; 753 status = "disabled"; 754 }; 755 756 ecap2: pwm@23120000 { 757 compatible = "ti,am3352-ecap"; 758 #pwm-cells = <3>; 759 reg = <0x00 0x23120000 0x00 0x100>; 760 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 761 clocks = <&k3_clks 53 0>; 762 clock-names = "fck"; 763 status = "disabled"; 764 }; 765 766 main_mcan0: can@20701000 { 767 compatible = "bosch,m_can"; 768 reg = <0x00 0x20701000 0x00 0x200>, 769 <0x00 0x20708000 0x00 0x8000>; 770 reg-names = "m_can", "message_ram"; 771 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 772 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; 773 clock-names = "hclk", "cclk"; 774 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 776 interrupt-names = "int0", "int1"; 777 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 778 status = "disabled"; 779 }; 780 781 main_rti0: watchdog@e000000 { 782 compatible = "ti,j7-rti-wdt"; 783 reg = <0x00 0x0e000000 0x00 0x100>; 784 clocks = <&k3_clks 125 0>; 785 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 786 assigned-clocks = <&k3_clks 125 0>; 787 assigned-clock-parents = <&k3_clks 125 2>; 788 }; 789 790 main_rti1: watchdog@e010000 { 791 compatible = "ti,j7-rti-wdt"; 792 reg = <0x00 0x0e010000 0x00 0x100>; 793 clocks = <&k3_clks 126 0>; 794 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; 795 assigned-clocks = <&k3_clks 126 0>; 796 assigned-clock-parents = <&k3_clks 126 2>; 797 }; 798 799 main_rti2: watchdog@e020000 { 800 compatible = "ti,j7-rti-wdt"; 801 reg = <0x00 0x0e020000 0x00 0x100>; 802 clocks = <&k3_clks 127 0>; 803 power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; 804 assigned-clocks = <&k3_clks 127 0>; 805 assigned-clock-parents = <&k3_clks 127 2>; 806 }; 807 808 main_rti3: watchdog@e030000 { 809 compatible = "ti,j7-rti-wdt"; 810 reg = <0x00 0x0e030000 0x00 0x100>; 811 clocks = <&k3_clks 128 0>; 812 power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; 813 assigned-clocks = <&k3_clks 128 0>; 814 assigned-clock-parents = <&k3_clks 128 2>; 815 }; 816 817 main_rti15: watchdog@e0f0000 { 818 compatible = "ti,j7-rti-wdt"; 819 reg = <0x00 0x0e0f0000 0x00 0x100>; 820 clocks = <&k3_clks 130 0>; 821 power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>; 822 assigned-clocks = <&k3_clks 130 0>; 823 assigned-clock-parents = <&k3_clks 130 2>; 824 }; 825 826 epwm0: pwm@23000000 { 827 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 828 #pwm-cells = <3>; 829 reg = <0x00 0x23000000 0x00 0x100>; 830 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 831 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 832 clock-names = "tbclk", "fck"; 833 status = "disabled"; 834 }; 835 836 epwm1: pwm@23010000 { 837 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 838 #pwm-cells = <3>; 839 reg = <0x00 0x23010000 0x00 0x100>; 840 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 841 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 842 clock-names = "tbclk", "fck"; 843 status = "disabled"; 844 }; 845 846 epwm2: pwm@23020000 { 847 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 848 #pwm-cells = <3>; 849 reg = <0x00 0x23020000 0x00 0x100>; 850 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 851 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 852 clock-names = "tbclk", "fck"; 853 status = "disabled"; 854 }; 855 856 mcasp0: audio-controller@2b00000 { 857 compatible = "ti,am33xx-mcasp-audio"; 858 reg = <0x00 0x02b00000 0x00 0x2000>, 859 <0x00 0x02b08000 0x00 0x400>; 860 reg-names = "mpu", "dat"; 861 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 863 interrupt-names = "tx", "rx"; 864 865 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>; 866 dma-names = "tx", "rx"; 867 868 clocks = <&k3_clks 190 0>; 869 clock-names = "fck"; 870 assigned-clocks = <&k3_clks 190 0>; 871 assigned-clock-parents = <&k3_clks 190 2>; 872 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 873 status = "disabled"; 874 }; 875 876 mcasp1: audio-controller@2b10000 { 877 compatible = "ti,am33xx-mcasp-audio"; 878 reg = <0x00 0x02b10000 0x00 0x2000>, 879 <0x00 0x02b18000 0x00 0x400>; 880 reg-names = "mpu", "dat"; 881 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 883 interrupt-names = "tx", "rx"; 884 885 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>; 886 dma-names = "tx", "rx"; 887 888 clocks = <&k3_clks 191 0>; 889 clock-names = "fck"; 890 assigned-clocks = <&k3_clks 191 0>; 891 assigned-clock-parents = <&k3_clks 191 2>; 892 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 893 status = "disabled"; 894 }; 895 896 mcasp2: audio-controller@2b20000 { 897 compatible = "ti,am33xx-mcasp-audio"; 898 reg = <0x00 0x02b20000 0x00 0x2000>, 899 <0x00 0x02b28000 0x00 0x400>; 900 reg-names = "mpu", "dat"; 901 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 903 interrupt-names = "tx", "rx"; 904 905 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>; 906 dma-names = "tx", "rx"; 907 908 clocks = <&k3_clks 192 0>; 909 clock-names = "fck"; 910 assigned-clocks = <&k3_clks 192 0>; 911 assigned-clock-parents = <&k3_clks 192 2>; 912 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 913 status = "disabled"; 914 }; 915}; 916