1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM642 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/phy/phy-cadence.h> 9#include <dt-bindings/phy/phy-ti.h> 10 11/ { 12 serdes_refclk: clock-cmnrefclk { 13 #clock-cells = <0>; 14 compatible = "fixed-clock"; 15 clock-frequency = <0>; 16 }; 17}; 18 19&cbass_main { 20 oc_sram: sram@70000000 { 21 compatible = "mmio-sram"; 22 reg = <0x00 0x70000000 0x00 0x200000>; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 ranges = <0x0 0x00 0x70000000 0x200000>; 26 27 tfa-sram@1c0000 { 28 reg = <0x1c0000 0x20000>; 29 }; 30 31 dmsc-sram@1e0000 { 32 reg = <0x1e0000 0x1c000>; 33 }; 34 35 sproxy-sram@1fc000 { 36 reg = <0x1fc000 0x4000>; 37 }; 38 }; 39 40 main_conf: syscon@43000000 { 41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 42 reg = <0x0 0x43000000 0x0 0x20000>; 43 #address-cells = <1>; 44 #size-cells = <1>; 45 ranges = <0x0 0x0 0x43000000 0x20000>; 46 47 chipid@14 { 48 compatible = "ti,am654-chipid"; 49 reg = <0x00000014 0x4>; 50 }; 51 52 serdes_ln_ctrl: mux-controller { 53 compatible = "mmio-mux"; 54 #mux-control-cells = <1>; 55 mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */ 56 }; 57 58 phy_gmii_sel: phy@4044 { 59 compatible = "ti,am654-phy-gmii-sel"; 60 reg = <0x4044 0x8>; 61 #phy-cells = <1>; 62 }; 63 64 epwm_tbclk: clock@4140 { 65 compatible = "ti,am64-epwm-tbclk"; 66 reg = <0x4130 0x4>; 67 #clock-cells = <1>; 68 }; 69 }; 70 71 gic500: interrupt-controller@1800000 { 72 compatible = "arm,gic-v3"; 73 #address-cells = <2>; 74 #size-cells = <2>; 75 ranges; 76 #interrupt-cells = <3>; 77 interrupt-controller; 78 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 79 <0x00 0x01840000 0x00 0xC0000>, /* GICR */ 80 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 81 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 82 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 83 /* 84 * vcpumntirq: 85 * virtual CPU interface maintenance interrupt 86 */ 87 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 88 89 gic_its: msi-controller@1820000 { 90 compatible = "arm,gic-v3-its"; 91 reg = <0x00 0x01820000 0x00 0x10000>; 92 socionext,synquacer-pre-its = <0x1000000 0x400000>; 93 msi-controller; 94 #msi-cells = <1>; 95 }; 96 }; 97 98 dmss: bus@48000000 { 99 compatible = "simple-mfd"; 100 #address-cells = <2>; 101 #size-cells = <2>; 102 dma-ranges; 103 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; 104 105 ti,sci-dev-id = <25>; 106 107 secure_proxy_main: mailbox@4d000000 { 108 compatible = "ti,am654-secure-proxy"; 109 #mbox-cells = <1>; 110 reg-names = "target_data", "rt", "scfg"; 111 reg = <0x00 0x4d000000 0x00 0x80000>, 112 <0x00 0x4a600000 0x00 0x80000>, 113 <0x00 0x4a400000 0x00 0x80000>; 114 interrupt-names = "rx_012"; 115 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 116 }; 117 118 inta_main_dmss: interrupt-controller@48000000 { 119 compatible = "ti,sci-inta"; 120 reg = <0x00 0x48000000 0x00 0x100000>; 121 #interrupt-cells = <0>; 122 interrupt-controller; 123 interrupt-parent = <&gic500>; 124 msi-controller; 125 ti,sci = <&dmsc>; 126 ti,sci-dev-id = <28>; 127 ti,interrupt-ranges = <4 68 36>; 128 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 129 }; 130 131 main_bcdma: dma-controller@485c0100 { 132 compatible = "ti,am64-dmss-bcdma"; 133 reg = <0x00 0x485c0100 0x00 0x100>, 134 <0x00 0x4c000000 0x00 0x20000>, 135 <0x00 0x4a820000 0x00 0x20000>, 136 <0x00 0x4aa40000 0x00 0x20000>, 137 <0x00 0x4bc00000 0x00 0x100000>; 138 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; 139 msi-parent = <&inta_main_dmss>; 140 #dma-cells = <3>; 141 142 ti,sci = <&dmsc>; 143 ti,sci-dev-id = <26>; 144 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 145 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 146 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 147 }; 148 149 main_pktdma: dma-controller@485c0000 { 150 compatible = "ti,am64-dmss-pktdma"; 151 reg = <0x00 0x485c0000 0x00 0x100>, 152 <0x00 0x4a800000 0x00 0x20000>, 153 <0x00 0x4aa00000 0x00 0x40000>, 154 <0x00 0x4b800000 0x00 0x400000>; 155 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 156 msi-parent = <&inta_main_dmss>; 157 #dma-cells = <2>; 158 159 ti,sci = <&dmsc>; 160 ti,sci-dev-id = <30>; 161 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 162 <0x24>, /* CPSW_TX_CHAN */ 163 <0x25>, /* SAUL_TX_0_CHAN */ 164 <0x26>, /* SAUL_TX_1_CHAN */ 165 <0x27>, /* ICSSG_0_TX_CHAN */ 166 <0x28>; /* ICSSG_1_TX_CHAN */ 167 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 168 <0x11>, /* RING_CPSW_TX_CHAN */ 169 <0x12>, /* RING_SAUL_TX_0_CHAN */ 170 <0x13>, /* RING_SAUL_TX_1_CHAN */ 171 <0x14>, /* RING_ICSSG_0_TX_CHAN */ 172 <0x15>; /* RING_ICSSG_1_TX_CHAN */ 173 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 174 <0x2b>, /* CPSW_RX_CHAN */ 175 <0x2d>, /* SAUL_RX_0_CHAN */ 176 <0x2f>, /* SAUL_RX_1_CHAN */ 177 <0x31>, /* SAUL_RX_2_CHAN */ 178 <0x33>, /* SAUL_RX_3_CHAN */ 179 <0x35>, /* ICSSG_0_RX_CHAN */ 180 <0x37>; /* ICSSG_1_RX_CHAN */ 181 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 182 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 183 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 184 <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */ 185 <0x36>, /* FLOW_ICSSG_0_RX_CHAN */ 186 <0x38>; /* FLOW_ICSSG_1_RX_CHAN */ 187 }; 188 }; 189 190 dmsc: system-controller@44043000 { 191 compatible = "ti,k2g-sci"; 192 ti,host-id = <12>; 193 mbox-names = "rx", "tx"; 194 mboxes = <&secure_proxy_main 12>, 195 <&secure_proxy_main 13>; 196 reg-names = "debug_messages"; 197 reg = <0x00 0x44043000 0x00 0xfe0>; 198 199 k3_pds: power-controller { 200 compatible = "ti,sci-pm-domain"; 201 #power-domain-cells = <2>; 202 }; 203 204 k3_clks: clock-controller { 205 compatible = "ti,k2g-sci-clk"; 206 #clock-cells = <2>; 207 }; 208 209 k3_reset: reset-controller { 210 compatible = "ti,sci-reset"; 211 #reset-cells = <2>; 212 }; 213 }; 214 215 main_pmx0: pinctrl@f4000 { 216 compatible = "pinctrl-single"; 217 reg = <0x00 0xf4000 0x00 0x2d0>; 218 #pinctrl-cells = <1>; 219 pinctrl-single,register-width = <32>; 220 pinctrl-single,function-mask = <0xffffffff>; 221 }; 222 223 main_timer0: timer@2400000 { 224 compatible = "ti,am654-timer"; 225 reg = <0x00 0x2400000 0x00 0x400>; 226 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&k3_clks 36 1>; 228 clock-names = "fck"; 229 assigned-clocks = <&k3_clks 36 1>; 230 assigned-clock-parents = <&k3_clks 36 2>; 231 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 232 ti,timer-pwm; 233 }; 234 235 main_timer1: timer@2410000 { 236 compatible = "ti,am654-timer"; 237 reg = <0x00 0x2410000 0x00 0x400>; 238 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&k3_clks 37 1>; 240 clock-names = "fck"; 241 assigned-clocks = <&k3_clks 37 1>; 242 assigned-clock-parents = <&k3_clks 37 2>; 243 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; 244 ti,timer-pwm; 245 }; 246 247 main_timer2: timer@2420000 { 248 compatible = "ti,am654-timer"; 249 reg = <0x00 0x2420000 0x00 0x400>; 250 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&k3_clks 38 1>; 252 clock-names = "fck"; 253 assigned-clocks = <&k3_clks 38 1>; 254 assigned-clock-parents = <&k3_clks 38 2>; 255 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 256 ti,timer-pwm; 257 }; 258 259 main_timer3: timer@2430000 { 260 compatible = "ti,am654-timer"; 261 reg = <0x00 0x2430000 0x00 0x400>; 262 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 263 clocks = <&k3_clks 39 1>; 264 clock-names = "fck"; 265 assigned-clocks = <&k3_clks 39 1>; 266 assigned-clock-parents = <&k3_clks 39 2>; 267 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 268 ti,timer-pwm; 269 }; 270 271 main_timer4: timer@2440000 { 272 compatible = "ti,am654-timer"; 273 reg = <0x00 0x2440000 0x00 0x400>; 274 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&k3_clks 40 1>; 276 clock-names = "fck"; 277 assigned-clocks = <&k3_clks 40 1>; 278 assigned-clock-parents = <&k3_clks 40 2>; 279 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 280 ti,timer-pwm; 281 }; 282 283 main_timer5: timer@2450000 { 284 compatible = "ti,am654-timer"; 285 reg = <0x00 0x2450000 0x00 0x400>; 286 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 287 clocks = <&k3_clks 41 1>; 288 clock-names = "fck"; 289 assigned-clocks = <&k3_clks 41 1>; 290 assigned-clock-parents = <&k3_clks 41 2>; 291 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 292 ti,timer-pwm; 293 }; 294 295 main_timer6: timer@2460000 { 296 compatible = "ti,am654-timer"; 297 reg = <0x00 0x2460000 0x00 0x400>; 298 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 299 clocks = <&k3_clks 42 1>; 300 clock-names = "fck"; 301 assigned-clocks = <&k3_clks 42 1>; 302 assigned-clock-parents = <&k3_clks 42 2>; 303 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 304 ti,timer-pwm; 305 }; 306 307 main_timer7: timer@2470000 { 308 compatible = "ti,am654-timer"; 309 reg = <0x00 0x2470000 0x00 0x400>; 310 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&k3_clks 43 1>; 312 clock-names = "fck"; 313 assigned-clocks = <&k3_clks 43 1>; 314 assigned-clock-parents = <&k3_clks 43 2>; 315 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 316 ti,timer-pwm; 317 }; 318 319 main_timer8: timer@2480000 { 320 compatible = "ti,am654-timer"; 321 reg = <0x00 0x2480000 0x00 0x400>; 322 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&k3_clks 44 1>; 324 clock-names = "fck"; 325 assigned-clocks = <&k3_clks 44 1>; 326 assigned-clock-parents = <&k3_clks 44 2>; 327 power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>; 328 ti,timer-pwm; 329 }; 330 331 main_timer9: timer@2490000 { 332 compatible = "ti,am654-timer"; 333 reg = <0x00 0x2490000 0x00 0x400>; 334 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 335 clocks = <&k3_clks 45 1>; 336 clock-names = "fck"; 337 assigned-clocks = <&k3_clks 45 1>; 338 assigned-clock-parents = <&k3_clks 45 2>; 339 power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>; 340 ti,timer-pwm; 341 }; 342 343 main_timer10: timer@24a0000 { 344 compatible = "ti,am654-timer"; 345 reg = <0x00 0x24a0000 0x00 0x400>; 346 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&k3_clks 46 1>; 348 clock-names = "fck"; 349 assigned-clocks = <&k3_clks 46 1>; 350 assigned-clock-parents = <&k3_clks 46 2>; 351 power-domains = <&k3_pds 46 TI_SCI_PD_EXCLUSIVE>; 352 ti,timer-pwm; 353 }; 354 355 main_timer11: timer@24b0000 { 356 compatible = "ti,am654-timer"; 357 reg = <0x00 0x24b0000 0x00 0x400>; 358 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&k3_clks 47 1>; 360 clock-names = "fck"; 361 assigned-clocks = <&k3_clks 47 1>; 362 assigned-clock-parents = <&k3_clks 47 2>; 363 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>; 364 ti,timer-pwm; 365 }; 366 367 main_esm: esm@420000 { 368 compatible = "ti,j721e-esm"; 369 reg = <0x00 0x420000 0x00 0x1000>; 370 ti,esm-pins = <160>, <161>; 371 }; 372 373 main_uart0: serial@2800000 { 374 compatible = "ti,am64-uart", "ti,am654-uart"; 375 reg = <0x00 0x02800000 0x00 0x100>; 376 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 377 clock-frequency = <48000000>; 378 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 379 clocks = <&k3_clks 146 0>; 380 clock-names = "fclk"; 381 status = "disabled"; 382 }; 383 384 main_uart1: serial@2810000 { 385 compatible = "ti,am64-uart", "ti,am654-uart"; 386 reg = <0x00 0x02810000 0x00 0x100>; 387 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 388 clock-frequency = <48000000>; 389 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 390 clocks = <&k3_clks 152 0>; 391 clock-names = "fclk"; 392 status = "disabled"; 393 }; 394 395 main_uart2: serial@2820000 { 396 compatible = "ti,am64-uart", "ti,am654-uart"; 397 reg = <0x00 0x02820000 0x00 0x100>; 398 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 399 clock-frequency = <48000000>; 400 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 401 clocks = <&k3_clks 153 0>; 402 clock-names = "fclk"; 403 status = "disabled"; 404 }; 405 406 main_uart3: serial@2830000 { 407 compatible = "ti,am64-uart", "ti,am654-uart"; 408 reg = <0x00 0x02830000 0x00 0x100>; 409 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 410 clock-frequency = <48000000>; 411 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 412 clocks = <&k3_clks 154 0>; 413 clock-names = "fclk"; 414 status = "disabled"; 415 }; 416 417 main_uart4: serial@2840000 { 418 compatible = "ti,am64-uart", "ti,am654-uart"; 419 reg = <0x00 0x02840000 0x00 0x100>; 420 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 421 clock-frequency = <48000000>; 422 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 423 clocks = <&k3_clks 155 0>; 424 clock-names = "fclk"; 425 status = "disabled"; 426 }; 427 428 main_uart5: serial@2850000 { 429 compatible = "ti,am64-uart", "ti,am654-uart"; 430 reg = <0x00 0x02850000 0x00 0x100>; 431 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 432 clock-frequency = <48000000>; 433 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 434 clocks = <&k3_clks 156 0>; 435 clock-names = "fclk"; 436 status = "disabled"; 437 }; 438 439 main_uart6: serial@2860000 { 440 compatible = "ti,am64-uart", "ti,am654-uart"; 441 reg = <0x00 0x02860000 0x00 0x100>; 442 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 443 clock-frequency = <48000000>; 444 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 445 clocks = <&k3_clks 158 0>; 446 clock-names = "fclk"; 447 status = "disabled"; 448 }; 449 450 main_i2c0: i2c@20000000 { 451 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 452 reg = <0x00 0x20000000 0x00 0x100>; 453 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 454 #address-cells = <1>; 455 #size-cells = <0>; 456 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 457 clocks = <&k3_clks 102 2>; 458 clock-names = "fck"; 459 status = "disabled"; 460 }; 461 462 main_i2c1: i2c@20010000 { 463 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 464 reg = <0x00 0x20010000 0x00 0x100>; 465 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 469 clocks = <&k3_clks 103 2>; 470 clock-names = "fck"; 471 status = "disabled"; 472 }; 473 474 main_i2c2: i2c@20020000 { 475 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 476 reg = <0x00 0x20020000 0x00 0x100>; 477 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 478 #address-cells = <1>; 479 #size-cells = <0>; 480 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 481 clocks = <&k3_clks 104 2>; 482 clock-names = "fck"; 483 status = "disabled"; 484 }; 485 486 main_i2c3: i2c@20030000 { 487 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 488 reg = <0x00 0x20030000 0x00 0x100>; 489 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 493 clocks = <&k3_clks 105 2>; 494 clock-names = "fck"; 495 status = "disabled"; 496 }; 497 498 main_spi0: spi@20100000 { 499 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 500 reg = <0x00 0x20100000 0x00 0x400>; 501 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 502 #address-cells = <1>; 503 #size-cells = <0>; 504 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 505 clocks = <&k3_clks 141 0>; 506 dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>; 507 dma-names = "tx0", "rx0"; 508 status = "disabled"; 509 }; 510 511 main_spi1: spi@20110000 { 512 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 513 reg = <0x00 0x20110000 0x00 0x400>; 514 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 515 #address-cells = <1>; 516 #size-cells = <0>; 517 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 518 clocks = <&k3_clks 142 0>; 519 status = "disabled"; 520 }; 521 522 main_spi2: spi@20120000 { 523 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 524 reg = <0x00 0x20120000 0x00 0x400>; 525 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 526 #address-cells = <1>; 527 #size-cells = <0>; 528 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 529 clocks = <&k3_clks 143 0>; 530 status = "disabled"; 531 }; 532 533 main_spi3: spi@20130000 { 534 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 535 reg = <0x00 0x20130000 0x00 0x400>; 536 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 537 #address-cells = <1>; 538 #size-cells = <0>; 539 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; 540 clocks = <&k3_clks 144 0>; 541 status = "disabled"; 542 }; 543 544 main_spi4: spi@20140000 { 545 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 546 reg = <0x00 0x20140000 0x00 0x400>; 547 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 548 #address-cells = <1>; 549 #size-cells = <0>; 550 power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>; 551 clocks = <&k3_clks 145 0>; 552 status = "disabled"; 553 }; 554 555 main_gpio_intr: interrupt-controller@a00000 { 556 compatible = "ti,sci-intr"; 557 reg = <0x00 0x00a00000 0x00 0x800>; 558 ti,intr-trigger-type = <1>; 559 interrupt-controller; 560 interrupt-parent = <&gic500>; 561 #interrupt-cells = <1>; 562 ti,sci = <&dmsc>; 563 ti,sci-dev-id = <3>; 564 ti,interrupt-ranges = <0 32 16>; 565 }; 566 567 main_gpio0: gpio@600000 { 568 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 569 reg = <0x0 0x00600000 0x0 0x100>; 570 gpio-controller; 571 #gpio-cells = <2>; 572 interrupt-parent = <&main_gpio_intr>; 573 interrupts = <190>, <191>, <192>, 574 <193>, <194>, <195>; 575 interrupt-controller; 576 #interrupt-cells = <2>; 577 ti,ngpio = <87>; 578 ti,davinci-gpio-unbanked = <0>; 579 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 580 clocks = <&k3_clks 77 0>; 581 clock-names = "gpio"; 582 }; 583 584 main_gpio1: gpio@601000 { 585 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 586 reg = <0x0 0x00601000 0x0 0x100>; 587 gpio-controller; 588 #gpio-cells = <2>; 589 interrupt-parent = <&main_gpio_intr>; 590 interrupts = <180>, <181>, <182>, 591 <183>, <184>, <185>; 592 interrupt-controller; 593 #interrupt-cells = <2>; 594 ti,ngpio = <88>; 595 ti,davinci-gpio-unbanked = <0>; 596 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 597 clocks = <&k3_clks 78 0>; 598 clock-names = "gpio"; 599 }; 600 601 sdhci0: mmc@fa10000 { 602 compatible = "ti,am64-sdhci-8bit"; 603 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; 604 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 605 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 606 clocks = <&k3_clks 57 0>, <&k3_clks 57 1>; 607 clock-names = "clk_ahb", "clk_xin"; 608 mmc-ddr-1_8v; 609 mmc-hs200-1_8v; 610 ti,trm-icp = <0x2>; 611 ti,otap-del-sel-legacy = <0x0>; 612 ti,otap-del-sel-mmc-hs = <0x0>; 613 ti,otap-del-sel-ddr52 = <0x6>; 614 ti,otap-del-sel-hs200 = <0x7>; 615 }; 616 617 sdhci1: mmc@fa00000 { 618 compatible = "ti,am64-sdhci-4bit"; 619 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; 620 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 621 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 622 clocks = <&k3_clks 58 3>, <&k3_clks 58 4>; 623 clock-names = "clk_ahb", "clk_xin"; 624 ti,trm-icp = <0x2>; 625 ti,otap-del-sel-legacy = <0x0>; 626 ti,otap-del-sel-sd-hs = <0xf>; 627 ti,otap-del-sel-sdr12 = <0xf>; 628 ti,otap-del-sel-sdr25 = <0xf>; 629 ti,otap-del-sel-sdr50 = <0xc>; 630 ti,otap-del-sel-sdr104 = <0x6>; 631 ti,otap-del-sel-ddr50 = <0x9>; 632 ti,clkbuf-sel = <0x7>; 633 }; 634 635 cpsw3g: ethernet@8000000 { 636 compatible = "ti,am642-cpsw-nuss"; 637 #address-cells = <2>; 638 #size-cells = <2>; 639 reg = <0x0 0x8000000 0x0 0x200000>; 640 reg-names = "cpsw_nuss"; 641 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>; 642 clocks = <&k3_clks 13 0>; 643 assigned-clocks = <&k3_clks 13 1>; 644 assigned-clock-parents = <&k3_clks 13 9>; 645 clock-names = "fck"; 646 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 647 648 dmas = <&main_pktdma 0xC500 15>, 649 <&main_pktdma 0xC501 15>, 650 <&main_pktdma 0xC502 15>, 651 <&main_pktdma 0xC503 15>, 652 <&main_pktdma 0xC504 15>, 653 <&main_pktdma 0xC505 15>, 654 <&main_pktdma 0xC506 15>, 655 <&main_pktdma 0xC507 15>, 656 <&main_pktdma 0x4500 15>; 657 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 658 "tx7", "rx"; 659 660 ethernet-ports { 661 #address-cells = <1>; 662 #size-cells = <0>; 663 664 cpsw_port1: port@1 { 665 reg = <1>; 666 ti,mac-only; 667 label = "port1"; 668 phys = <&phy_gmii_sel 1>; 669 mac-address = [00 00 00 00 00 00]; 670 ti,syscon-efuse = <&main_conf 0x200>; 671 }; 672 673 cpsw_port2: port@2 { 674 reg = <2>; 675 ti,mac-only; 676 label = "port2"; 677 phys = <&phy_gmii_sel 2>; 678 mac-address = [00 00 00 00 00 00]; 679 }; 680 }; 681 682 cpsw3g_mdio: mdio@f00 { 683 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 684 reg = <0x0 0xf00 0x0 0x100>; 685 #address-cells = <1>; 686 #size-cells = <0>; 687 clocks = <&k3_clks 13 0>; 688 clock-names = "fck"; 689 bus_freq = <1000000>; 690 status = "disabled"; 691 }; 692 693 cpts@3d000 { 694 compatible = "ti,j721e-cpts"; 695 reg = <0x0 0x3d000 0x0 0x400>; 696 clocks = <&k3_clks 13 1>; 697 clock-names = "cpts"; 698 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 699 interrupt-names = "cpts"; 700 ti,cpts-ext-ts-inputs = <4>; 701 ti,cpts-periodic-outputs = <2>; 702 }; 703 }; 704 705 main_cpts0: cpts@39000000 { 706 compatible = "ti,j721e-cpts"; 707 reg = <0x0 0x39000000 0x0 0x400>; 708 reg-names = "cpts"; 709 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; 710 clocks = <&k3_clks 84 0>; 711 clock-names = "cpts"; 712 assigned-clocks = <&k3_clks 84 0>; 713 assigned-clock-parents = <&k3_clks 84 8>; 714 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 715 interrupt-names = "cpts"; 716 ti,cpts-periodic-outputs = <6>; 717 ti,cpts-ext-ts-inputs = <8>; 718 }; 719 720 timesync_router: pinctrl@a40000 { 721 compatible = "pinctrl-single"; 722 reg = <0x0 0xa40000 0x0 0x800>; 723 #pinctrl-cells = <1>; 724 pinctrl-single,register-width = <32>; 725 pinctrl-single,function-mask = <0x000107ff>; 726 }; 727 728 usbss0: cdns-usb@f900000 { 729 compatible = "ti,am64-usb"; 730 reg = <0x00 0xf900000 0x00 0x100>; 731 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 732 clocks = <&k3_clks 161 9>, <&k3_clks 161 1>; 733 clock-names = "ref", "lpm"; 734 assigned-clocks = <&k3_clks 161 9>; /* USB2_REFCLK */ 735 assigned-clock-parents = <&k3_clks 161 10>; /* HF0SC0 */ 736 #address-cells = <2>; 737 #size-cells = <2>; 738 ranges; 739 usb0: usb@f400000 { 740 compatible = "cdns,usb3"; 741 reg = <0x00 0xf400000 0x00 0x10000>, 742 <0x00 0xf410000 0x00 0x10000>, 743 <0x00 0xf420000 0x00 0x10000>; 744 reg-names = "otg", 745 "xhci", 746 "dev"; 747 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 748 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 749 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */ 750 interrupt-names = "host", 751 "peripheral", 752 "otg"; 753 maximum-speed = "super-speed"; 754 dr_mode = "otg"; 755 }; 756 }; 757 758 tscadc0: tscadc@28001000 { 759 compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; 760 reg = <0x00 0x28001000 0x00 0x1000>; 761 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 762 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 763 clocks = <&k3_clks 0 0>; 764 assigned-clocks = <&k3_clks 0 0>; 765 assigned-clock-parents = <&k3_clks 0 3>; 766 assigned-clock-rates = <60000000>; 767 clock-names = "fck"; 768 769 adc { 770 #io-channel-cells = <1>; 771 compatible = "ti,am654-adc", "ti,am3359-adc"; 772 }; 773 }; 774 775 fss: bus@fc00000 { 776 compatible = "simple-bus"; 777 reg = <0x00 0x0fc00000 0x00 0x70000>; 778 #address-cells = <2>; 779 #size-cells = <2>; 780 ranges; 781 782 ospi0: spi@fc40000 { 783 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 784 reg = <0x00 0x0fc40000 0x00 0x100>, 785 <0x05 0x00000000 0x01 0x00000000>; 786 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 787 cdns,fifo-depth = <256>; 788 cdns,fifo-width = <4>; 789 cdns,trigger-address = <0x0>; 790 #address-cells = <0x1>; 791 #size-cells = <0x0>; 792 clocks = <&k3_clks 75 6>; 793 assigned-clocks = <&k3_clks 75 6>; 794 assigned-clock-parents = <&k3_clks 75 7>; 795 assigned-clock-rates = <166666666>; 796 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 797 }; 798 }; 799 800 hwspinlock: spinlock@2a000000 { 801 compatible = "ti,am64-hwspinlock"; 802 reg = <0x00 0x2a000000 0x00 0x1000>; 803 #hwlock-cells = <1>; 804 }; 805 806 mailbox0_cluster2: mailbox@29020000 { 807 compatible = "ti,am64-mailbox"; 808 reg = <0x00 0x29020000 0x00 0x200>; 809 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 810 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 811 #mbox-cells = <1>; 812 ti,mbox-num-users = <4>; 813 ti,mbox-num-fifos = <16>; 814 status = "disabled"; 815 }; 816 817 mailbox0_cluster3: mailbox@29030000 { 818 compatible = "ti,am64-mailbox"; 819 reg = <0x00 0x29030000 0x00 0x200>; 820 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 821 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 822 #mbox-cells = <1>; 823 ti,mbox-num-users = <4>; 824 ti,mbox-num-fifos = <16>; 825 status = "disabled"; 826 }; 827 828 mailbox0_cluster4: mailbox@29040000 { 829 compatible = "ti,am64-mailbox"; 830 reg = <0x00 0x29040000 0x00 0x200>; 831 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 833 #mbox-cells = <1>; 834 ti,mbox-num-users = <4>; 835 ti,mbox-num-fifos = <16>; 836 status = "disabled"; 837 }; 838 839 mailbox0_cluster5: mailbox@29050000 { 840 compatible = "ti,am64-mailbox"; 841 reg = <0x00 0x29050000 0x00 0x200>; 842 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 843 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 844 #mbox-cells = <1>; 845 ti,mbox-num-users = <4>; 846 ti,mbox-num-fifos = <16>; 847 status = "disabled"; 848 }; 849 850 mailbox0_cluster6: mailbox@29060000 { 851 compatible = "ti,am64-mailbox"; 852 reg = <0x00 0x29060000 0x00 0x200>; 853 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 854 #mbox-cells = <1>; 855 ti,mbox-num-users = <4>; 856 ti,mbox-num-fifos = <16>; 857 status = "disabled"; 858 }; 859 860 mailbox0_cluster7: mailbox@29070000 { 861 compatible = "ti,am64-mailbox"; 862 reg = <0x00 0x29070000 0x00 0x200>; 863 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 864 #mbox-cells = <1>; 865 ti,mbox-num-users = <4>; 866 ti,mbox-num-fifos = <16>; 867 status = "disabled"; 868 }; 869 870 main_r5fss0: r5fss@78000000 { 871 compatible = "ti,am64-r5fss"; 872 ti,cluster-mode = <0>; 873 #address-cells = <1>; 874 #size-cells = <1>; 875 ranges = <0x78000000 0x00 0x78000000 0x10000>, 876 <0x78100000 0x00 0x78100000 0x10000>, 877 <0x78200000 0x00 0x78200000 0x08000>, 878 <0x78300000 0x00 0x78300000 0x08000>; 879 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; 880 881 main_r5fss0_core0: r5f@78000000 { 882 compatible = "ti,am64-r5f"; 883 reg = <0x78000000 0x00010000>, 884 <0x78100000 0x00010000>; 885 reg-names = "atcm", "btcm"; 886 ti,sci = <&dmsc>; 887 ti,sci-dev-id = <121>; 888 ti,sci-proc-ids = <0x01 0xff>; 889 resets = <&k3_reset 121 1>; 890 firmware-name = "am64-main-r5f0_0-fw"; 891 ti,atcm-enable = <1>; 892 ti,btcm-enable = <1>; 893 ti,loczrama = <1>; 894 }; 895 896 main_r5fss0_core1: r5f@78200000 { 897 compatible = "ti,am64-r5f"; 898 reg = <0x78200000 0x00008000>, 899 <0x78300000 0x00008000>; 900 reg-names = "atcm", "btcm"; 901 ti,sci = <&dmsc>; 902 ti,sci-dev-id = <122>; 903 ti,sci-proc-ids = <0x02 0xff>; 904 resets = <&k3_reset 122 1>; 905 firmware-name = "am64-main-r5f0_1-fw"; 906 ti,atcm-enable = <1>; 907 ti,btcm-enable = <1>; 908 ti,loczrama = <1>; 909 }; 910 }; 911 912 main_r5fss1: r5fss@78400000 { 913 compatible = "ti,am64-r5fss"; 914 ti,cluster-mode = <0>; 915 #address-cells = <1>; 916 #size-cells = <1>; 917 ranges = <0x78400000 0x00 0x78400000 0x10000>, 918 <0x78500000 0x00 0x78500000 0x10000>, 919 <0x78600000 0x00 0x78600000 0x08000>, 920 <0x78700000 0x00 0x78700000 0x08000>; 921 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 922 923 main_r5fss1_core0: r5f@78400000 { 924 compatible = "ti,am64-r5f"; 925 reg = <0x78400000 0x00010000>, 926 <0x78500000 0x00010000>; 927 reg-names = "atcm", "btcm"; 928 ti,sci = <&dmsc>; 929 ti,sci-dev-id = <123>; 930 ti,sci-proc-ids = <0x06 0xff>; 931 resets = <&k3_reset 123 1>; 932 firmware-name = "am64-main-r5f1_0-fw"; 933 ti,atcm-enable = <1>; 934 ti,btcm-enable = <1>; 935 ti,loczrama = <1>; 936 }; 937 938 main_r5fss1_core1: r5f@78600000 { 939 compatible = "ti,am64-r5f"; 940 reg = <0x78600000 0x00008000>, 941 <0x78700000 0x00008000>; 942 reg-names = "atcm", "btcm"; 943 ti,sci = <&dmsc>; 944 ti,sci-dev-id = <124>; 945 ti,sci-proc-ids = <0x07 0xff>; 946 resets = <&k3_reset 124 1>; 947 firmware-name = "am64-main-r5f1_1-fw"; 948 ti,atcm-enable = <1>; 949 ti,btcm-enable = <1>; 950 ti,loczrama = <1>; 951 }; 952 }; 953 954 serdes_wiz0: wiz@f000000 { 955 compatible = "ti,am64-wiz-10g"; 956 #address-cells = <1>; 957 #size-cells = <1>; 958 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 959 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>; 960 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 961 num-lanes = <1>; 962 #reset-cells = <1>; 963 #clock-cells = <1>; 964 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; 965 966 assigned-clocks = <&k3_clks 162 1>; 967 assigned-clock-parents = <&k3_clks 162 5>; 968 969 serdes0: serdes@f000000 { 970 compatible = "ti,j721e-serdes-10g"; 971 reg = <0x0f000000 0x00010000>; 972 reg-names = "torrent_phy"; 973 resets = <&serdes_wiz0 0>; 974 reset-names = "torrent_reset"; 975 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 976 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; 977 clock-names = "refclk", "phy_en_refclk"; 978 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 979 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, 980 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; 981 assigned-clock-parents = <&k3_clks 162 1>, 982 <&k3_clks 162 1>, 983 <&k3_clks 162 1>; 984 #address-cells = <1>; 985 #size-cells = <0>; 986 #clock-cells = <1>; 987 }; 988 }; 989 990 pcie0_rc: pcie@f102000 { 991 compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host"; 992 reg = <0x00 0x0f102000 0x00 0x1000>, 993 <0x00 0x0f100000 0x00 0x400>, 994 <0x00 0x0d000000 0x00 0x00800000>, 995 <0x00 0x68000000 0x00 0x00001000>; 996 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 997 interrupt-names = "link_state"; 998 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 999 device_type = "pci"; 1000 ti,syscon-pcie-ctrl = <&main_conf 0x4070>; 1001 max-link-speed = <2>; 1002 num-lanes = <1>; 1003 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 1004 clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; 1005 clock-names = "fck", "pcie_refclk"; 1006 #address-cells = <3>; 1007 #size-cells = <2>; 1008 bus-range = <0x0 0xff>; 1009 cdns,no-bar-match-nbits = <64>; 1010 vendor-id = <0x104c>; 1011 device-id = <0xb010>; 1012 msi-map = <0x0 &gic_its 0x0 0x10000>; 1013 ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, 1014 <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; 1015 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>; 1016 status = "disabled"; 1017 }; 1018 1019 pcie0_ep: pcie-ep@f102000 { 1020 compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep"; 1021 reg = <0x00 0x0f102000 0x00 0x1000>, 1022 <0x00 0x0f100000 0x00 0x400>, 1023 <0x00 0x0d000000 0x00 0x00800000>, 1024 <0x00 0x68000000 0x00 0x08000000>; 1025 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 1026 interrupt-names = "link_state"; 1027 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 1028 ti,syscon-pcie-ctrl = <&main_conf 0x4070>; 1029 max-link-speed = <2>; 1030 num-lanes = <1>; 1031 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 1032 clocks = <&k3_clks 114 0>; 1033 clock-names = "fck"; 1034 max-functions = /bits/ 8 <1>; 1035 status = "disabled"; 1036 }; 1037 1038 epwm0: pwm@23000000 { 1039 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1040 #pwm-cells = <3>; 1041 reg = <0x0 0x23000000 0x0 0x100>; 1042 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 1043 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 1044 clock-names = "tbclk", "fck"; 1045 status = "disabled"; 1046 }; 1047 1048 epwm1: pwm@23010000 { 1049 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1050 #pwm-cells = <3>; 1051 reg = <0x0 0x23010000 0x0 0x100>; 1052 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 1053 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 1054 clock-names = "tbclk", "fck"; 1055 status = "disabled"; 1056 }; 1057 1058 epwm2: pwm@23020000 { 1059 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1060 #pwm-cells = <3>; 1061 reg = <0x0 0x23020000 0x0 0x100>; 1062 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 1063 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 1064 clock-names = "tbclk", "fck"; 1065 status = "disabled"; 1066 }; 1067 1068 epwm3: pwm@23030000 { 1069 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1070 #pwm-cells = <3>; 1071 reg = <0x0 0x23030000 0x0 0x100>; 1072 power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; 1073 clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>; 1074 clock-names = "tbclk", "fck"; 1075 status = "disabled"; 1076 }; 1077 1078 epwm4: pwm@23040000 { 1079 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1080 #pwm-cells = <3>; 1081 reg = <0x0 0x23040000 0x0 0x100>; 1082 power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; 1083 clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>; 1084 clock-names = "tbclk", "fck"; 1085 status = "disabled"; 1086 }; 1087 1088 epwm5: pwm@23050000 { 1089 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1090 #pwm-cells = <3>; 1091 reg = <0x0 0x23050000 0x0 0x100>; 1092 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 1093 clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>; 1094 clock-names = "tbclk", "fck"; 1095 status = "disabled"; 1096 }; 1097 1098 epwm6: pwm@23060000 { 1099 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1100 #pwm-cells = <3>; 1101 reg = <0x0 0x23060000 0x0 0x100>; 1102 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 1103 clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>; 1104 clock-names = "tbclk", "fck"; 1105 status = "disabled"; 1106 }; 1107 1108 epwm7: pwm@23070000 { 1109 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1110 #pwm-cells = <3>; 1111 reg = <0x0 0x23070000 0x0 0x100>; 1112 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 1113 clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>; 1114 clock-names = "tbclk", "fck"; 1115 status = "disabled"; 1116 }; 1117 1118 epwm8: pwm@23080000 { 1119 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1120 #pwm-cells = <3>; 1121 reg = <0x0 0x23080000 0x0 0x100>; 1122 power-domains = <&k3_pds 94 TI_SCI_PD_EXCLUSIVE>; 1123 clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>; 1124 clock-names = "tbclk", "fck"; 1125 status = "disabled"; 1126 }; 1127 1128 ecap0: pwm@23100000 { 1129 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 1130 #pwm-cells = <3>; 1131 reg = <0x0 0x23100000 0x0 0x60>; 1132 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 1133 clocks = <&k3_clks 51 0>; 1134 clock-names = "fck"; 1135 status = "disabled"; 1136 }; 1137 1138 ecap1: pwm@23110000 { 1139 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 1140 #pwm-cells = <3>; 1141 reg = <0x0 0x23110000 0x0 0x60>; 1142 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 1143 clocks = <&k3_clks 52 0>; 1144 clock-names = "fck"; 1145 status = "disabled"; 1146 }; 1147 1148 ecap2: pwm@23120000 { 1149 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 1150 #pwm-cells = <3>; 1151 reg = <0x0 0x23120000 0x0 0x60>; 1152 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 1153 clocks = <&k3_clks 53 0>; 1154 clock-names = "fck"; 1155 status = "disabled"; 1156 }; 1157 1158 main_rti0: watchdog@e000000 { 1159 compatible = "ti,j7-rti-wdt"; 1160 reg = <0x00 0xe000000 0x00 0x100>; 1161 clocks = <&k3_clks 125 0>; 1162 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 1163 assigned-clocks = <&k3_clks 125 0>; 1164 assigned-clock-parents = <&k3_clks 125 2>; 1165 }; 1166 1167 main_rti1: watchdog@e010000 { 1168 compatible = "ti,j7-rti-wdt"; 1169 reg = <0x00 0xe010000 0x00 0x100>; 1170 clocks = <&k3_clks 126 0>; 1171 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; 1172 assigned-clocks = <&k3_clks 126 0>; 1173 assigned-clock-parents = <&k3_clks 126 2>; 1174 }; 1175 1176 icssg0: icssg@30000000 { 1177 compatible = "ti,am642-icssg"; 1178 reg = <0x00 0x30000000 0x00 0x80000>; 1179 power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; 1180 #address-cells = <1>; 1181 #size-cells = <1>; 1182 ranges = <0x0 0x00 0x30000000 0x80000>; 1183 1184 icssg0_mem: memories@0 { 1185 reg = <0x0 0x2000>, 1186 <0x2000 0x2000>, 1187 <0x10000 0x10000>; 1188 reg-names = "dram0", "dram1", "shrdram2"; 1189 }; 1190 1191 icssg0_cfg: cfg@26000 { 1192 compatible = "ti,pruss-cfg", "syscon"; 1193 reg = <0x26000 0x200>; 1194 #address-cells = <1>; 1195 #size-cells = <1>; 1196 ranges = <0x0 0x26000 0x2000>; 1197 1198 clocks { 1199 #address-cells = <1>; 1200 #size-cells = <0>; 1201 1202 icssg0_coreclk_mux: coreclk-mux@3c { 1203 reg = <0x3c>; 1204 #clock-cells = <0>; 1205 clocks = <&k3_clks 81 0>, /* icssg0_core_clk */ 1206 <&k3_clks 81 20>; /* icssg0_iclk */ 1207 assigned-clocks = <&icssg0_coreclk_mux>; 1208 assigned-clock-parents = <&k3_clks 81 20>; 1209 }; 1210 1211 icssg0_iepclk_mux: iepclk-mux@30 { 1212 reg = <0x30>; 1213 #clock-cells = <0>; 1214 clocks = <&k3_clks 81 3>, /* icssg0_iep_clk */ 1215 <&icssg0_coreclk_mux>; /* icssg0_coreclk_mux */ 1216 assigned-clocks = <&icssg0_iepclk_mux>; 1217 assigned-clock-parents = <&icssg0_coreclk_mux>; 1218 }; 1219 }; 1220 }; 1221 1222 icssg0_mii_rt: mii-rt@32000 { 1223 compatible = "ti,pruss-mii", "syscon"; 1224 reg = <0x32000 0x100>; 1225 }; 1226 1227 icssg0_mii_g_rt: mii-g-rt@33000 { 1228 compatible = "ti,pruss-mii-g", "syscon"; 1229 reg = <0x33000 0x1000>; 1230 }; 1231 1232 icssg0_intc: interrupt-controller@20000 { 1233 compatible = "ti,icssg-intc"; 1234 reg = <0x20000 0x2000>; 1235 interrupt-controller; 1236 #interrupt-cells = <3>; 1237 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1245 interrupt-names = "host_intr0", "host_intr1", 1246 "host_intr2", "host_intr3", 1247 "host_intr4", "host_intr5", 1248 "host_intr6", "host_intr7"; 1249 }; 1250 1251 pru0_0: pru@34000 { 1252 compatible = "ti,am642-pru"; 1253 reg = <0x34000 0x3000>, 1254 <0x22000 0x100>, 1255 <0x22400 0x100>; 1256 reg-names = "iram", "control", "debug"; 1257 firmware-name = "am64x-pru0_0-fw"; 1258 }; 1259 1260 rtu0_0: rtu@4000 { 1261 compatible = "ti,am642-rtu"; 1262 reg = <0x4000 0x2000>, 1263 <0x23000 0x100>, 1264 <0x23400 0x100>; 1265 reg-names = "iram", "control", "debug"; 1266 firmware-name = "am64x-rtu0_0-fw"; 1267 }; 1268 1269 tx_pru0_0: txpru@a000 { 1270 compatible = "ti,am642-tx-pru"; 1271 reg = <0xa000 0x1800>, 1272 <0x25000 0x100>, 1273 <0x25400 0x100>; 1274 reg-names = "iram", "control", "debug"; 1275 firmware-name = "am64x-txpru0_0-fw"; 1276 }; 1277 1278 pru0_1: pru@38000 { 1279 compatible = "ti,am642-pru"; 1280 reg = <0x38000 0x3000>, 1281 <0x24000 0x100>, 1282 <0x24400 0x100>; 1283 reg-names = "iram", "control", "debug"; 1284 firmware-name = "am64x-pru0_1-fw"; 1285 }; 1286 1287 rtu0_1: rtu@6000 { 1288 compatible = "ti,am642-rtu"; 1289 reg = <0x6000 0x2000>, 1290 <0x23800 0x100>, 1291 <0x23c00 0x100>; 1292 reg-names = "iram", "control", "debug"; 1293 firmware-name = "am64x-rtu0_1-fw"; 1294 }; 1295 1296 tx_pru0_1: txpru@c000 { 1297 compatible = "ti,am642-tx-pru"; 1298 reg = <0xc000 0x1800>, 1299 <0x25800 0x100>, 1300 <0x25c00 0x100>; 1301 reg-names = "iram", "control", "debug"; 1302 firmware-name = "am64x-txpru0_1-fw"; 1303 }; 1304 1305 icssg0_mdio: mdio@32400 { 1306 compatible = "ti,davinci_mdio"; 1307 reg = <0x32400 0x100>; 1308 clocks = <&k3_clks 62 3>; 1309 clock-names = "fck"; 1310 #address-cells = <1>; 1311 #size-cells = <0>; 1312 bus_freq = <1000000>; 1313 status = "disabled"; 1314 }; 1315 }; 1316 1317 icssg1: icssg@30080000 { 1318 compatible = "ti,am642-icssg"; 1319 reg = <0x00 0x30080000 0x00 0x80000>; 1320 power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>; 1321 #address-cells = <1>; 1322 #size-cells = <1>; 1323 ranges = <0x0 0x00 0x30080000 0x80000>; 1324 1325 icssg1_mem: memories@0 { 1326 reg = <0x0 0x2000>, 1327 <0x2000 0x2000>, 1328 <0x10000 0x10000>; 1329 reg-names = "dram0", "dram1", "shrdram2"; 1330 }; 1331 1332 icssg1_cfg: cfg@26000 { 1333 compatible = "ti,pruss-cfg", "syscon"; 1334 reg = <0x26000 0x200>; 1335 #address-cells = <1>; 1336 #size-cells = <1>; 1337 ranges = <0x0 0x26000 0x2000>; 1338 1339 clocks { 1340 #address-cells = <1>; 1341 #size-cells = <0>; 1342 1343 icssg1_coreclk_mux: coreclk-mux@3c { 1344 reg = <0x3c>; 1345 #clock-cells = <0>; 1346 clocks = <&k3_clks 82 0>, /* icssg1_core_clk */ 1347 <&k3_clks 82 20>; /* icssg1_iclk */ 1348 assigned-clocks = <&icssg1_coreclk_mux>; 1349 assigned-clock-parents = <&k3_clks 82 20>; 1350 }; 1351 1352 icssg1_iepclk_mux: iepclk-mux@30 { 1353 reg = <0x30>; 1354 #clock-cells = <0>; 1355 clocks = <&k3_clks 82 3>, /* icssg1_iep_clk */ 1356 <&icssg1_coreclk_mux>; /* icssg1_coreclk_mux */ 1357 assigned-clocks = <&icssg1_iepclk_mux>; 1358 assigned-clock-parents = <&icssg1_coreclk_mux>; 1359 }; 1360 }; 1361 }; 1362 1363 icssg1_mii_rt: mii-rt@32000 { 1364 compatible = "ti,pruss-mii", "syscon"; 1365 reg = <0x32000 0x100>; 1366 }; 1367 1368 icssg1_mii_g_rt: mii-g-rt@33000 { 1369 compatible = "ti,pruss-mii-g", "syscon"; 1370 reg = <0x33000 0x1000>; 1371 }; 1372 1373 icssg1_intc: interrupt-controller@20000 { 1374 compatible = "ti,icssg-intc"; 1375 reg = <0x20000 0x2000>; 1376 interrupt-controller; 1377 #interrupt-cells = <3>; 1378 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 1384 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 1385 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1386 interrupt-names = "host_intr0", "host_intr1", 1387 "host_intr2", "host_intr3", 1388 "host_intr4", "host_intr5", 1389 "host_intr6", "host_intr7"; 1390 }; 1391 1392 pru1_0: pru@34000 { 1393 compatible = "ti,am642-pru"; 1394 reg = <0x34000 0x4000>, 1395 <0x22000 0x100>, 1396 <0x22400 0x100>; 1397 reg-names = "iram", "control", "debug"; 1398 firmware-name = "am64x-pru1_0-fw"; 1399 }; 1400 1401 rtu1_0: rtu@4000 { 1402 compatible = "ti,am642-rtu"; 1403 reg = <0x4000 0x2000>, 1404 <0x23000 0x100>, 1405 <0x23400 0x100>; 1406 reg-names = "iram", "control", "debug"; 1407 firmware-name = "am64x-rtu1_0-fw"; 1408 }; 1409 1410 tx_pru1_0: txpru@a000 { 1411 compatible = "ti,am642-tx-pru"; 1412 reg = <0xa000 0x1800>, 1413 <0x25000 0x100>, 1414 <0x25400 0x100>; 1415 reg-names = "iram", "control", "debug"; 1416 firmware-name = "am64x-txpru1_0-fw"; 1417 }; 1418 1419 pru1_1: pru@38000 { 1420 compatible = "ti,am642-pru"; 1421 reg = <0x38000 0x4000>, 1422 <0x24000 0x100>, 1423 <0x24400 0x100>; 1424 reg-names = "iram", "control", "debug"; 1425 firmware-name = "am64x-pru1_1-fw"; 1426 }; 1427 1428 rtu1_1: rtu@6000 { 1429 compatible = "ti,am642-rtu"; 1430 reg = <0x6000 0x2000>, 1431 <0x23800 0x100>, 1432 <0x23c00 0x100>; 1433 reg-names = "iram", "control", "debug"; 1434 firmware-name = "am64x-rtu1_1-fw"; 1435 }; 1436 1437 tx_pru1_1: txpru@c000 { 1438 compatible = "ti,am642-tx-pru"; 1439 reg = <0xc000 0x1800>, 1440 <0x25800 0x100>, 1441 <0x25c00 0x100>; 1442 reg-names = "iram", "control", "debug"; 1443 firmware-name = "am64x-txpru1_1-fw"; 1444 }; 1445 1446 icssg1_mdio: mdio@32400 { 1447 compatible = "ti,davinci_mdio"; 1448 reg = <0x32400 0x100>; 1449 #address-cells = <1>; 1450 #size-cells = <0>; 1451 clocks = <&k3_clks 82 0>; 1452 clock-names = "fck"; 1453 bus_freq = <1000000>; 1454 status = "disabled"; 1455 }; 1456 }; 1457 1458 main_mcan0: can@20701000 { 1459 compatible = "bosch,m_can"; 1460 reg = <0x00 0x20701000 0x00 0x200>, 1461 <0x00 0x20708000 0x00 0x8000>; 1462 reg-names = "m_can", "message_ram"; 1463 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 1464 clocks = <&k3_clks 98 5>, <&k3_clks 98 0>; 1465 clock-names = "hclk", "cclk"; 1466 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1468 interrupt-names = "int0", "int1"; 1469 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1470 status = "disabled"; 1471 }; 1472 1473 main_mcan1: can@20711000 { 1474 compatible = "bosch,m_can"; 1475 reg = <0x00 0x20711000 0x00 0x200>, 1476 <0x00 0x20718000 0x00 0x8000>; 1477 reg-names = "m_can", "message_ram"; 1478 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 1479 clocks = <&k3_clks 99 5>, <&k3_clks 99 0>; 1480 clock-names = "hclk", "cclk"; 1481 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1483 interrupt-names = "int0", "int1"; 1484 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1485 status = "disabled"; 1486 }; 1487 1488 crypto: crypto@40900000 { 1489 compatible = "ti,am64-sa2ul"; 1490 reg = <0x00 0x40900000 0x00 0x1200>; 1491 power-domains = <&k3_pds 133 TI_SCI_PD_SHARED>; 1492 #address-cells = <2>; 1493 #size-cells = <2>; 1494 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; 1495 dmas = <&main_pktdma 0xc001 0>, <&main_pktdma 0x4002 0>, 1496 <&main_pktdma 0x4003 0>; 1497 dma-names = "tx", "rx1", "rx2"; 1498 1499 rng: rng@40910000 { 1500 compatible = "inside-secure,safexcel-eip76"; 1501 reg = <0x00 0x40910000 0x00 0x7d>; 1502 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1503 status = "disabled"; /* Used by OP-TEE */ 1504 }; 1505 }; 1506 1507 gpmc0: memory-controller@3b000000 { 1508 compatible = "ti,am64-gpmc"; 1509 power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; 1510 clocks = <&k3_clks 80 0>; 1511 clock-names = "fck"; 1512 reg = <0x00 0x3b000000 0x00 0x400>, 1513 <0x00 0x50000000 0x00 0x8000000>; 1514 reg-names = "cfg", "data"; 1515 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1516 gpmc,num-cs = <3>; 1517 gpmc,num-waitpins = <2>; 1518 #address-cells = <2>; 1519 #size-cells = <1>; 1520 interrupt-controller; 1521 #interrupt-cells = <2>; 1522 gpio-controller; 1523 #gpio-cells = <2>; 1524 status = "disabled"; 1525 }; 1526 1527 elm0: ecc@25010000 { 1528 compatible = "ti,am64-elm"; 1529 reg = <0x00 0x25010000 0x00 0x2000>; 1530 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 1531 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; 1532 clocks = <&k3_clks 54 0>; 1533 clock-names = "fck"; 1534 status = "disabled"; 1535 }; 1536 1537 main_vtm0: temperature-sensor@b00000 { 1538 compatible = "ti,j7200-vtm"; 1539 reg = <0x00 0xb00000 0x00 0x400>, 1540 <0x00 0xb01000 0x00 0x400>; 1541 power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>; 1542 #thermal-sensor-cells = <1>; 1543 }; 1544}; 1545