#
b066a310 |
| 06-Dec-2018 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Add HDA controller on Tegra186
The HDA controller found on Tegra186 can be used for audio playback over HDMI.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
9733a251 |
| 28-Nov-2018 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Add RTC support on Tegra186
The RTC on Tegra186 is very similar to the RTC on earlier generations. One notable exception is that the source clock is now the 32 kHz clock instead of a d
arm64: tegra: Add RTC support on Tegra186
The RTC on Tegra186 is very similar to the RTC on earlier generations. One notable exception is that the source clock is now the 32 kHz clock instead of a dedicated RTC clock and the RTC alarm is a wake event and can be used to wake the system from sleep.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
32e66e46 |
| 28-Nov-2018 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Enable PMC wake events on Tegra186
Wake events are a feature that allows the interrupt and GPIO controllers to be powered off as part of system sleep. The PMC which is always on is mon
arm64: tegra: Enable PMC wake events on Tegra186
Wake events are a feature that allows the interrupt and GPIO controllers to be powered off as part of system sleep. The PMC which is always on is monitoring these wake events and can power up subsequent controllers as necessary to process them.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
207f60ba |
| 10-Aug-2018 |
Aapo Vienamo <avienamo@nvidia.com> |
arm64: dts: tegra186: Enable HS400
Enable HS400 signaling on Tegra186 SDMMC4 controller.
Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
22248e91 |
| 10-Aug-2018 |
Aapo Vienamo <avienamo@nvidia.com> |
arm64: dts: tegra186: Add SDMMC4 DQS trim value
Add the HS400 DQS trim value for Tegra186 SDMMC4.
Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
98a2494f |
| 10-Aug-2018 |
Aapo Vienamo <avienamo@nvidia.com> |
arm64: dts: tegra186: Assign clocks for sdmmc1 and sdmmc4
Configure sdmmc4 parent clock to pllc4 and sdmmc1 to pllp_out0 by setting the assigned-clocks device tree properties. pllc4 offer better jit
arm64: dts: tegra186: Assign clocks for sdmmc1 and sdmmc4
Configure sdmmc4 parent clock to pllc4 and sdmmc1 to pllp_out0 by setting the assigned-clocks device tree properties. pllc4 offer better jitter performance and should be used with higher speed modes like HS200 and HS400.
Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
6f90c6f0 |
| 10-Aug-2018 |
Aapo Vienamo <avienamo@nvidia.com> |
arm64: dts: tegra186: Add SDHCI tap and trim values
Add SDHCI inbound and outbound SDHCI sampling trimmer values for Tegra186.
Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Signed-off-by: Thier
arm64: dts: tegra186: Add SDHCI tap and trim values
Add SDHCI inbound and outbound SDHCI sampling trimmer values for Tegra186.
Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
41408c21 |
| 10-Aug-2018 |
Aapo Vienamo <avienamo@nvidia.com> |
arm64: dts: tegra186: Add sdmmc pad auto calibration offsets
Add the calibration offset properties used for automatic pad drive strength calibration.
Signed-off-by: Aapo Vienamo <avienamo@nvidia.co
arm64: dts: tegra186: Add sdmmc pad auto calibration offsets
Add the calibration offset properties used for automatic pad drive strength calibration.
Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
24005fd1 |
| 10-Aug-2018 |
Aapo Vienamo <avienamo@nvidia.com> |
arm64: dts: Add Tegra186 sdmmc pinctrl voltage states
Add pad voltage configuration nodes for sdmmc pads with configurable voltages on Tegra186.
Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Re
arm64: dts: Add Tegra186 sdmmc pinctrl voltage states
Add pad voltage configuration nodes for sdmmc pads with configurable voltages on Tegra186.
Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v4.12, v4.10.17, v4.10.16, v4.10.15, v4.10.14, v4.10.13, v4.10.12, v4.10.11, v4.10.10, v4.10.9, v4.10.8, v4.10.7 |
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#
c2599da7 |
| 28-Mar-2017 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Add display nodes on Tegra186
Adds the device tree nodes for the display hub and display controllers as well as the DPAUX, DSI and SOR controllers.
Signed-off-by: Thierry Reding <tred
arm64: tegra: Add display nodes on Tegra186
Adds the device tree nodes for the display hub and display controllers as well as the DPAUX, DSI and SOR controllers.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
b30a8e61 |
| 28-Mar-2017 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Add SMMU node for Tegra186
Add the DT node for ARM SMMU on Tegra186.
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: M
arm64: tegra: Add SMMU node for Tegra186
Add the DT node for ARM SMMU on Tegra186.
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
d25a3bf1 |
| 28-Mar-2017 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Add memory controller on Tegra186
Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
85593b75 |
| 26-Jun-2017 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Add FUSE block on Tegra186
The FUSE register block found on Tegra186 SoCs encodes various settings, such as calibration data for other blocks.
Signed-off-by: Thierry Reding <treding@n
arm64: tegra: Add FUSE block on Tegra186
The FUSE register block found on Tegra186 SoCs encodes various settings, such as calibration data for other blocks.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
94e25dc3 |
| 26-Jun-2017 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Add MISC registers on Tegra186
The MISC register block found on Tegra186 SoCs contains registers that can be used to identify a given chip and various strapping options.
Signed-off-by
arm64: tegra: Add MISC registers on Tegra186
The MISC register block found on Tegra186 SoCs contains registers that can be used to identify a given chip and various strapping options.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
b2441318 |
| 01-Nov-2017 |
Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine
License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license identifiers to apply.
- when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary:
SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became the concluded license(s).
- when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time.
In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related.
Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
15274c23 |
| 24-Jul-2017 |
Mikko Perttunen <mperttunen@nvidia.com> |
arm64: tegra: Add BPMP thermal sensor to Tegra186
This adds the thermal sensor device provided by the BPMP, and the relevant thermal sensors to the Tegra186 device tree.
Signed-off-by: Mikko Perttu
arm64: tegra: Add BPMP thermal sensor to Tegra186
This adds the thermal sensor device provided by the BPMP, and the relevant thermal sensors to the Tegra186 device tree.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
f8973cf4 |
| 27-Sep-2017 |
Manikanta Maddireddy <mmaddireddy@nvidia.com> |
arm64: tegra: Add PCIe node for Tegra186
Tegra186 has three PCIe controllers, which can be operated in 401, 211 or 111 lane combinations. Add DT support for PCIe controllers.
Signed-off-by: Manikan
arm64: tegra: Add PCIe node for Tegra186
Tegra186 has three PCIe controllers, which can be operated in 401, 211 or 111 lane combinations. Add DT support for PCIe controllers.
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
effc4b44 |
| 05-Sep-2017 |
Mikko Perttunen <mperttunen@nvidia.com> |
arm64: tegra: Add VIC on Tegra186
Add a node for the Video Image Compositor on the Tegra186.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
5524c61f |
| 05-Sep-2017 |
Mikko Perttunen <mperttunen@nvidia.com> |
arm64: tegra: Add host1x on Tegra186
Add the node for Host1x on the Tegra186, without any subdevices for now.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <t
arm64: tegra: Add host1x on Tegra186
Add the node for Host1x on the Tegra186, without any subdevices for now.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
dcbc5e44 |
| 05-Sep-2017 |
Mikko Perttunen <mperttunen@nvidia.com> |
arm64: tegra: Add #power-domain-cells for BPMP
Add #power-domain-cells for the BPMP node on Tegra186 so that the power domain provider may be used.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia
arm64: tegra: Add #power-domain-cells for BPMP
Add #power-domain-cells for the BPMP node on Tegra186 so that the power domain provider may be used.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
7b7ef494 |
| 01-Jun-2017 |
Mikko Perttunen <mperttunen@nvidia.com> |
arm64: tegra: Add CCPLEX_CLUSTER area in Tegra186
The Tegra186 CCPLEX_CLUSTER area contains memory-mapped registers that initiate CPU frequency/voltage transitions.
Signed-off-by: Mikko Perttunen <
arm64: tegra: Add CCPLEX_CLUSTER area in Tegra186
The Tegra186 CCPLEX_CLUSTER area contains memory-mapped registers that initiate CPU frequency/voltage transitions.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
dfd7a384 |
| 30-Mar-2017 |
Alexandre Courbot <acourbot@nvidia.com> |
arm64: tegra: Add GPU node for Tegra186
Add the DT node for the GP10B GPU on Tegra186.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v4.10.6, v4.10.5, v4.10.4, v4.10.3, v4.10.2, v4.10.1 |
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#
0caafbde |
| 23-Feb-2017 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Add ethernet support for Tegra186
The NVIDIA Tegra186 SoC contains an instance of the Synopsys DWC ethernet QOS IP block, which supports 10, 100 and 1000 Mbps data transfer rates.
Ack
arm64: tegra: Add ethernet support for Tegra186
The NVIDIA Tegra186 SoC contains an instance of the Synopsys DWC ethernet QOS IP block, which supports 10, 100 and 1000 Mbps data transfer rates.
Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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#
73bf90d4 |
| 23-Feb-2017 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Add PMC controller on Tegra186
The NVIDIA Tegra186 SoC has a Power Management Controller that performs various tasks related to system power, boot as well as suspend/resume.
Acked-by:
arm64: tegra: Add PMC controller on Tegra186
The NVIDIA Tegra186 SoC has a Power Management Controller that performs various tasks related to system power, boot as well as suspend/resume.
Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Revision tags: v4.10, v4.9 |
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#
7bcf2664 |
| 21-Nov-2016 |
Thierry Reding <treding@nvidia.com> |
arm64: tegra: Use symbolic reset identifiers
Now that the corresponding device tree binding include has been merged, convert the DTS files to use symbolic names instead of numeric ones.
Signed-off-
arm64: tegra: Use symbolic reset identifiers
Now that the corresponding device tree binding include has been merged, convert the DTS files to use symbolic names instead of numeric ones.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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