1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 status = "disabled"; 64 65 snps,write-requests = <1>; 66 snps,read-requests = <3>; 67 snps,burst-map = <0x7>; 68 snps,txpbl = <32>; 69 snps,rxpbl = <8>; 70 }; 71 72 memory-controller@2c00000 { 73 compatible = "nvidia,tegra186-mc"; 74 reg = <0x0 0x02c00000 0x0 0xb0000>; 75 status = "disabled"; 76 }; 77 78 uarta: serial@3100000 { 79 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 80 reg = <0x0 0x03100000 0x0 0x40>; 81 reg-shift = <2>; 82 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 83 clocks = <&bpmp TEGRA186_CLK_UARTA>; 84 clock-names = "serial"; 85 resets = <&bpmp TEGRA186_RESET_UARTA>; 86 reset-names = "serial"; 87 status = "disabled"; 88 }; 89 90 uartb: serial@3110000 { 91 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 92 reg = <0x0 0x03110000 0x0 0x40>; 93 reg-shift = <2>; 94 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 95 clocks = <&bpmp TEGRA186_CLK_UARTB>; 96 clock-names = "serial"; 97 resets = <&bpmp TEGRA186_RESET_UARTB>; 98 reset-names = "serial"; 99 status = "disabled"; 100 }; 101 102 uartd: serial@3130000 { 103 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 104 reg = <0x0 0x03130000 0x0 0x40>; 105 reg-shift = <2>; 106 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 107 clocks = <&bpmp TEGRA186_CLK_UARTD>; 108 clock-names = "serial"; 109 resets = <&bpmp TEGRA186_RESET_UARTD>; 110 reset-names = "serial"; 111 status = "disabled"; 112 }; 113 114 uarte: serial@3140000 { 115 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 116 reg = <0x0 0x03140000 0x0 0x40>; 117 reg-shift = <2>; 118 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 119 clocks = <&bpmp TEGRA186_CLK_UARTE>; 120 clock-names = "serial"; 121 resets = <&bpmp TEGRA186_RESET_UARTE>; 122 reset-names = "serial"; 123 status = "disabled"; 124 }; 125 126 uartf: serial@3150000 { 127 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 128 reg = <0x0 0x03150000 0x0 0x40>; 129 reg-shift = <2>; 130 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&bpmp TEGRA186_CLK_UARTF>; 132 clock-names = "serial"; 133 resets = <&bpmp TEGRA186_RESET_UARTF>; 134 reset-names = "serial"; 135 status = "disabled"; 136 }; 137 138 gen1_i2c: i2c@3160000 { 139 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 140 reg = <0x0 0x03160000 0x0 0x10000>; 141 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 clocks = <&bpmp TEGRA186_CLK_I2C1>; 145 clock-names = "div-clk"; 146 resets = <&bpmp TEGRA186_RESET_I2C1>; 147 reset-names = "i2c"; 148 status = "disabled"; 149 }; 150 151 cam_i2c: i2c@3180000 { 152 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 153 reg = <0x0 0x03180000 0x0 0x10000>; 154 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 155 #address-cells = <1>; 156 #size-cells = <0>; 157 clocks = <&bpmp TEGRA186_CLK_I2C3>; 158 clock-names = "div-clk"; 159 resets = <&bpmp TEGRA186_RESET_I2C3>; 160 reset-names = "i2c"; 161 status = "disabled"; 162 }; 163 164 /* shares pads with dpaux1 */ 165 dp_aux_ch1_i2c: i2c@3190000 { 166 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 167 reg = <0x0 0x03190000 0x0 0x10000>; 168 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 169 #address-cells = <1>; 170 #size-cells = <0>; 171 clocks = <&bpmp TEGRA186_CLK_I2C4>; 172 clock-names = "div-clk"; 173 resets = <&bpmp TEGRA186_RESET_I2C4>; 174 reset-names = "i2c"; 175 status = "disabled"; 176 }; 177 178 /* controlled by BPMP, should not be enabled */ 179 pwr_i2c: i2c@31a0000 { 180 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 181 reg = <0x0 0x031a0000 0x0 0x10000>; 182 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 183 #address-cells = <1>; 184 #size-cells = <0>; 185 clocks = <&bpmp TEGRA186_CLK_I2C5>; 186 clock-names = "div-clk"; 187 resets = <&bpmp TEGRA186_RESET_I2C5>; 188 reset-names = "i2c"; 189 status = "disabled"; 190 }; 191 192 /* shares pads with dpaux0 */ 193 dp_aux_ch0_i2c: i2c@31b0000 { 194 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 195 reg = <0x0 0x031b0000 0x0 0x10000>; 196 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 clocks = <&bpmp TEGRA186_CLK_I2C6>; 200 clock-names = "div-clk"; 201 resets = <&bpmp TEGRA186_RESET_I2C6>; 202 reset-names = "i2c"; 203 status = "disabled"; 204 }; 205 206 gen7_i2c: i2c@31c0000 { 207 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 208 reg = <0x0 0x031c0000 0x0 0x10000>; 209 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 clocks = <&bpmp TEGRA186_CLK_I2C7>; 213 clock-names = "div-clk"; 214 resets = <&bpmp TEGRA186_RESET_I2C7>; 215 reset-names = "i2c"; 216 status = "disabled"; 217 }; 218 219 gen9_i2c: i2c@31e0000 { 220 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 221 reg = <0x0 0x031e0000 0x0 0x10000>; 222 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 clocks = <&bpmp TEGRA186_CLK_I2C9>; 226 clock-names = "div-clk"; 227 resets = <&bpmp TEGRA186_RESET_I2C9>; 228 reset-names = "i2c"; 229 status = "disabled"; 230 }; 231 232 sdmmc1: sdhci@3400000 { 233 compatible = "nvidia,tegra186-sdhci"; 234 reg = <0x0 0x03400000 0x0 0x10000>; 235 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 237 clock-names = "sdhci"; 238 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 239 reset-names = "sdhci"; 240 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 241 pinctrl-0 = <&sdmmc1_3v3>; 242 pinctrl-1 = <&sdmmc1_1v8>; 243 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 244 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 245 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 246 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 247 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 248 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 249 nvidia,default-tap = <0x5>; 250 nvidia,default-trim = <0xb>; 251 status = "disabled"; 252 }; 253 254 sdmmc2: sdhci@3420000 { 255 compatible = "nvidia,tegra186-sdhci"; 256 reg = <0x0 0x03420000 0x0 0x10000>; 257 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 259 clock-names = "sdhci"; 260 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 261 reset-names = "sdhci"; 262 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 263 pinctrl-0 = <&sdmmc2_3v3>; 264 pinctrl-1 = <&sdmmc2_1v8>; 265 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 266 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 267 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 268 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 269 nvidia,default-tap = <0x5>; 270 nvidia,default-trim = <0xb>; 271 status = "disabled"; 272 }; 273 274 sdmmc3: sdhci@3440000 { 275 compatible = "nvidia,tegra186-sdhci"; 276 reg = <0x0 0x03440000 0x0 0x10000>; 277 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 278 clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 279 clock-names = "sdhci"; 280 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 281 reset-names = "sdhci"; 282 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 283 pinctrl-0 = <&sdmmc3_3v3>; 284 pinctrl-1 = <&sdmmc3_1v8>; 285 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 286 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 287 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 288 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 289 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 290 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 291 nvidia,default-tap = <0x5>; 292 nvidia,default-trim = <0xb>; 293 status = "disabled"; 294 }; 295 296 sdmmc4: sdhci@3460000 { 297 compatible = "nvidia,tegra186-sdhci"; 298 reg = <0x0 0x03460000 0x0 0x10000>; 299 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 300 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 301 clock-names = "sdhci"; 302 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 303 reset-names = "sdhci"; 304 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 305 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 306 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 307 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 308 nvidia,default-tap = <0x5>; 309 nvidia,default-trim = <0x9>; 310 status = "disabled"; 311 }; 312 313 fuse@3820000 { 314 compatible = "nvidia,tegra186-efuse"; 315 reg = <0x0 0x03820000 0x0 0x10000>; 316 clocks = <&bpmp TEGRA186_CLK_FUSE>; 317 clock-names = "fuse"; 318 }; 319 320 gic: interrupt-controller@3881000 { 321 compatible = "arm,gic-400"; 322 #interrupt-cells = <3>; 323 interrupt-controller; 324 reg = <0x0 0x03881000 0x0 0x1000>, 325 <0x0 0x03882000 0x0 0x2000>; 326 interrupts = <GIC_PPI 9 327 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 328 interrupt-parent = <&gic>; 329 }; 330 331 hsp_top0: hsp@3c00000 { 332 compatible = "nvidia,tegra186-hsp"; 333 reg = <0x0 0x03c00000 0x0 0xa0000>; 334 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 335 interrupt-names = "doorbell"; 336 #mbox-cells = <2>; 337 status = "disabled"; 338 }; 339 340 gen2_i2c: i2c@c240000 { 341 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 342 reg = <0x0 0x0c240000 0x0 0x10000>; 343 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 344 #address-cells = <1>; 345 #size-cells = <0>; 346 clocks = <&bpmp TEGRA186_CLK_I2C2>; 347 clock-names = "div-clk"; 348 resets = <&bpmp TEGRA186_RESET_I2C2>; 349 reset-names = "i2c"; 350 status = "disabled"; 351 }; 352 353 gen8_i2c: i2c@c250000 { 354 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 355 reg = <0x0 0x0c250000 0x0 0x10000>; 356 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 357 #address-cells = <1>; 358 #size-cells = <0>; 359 clocks = <&bpmp TEGRA186_CLK_I2C8>; 360 clock-names = "div-clk"; 361 resets = <&bpmp TEGRA186_RESET_I2C8>; 362 reset-names = "i2c"; 363 status = "disabled"; 364 }; 365 366 uartc: serial@c280000 { 367 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 368 reg = <0x0 0x0c280000 0x0 0x40>; 369 reg-shift = <2>; 370 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&bpmp TEGRA186_CLK_UARTC>; 372 clock-names = "serial"; 373 resets = <&bpmp TEGRA186_RESET_UARTC>; 374 reset-names = "serial"; 375 status = "disabled"; 376 }; 377 378 uartg: serial@c290000 { 379 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 380 reg = <0x0 0x0c290000 0x0 0x40>; 381 reg-shift = <2>; 382 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&bpmp TEGRA186_CLK_UARTG>; 384 clock-names = "serial"; 385 resets = <&bpmp TEGRA186_RESET_UARTG>; 386 reset-names = "serial"; 387 status = "disabled"; 388 }; 389 390 gpio_aon: gpio@c2f0000 { 391 compatible = "nvidia,tegra186-gpio-aon"; 392 reg-names = "security", "gpio"; 393 reg = <0x0 0xc2f0000 0x0 0x1000>, 394 <0x0 0xc2f1000 0x0 0x1000>; 395 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 396 gpio-controller; 397 #gpio-cells = <2>; 398 interrupt-controller; 399 #interrupt-cells = <2>; 400 }; 401 402 pmc@c360000 { 403 compatible = "nvidia,tegra186-pmc"; 404 reg = <0 0x0c360000 0 0x10000>, 405 <0 0x0c370000 0 0x10000>, 406 <0 0x0c380000 0 0x10000>, 407 <0 0x0c390000 0 0x10000>; 408 reg-names = "pmc", "wake", "aotag", "scratch"; 409 410 sdmmc1_3v3: sdmmc1-3v3 { 411 pins = "sdmmc1-hv"; 412 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 413 }; 414 415 sdmmc1_1v8: sdmmc1-1v8 { 416 pins = "sdmmc1-hv"; 417 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 418 }; 419 420 sdmmc2_3v3: sdmmc2-3v3 { 421 pins = "sdmmc2-hv"; 422 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 423 }; 424 425 sdmmc2_1v8: sdmmc2-1v8 { 426 pins = "sdmmc2-hv"; 427 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 428 }; 429 430 sdmmc3_3v3: sdmmc3-3v3 { 431 pins = "sdmmc3-hv"; 432 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 433 }; 434 435 sdmmc3_1v8: sdmmc3-1v8 { 436 pins = "sdmmc3-hv"; 437 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 438 }; 439 }; 440 441 ccplex@e000000 { 442 compatible = "nvidia,tegra186-ccplex-cluster"; 443 reg = <0x0 0x0e000000 0x0 0x3fffff>; 444 445 nvidia,bpmp = <&bpmp>; 446 }; 447 448 pcie@10003000 { 449 compatible = "nvidia,tegra186-pcie"; 450 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 451 device_type = "pci"; 452 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 453 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 454 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 455 reg-names = "pads", "afi", "cs"; 456 457 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 458 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 459 interrupt-names = "intr", "msi"; 460 461 #interrupt-cells = <1>; 462 interrupt-map-mask = <0 0 0 0>; 463 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 464 465 bus-range = <0x00 0xff>; 466 #address-cells = <3>; 467 #size-cells = <2>; 468 469 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 470 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 471 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 472 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 473 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 474 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 475 476 clocks = <&bpmp TEGRA186_CLK_AFI>, 477 <&bpmp TEGRA186_CLK_PCIE>, 478 <&bpmp TEGRA186_CLK_PLLE>; 479 clock-names = "afi", "pex", "pll_e"; 480 481 resets = <&bpmp TEGRA186_RESET_AFI>, 482 <&bpmp TEGRA186_RESET_PCIE>, 483 <&bpmp TEGRA186_RESET_PCIEXCLK>; 484 reset-names = "afi", "pex", "pcie_x"; 485 486 status = "disabled"; 487 488 pci@1,0 { 489 device_type = "pci"; 490 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 491 reg = <0x000800 0 0 0 0>; 492 status = "disabled"; 493 494 #address-cells = <3>; 495 #size-cells = <2>; 496 ranges; 497 498 nvidia,num-lanes = <2>; 499 }; 500 501 pci@2,0 { 502 device_type = "pci"; 503 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 504 reg = <0x001000 0 0 0 0>; 505 status = "disabled"; 506 507 #address-cells = <3>; 508 #size-cells = <2>; 509 ranges; 510 511 nvidia,num-lanes = <1>; 512 }; 513 514 pci@3,0 { 515 device_type = "pci"; 516 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 517 reg = <0x001800 0 0 0 0>; 518 status = "disabled"; 519 520 #address-cells = <3>; 521 #size-cells = <2>; 522 ranges; 523 524 nvidia,num-lanes = <1>; 525 }; 526 }; 527 528 smmu: iommu@12000000 { 529 compatible = "arm,mmu-500"; 530 reg = <0 0x12000000 0 0x800000>; 531 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 596 stream-match-mask = <0x7f80>; 597 #global-interrupts = <1>; 598 #iommu-cells = <1>; 599 }; 600 601 host1x@13e00000 { 602 compatible = "nvidia,tegra186-host1x", "simple-bus"; 603 reg = <0x0 0x13e00000 0x0 0x10000>, 604 <0x0 0x13e10000 0x0 0x10000>; 605 reg-names = "hypervisor", "vm"; 606 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 608 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 609 clock-names = "host1x"; 610 resets = <&bpmp TEGRA186_RESET_HOST1X>; 611 reset-names = "host1x"; 612 613 #address-cells = <1>; 614 #size-cells = <1>; 615 616 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 617 iommus = <&smmu TEGRA186_SID_HOST1X>; 618 619 dpaux1: dpaux@15040000 { 620 compatible = "nvidia,tegra186-dpaux"; 621 reg = <0x15040000 0x10000>; 622 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 623 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 624 <&bpmp TEGRA186_CLK_PLLDP>; 625 clock-names = "dpaux", "parent"; 626 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 627 reset-names = "dpaux"; 628 status = "disabled"; 629 630 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 631 632 state_dpaux1_aux: pinmux-aux { 633 groups = "dpaux-io"; 634 function = "aux"; 635 }; 636 637 state_dpaux1_i2c: pinmux-i2c { 638 groups = "dpaux-io"; 639 function = "i2c"; 640 }; 641 642 state_dpaux1_off: pinmux-off { 643 groups = "dpaux-io"; 644 function = "off"; 645 }; 646 647 i2c-bus { 648 #address-cells = <1>; 649 #size-cells = <0>; 650 }; 651 }; 652 653 display-hub@15200000 { 654 compatible = "nvidia,tegra186-display", "simple-bus"; 655 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 656 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 657 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 658 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 659 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 660 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 661 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 662 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 663 "wgrp3", "wgrp4", "wgrp5"; 664 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 665 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 666 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 667 clock-names = "disp", "dsc", "hub"; 668 status = "disabled"; 669 670 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 671 672 #address-cells = <1>; 673 #size-cells = <1>; 674 675 ranges = <0x15200000 0x15200000 0x40000>; 676 677 display@15200000 { 678 compatible = "nvidia,tegra186-dc"; 679 reg = <0x15200000 0x10000>; 680 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 681 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 682 clock-names = "dc"; 683 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 684 reset-names = "dc"; 685 686 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 687 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 688 689 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 690 nvidia,head = <0>; 691 }; 692 693 display@15210000 { 694 compatible = "nvidia,tegra186-dc"; 695 reg = <0x15210000 0x10000>; 696 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 697 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 698 clock-names = "dc"; 699 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 700 reset-names = "dc"; 701 702 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 703 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 704 705 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 706 nvidia,head = <1>; 707 }; 708 709 display@15220000 { 710 compatible = "nvidia,tegra186-dc"; 711 reg = <0x15220000 0x10000>; 712 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 713 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 714 clock-names = "dc"; 715 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 716 reset-names = "dc"; 717 718 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 719 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 720 721 nvidia,outputs = <&sor0 &sor1>; 722 nvidia,head = <2>; 723 }; 724 }; 725 726 dsia: dsi@15300000 { 727 compatible = "nvidia,tegra186-dsi"; 728 reg = <0x15300000 0x10000>; 729 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 730 clocks = <&bpmp TEGRA186_CLK_DSI>, 731 <&bpmp TEGRA186_CLK_DSIA_LP>, 732 <&bpmp TEGRA186_CLK_PLLD>; 733 clock-names = "dsi", "lp", "parent"; 734 resets = <&bpmp TEGRA186_RESET_DSI>; 735 reset-names = "dsi"; 736 status = "disabled"; 737 738 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 739 }; 740 741 vic@15340000 { 742 compatible = "nvidia,tegra186-vic"; 743 reg = <0x15340000 0x40000>; 744 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 745 clocks = <&bpmp TEGRA186_CLK_VIC>; 746 clock-names = "vic"; 747 resets = <&bpmp TEGRA186_RESET_VIC>; 748 reset-names = "vic"; 749 750 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 751 }; 752 753 dsib: dsi@15400000 { 754 compatible = "nvidia,tegra186-dsi"; 755 reg = <0x15400000 0x10000>; 756 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 757 clocks = <&bpmp TEGRA186_CLK_DSIB>, 758 <&bpmp TEGRA186_CLK_DSIB_LP>, 759 <&bpmp TEGRA186_CLK_PLLD>; 760 clock-names = "dsi", "lp", "parent"; 761 resets = <&bpmp TEGRA186_RESET_DSIB>; 762 reset-names = "dsi"; 763 status = "disabled"; 764 765 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 766 }; 767 768 sor0: sor@15540000 { 769 compatible = "nvidia,tegra186-sor"; 770 reg = <0x15540000 0x10000>; 771 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 772 clocks = <&bpmp TEGRA186_CLK_SOR0>, 773 <&bpmp TEGRA186_CLK_SOR0_OUT>, 774 <&bpmp TEGRA186_CLK_PLLD2>, 775 <&bpmp TEGRA186_CLK_PLLDP>, 776 <&bpmp TEGRA186_CLK_SOR_SAFE>, 777 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 778 clock-names = "sor", "out", "parent", "dp", "safe", 779 "pad"; 780 resets = <&bpmp TEGRA186_RESET_SOR0>; 781 reset-names = "sor"; 782 pinctrl-0 = <&state_dpaux_aux>; 783 pinctrl-1 = <&state_dpaux_i2c>; 784 pinctrl-2 = <&state_dpaux_off>; 785 pinctrl-names = "aux", "i2c", "off"; 786 status = "disabled"; 787 788 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 789 nvidia,interface = <0>; 790 }; 791 792 sor1: sor@15580000 { 793 compatible = "nvidia,tegra186-sor1"; 794 reg = <0x15580000 0x10000>; 795 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 796 clocks = <&bpmp TEGRA186_CLK_SOR1>, 797 <&bpmp TEGRA186_CLK_SOR1_OUT>, 798 <&bpmp TEGRA186_CLK_PLLD3>, 799 <&bpmp TEGRA186_CLK_PLLDP>, 800 <&bpmp TEGRA186_CLK_SOR_SAFE>, 801 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 802 clock-names = "sor", "out", "parent", "dp", "safe", 803 "pad"; 804 resets = <&bpmp TEGRA186_RESET_SOR1>; 805 reset-names = "sor"; 806 pinctrl-0 = <&state_dpaux1_aux>; 807 pinctrl-1 = <&state_dpaux1_i2c>; 808 pinctrl-2 = <&state_dpaux1_off>; 809 pinctrl-names = "aux", "i2c", "off"; 810 status = "disabled"; 811 812 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 813 nvidia,interface = <1>; 814 }; 815 816 dpaux: dpaux@155c0000 { 817 compatible = "nvidia,tegra186-dpaux"; 818 reg = <0x155c0000 0x10000>; 819 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 820 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 821 <&bpmp TEGRA186_CLK_PLLDP>; 822 clock-names = "dpaux", "parent"; 823 resets = <&bpmp TEGRA186_RESET_DPAUX>; 824 reset-names = "dpaux"; 825 status = "disabled"; 826 827 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 828 829 state_dpaux_aux: pinmux-aux { 830 groups = "dpaux-io"; 831 function = "aux"; 832 }; 833 834 state_dpaux_i2c: pinmux-i2c { 835 groups = "dpaux-io"; 836 function = "i2c"; 837 }; 838 839 state_dpaux_off: pinmux-off { 840 groups = "dpaux-io"; 841 function = "off"; 842 }; 843 844 i2c-bus { 845 #address-cells = <1>; 846 #size-cells = <0>; 847 }; 848 }; 849 850 padctl@15880000 { 851 compatible = "nvidia,tegra186-dsi-padctl"; 852 reg = <0x15880000 0x10000>; 853 resets = <&bpmp TEGRA186_RESET_DSI>; 854 reset-names = "dsi"; 855 status = "disabled"; 856 }; 857 858 dsic: dsi@15900000 { 859 compatible = "nvidia,tegra186-dsi"; 860 reg = <0x15900000 0x10000>; 861 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 862 clocks = <&bpmp TEGRA186_CLK_DSIC>, 863 <&bpmp TEGRA186_CLK_DSIC_LP>, 864 <&bpmp TEGRA186_CLK_PLLD>; 865 clock-names = "dsi", "lp", "parent"; 866 resets = <&bpmp TEGRA186_RESET_DSIC>; 867 reset-names = "dsi"; 868 status = "disabled"; 869 870 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 871 }; 872 873 dsid: dsi@15940000 { 874 compatible = "nvidia,tegra186-dsi"; 875 reg = <0x15940000 0x10000>; 876 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 877 clocks = <&bpmp TEGRA186_CLK_DSID>, 878 <&bpmp TEGRA186_CLK_DSID_LP>, 879 <&bpmp TEGRA186_CLK_PLLD>; 880 clock-names = "dsi", "lp", "parent"; 881 resets = <&bpmp TEGRA186_RESET_DSID>; 882 reset-names = "dsi"; 883 status = "disabled"; 884 885 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 886 }; 887 }; 888 889 gpu@17000000 { 890 compatible = "nvidia,gp10b"; 891 reg = <0x0 0x17000000 0x0 0x1000000>, 892 <0x0 0x18000000 0x0 0x1000000>; 893 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 894 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 895 interrupt-names = "stall", "nonstall"; 896 897 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 898 <&bpmp TEGRA186_CLK_GPU>; 899 clock-names = "gpu", "pwr"; 900 resets = <&bpmp TEGRA186_RESET_GPU>; 901 reset-names = "gpu"; 902 status = "disabled"; 903 904 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 905 }; 906 907 sysram@30000000 { 908 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 909 reg = <0x0 0x30000000 0x0 0x50000>; 910 #address-cells = <2>; 911 #size-cells = <2>; 912 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 913 914 cpu_bpmp_tx: shmem@4e000 { 915 compatible = "nvidia,tegra186-bpmp-shmem"; 916 reg = <0x0 0x4e000 0x0 0x1000>; 917 label = "cpu-bpmp-tx"; 918 pool; 919 }; 920 921 cpu_bpmp_rx: shmem@4f000 { 922 compatible = "nvidia,tegra186-bpmp-shmem"; 923 reg = <0x0 0x4f000 0x0 0x1000>; 924 label = "cpu-bpmp-rx"; 925 pool; 926 }; 927 }; 928 929 cpus { 930 #address-cells = <1>; 931 #size-cells = <0>; 932 933 cpu@0 { 934 compatible = "nvidia,tegra186-denver", "arm,armv8"; 935 device_type = "cpu"; 936 reg = <0x000>; 937 }; 938 939 cpu@1 { 940 compatible = "nvidia,tegra186-denver", "arm,armv8"; 941 device_type = "cpu"; 942 reg = <0x001>; 943 }; 944 945 cpu@2 { 946 compatible = "arm,cortex-a57", "arm,armv8"; 947 device_type = "cpu"; 948 reg = <0x100>; 949 }; 950 951 cpu@3 { 952 compatible = "arm,cortex-a57", "arm,armv8"; 953 device_type = "cpu"; 954 reg = <0x101>; 955 }; 956 957 cpu@4 { 958 compatible = "arm,cortex-a57", "arm,armv8"; 959 device_type = "cpu"; 960 reg = <0x102>; 961 }; 962 963 cpu@5 { 964 compatible = "arm,cortex-a57", "arm,armv8"; 965 device_type = "cpu"; 966 reg = <0x103>; 967 }; 968 }; 969 970 bpmp: bpmp { 971 compatible = "nvidia,tegra186-bpmp"; 972 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 973 TEGRA_HSP_DB_MASTER_BPMP>; 974 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 975 #clock-cells = <1>; 976 #reset-cells = <1>; 977 #power-domain-cells = <1>; 978 979 bpmp_i2c: i2c { 980 compatible = "nvidia,tegra186-bpmp-i2c"; 981 nvidia,bpmp-bus-id = <5>; 982 #address-cells = <1>; 983 #size-cells = <0>; 984 status = "disabled"; 985 }; 986 987 bpmp_thermal: thermal { 988 compatible = "nvidia,tegra186-bpmp-thermal"; 989 #thermal-sensor-cells = <1>; 990 }; 991 }; 992 993 thermal-zones { 994 a57 { 995 polling-delay = <0>; 996 polling-delay-passive = <1000>; 997 998 thermal-sensors = 999 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 1000 1001 trips { 1002 critical { 1003 temperature = <101000>; 1004 hysteresis = <0>; 1005 type = "critical"; 1006 }; 1007 }; 1008 1009 cooling-maps { 1010 }; 1011 }; 1012 1013 denver { 1014 polling-delay = <0>; 1015 polling-delay-passive = <1000>; 1016 1017 thermal-sensors = 1018 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 1019 1020 trips { 1021 critical { 1022 temperature = <101000>; 1023 hysteresis = <0>; 1024 type = "critical"; 1025 }; 1026 }; 1027 1028 cooling-maps { 1029 }; 1030 }; 1031 1032 gpu { 1033 polling-delay = <0>; 1034 polling-delay-passive = <1000>; 1035 1036 thermal-sensors = 1037 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 1038 1039 trips { 1040 critical { 1041 temperature = <101000>; 1042 hysteresis = <0>; 1043 type = "critical"; 1044 }; 1045 }; 1046 1047 cooling-maps { 1048 }; 1049 }; 1050 1051 pll { 1052 polling-delay = <0>; 1053 polling-delay-passive = <1000>; 1054 1055 thermal-sensors = 1056 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 1057 1058 trips { 1059 critical { 1060 temperature = <101000>; 1061 hysteresis = <0>; 1062 type = "critical"; 1063 }; 1064 }; 1065 1066 cooling-maps { 1067 }; 1068 }; 1069 1070 always_on { 1071 polling-delay = <0>; 1072 polling-delay-passive = <1000>; 1073 1074 thermal-sensors = 1075 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 1076 1077 trips { 1078 critical { 1079 temperature = <101000>; 1080 hysteresis = <0>; 1081 type = "critical"; 1082 }; 1083 }; 1084 1085 cooling-maps { 1086 }; 1087 }; 1088 }; 1089 1090 timer { 1091 compatible = "arm,armv8-timer"; 1092 interrupts = <GIC_PPI 13 1093 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1094 <GIC_PPI 14 1095 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1096 <GIC_PPI 11 1097 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1098 <GIC_PPI 10 1099 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1100 interrupt-parent = <&gic>; 1101 }; 1102}; 1103