1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 status = "disabled"; 64 65 snps,write-requests = <1>; 66 snps,read-requests = <3>; 67 snps,burst-map = <0x7>; 68 snps,txpbl = <32>; 69 snps,rxpbl = <8>; 70 }; 71 72 memory-controller@2c00000 { 73 compatible = "nvidia,tegra186-mc"; 74 reg = <0x0 0x02c00000 0x0 0xb0000>; 75 status = "disabled"; 76 }; 77 78 uarta: serial@3100000 { 79 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 80 reg = <0x0 0x03100000 0x0 0x40>; 81 reg-shift = <2>; 82 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 83 clocks = <&bpmp TEGRA186_CLK_UARTA>; 84 clock-names = "serial"; 85 resets = <&bpmp TEGRA186_RESET_UARTA>; 86 reset-names = "serial"; 87 status = "disabled"; 88 }; 89 90 uartb: serial@3110000 { 91 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 92 reg = <0x0 0x03110000 0x0 0x40>; 93 reg-shift = <2>; 94 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 95 clocks = <&bpmp TEGRA186_CLK_UARTB>; 96 clock-names = "serial"; 97 resets = <&bpmp TEGRA186_RESET_UARTB>; 98 reset-names = "serial"; 99 status = "disabled"; 100 }; 101 102 uartd: serial@3130000 { 103 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 104 reg = <0x0 0x03130000 0x0 0x40>; 105 reg-shift = <2>; 106 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 107 clocks = <&bpmp TEGRA186_CLK_UARTD>; 108 clock-names = "serial"; 109 resets = <&bpmp TEGRA186_RESET_UARTD>; 110 reset-names = "serial"; 111 status = "disabled"; 112 }; 113 114 uarte: serial@3140000 { 115 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 116 reg = <0x0 0x03140000 0x0 0x40>; 117 reg-shift = <2>; 118 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 119 clocks = <&bpmp TEGRA186_CLK_UARTE>; 120 clock-names = "serial"; 121 resets = <&bpmp TEGRA186_RESET_UARTE>; 122 reset-names = "serial"; 123 status = "disabled"; 124 }; 125 126 uartf: serial@3150000 { 127 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 128 reg = <0x0 0x03150000 0x0 0x40>; 129 reg-shift = <2>; 130 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&bpmp TEGRA186_CLK_UARTF>; 132 clock-names = "serial"; 133 resets = <&bpmp TEGRA186_RESET_UARTF>; 134 reset-names = "serial"; 135 status = "disabled"; 136 }; 137 138 gen1_i2c: i2c@3160000 { 139 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 140 reg = <0x0 0x03160000 0x0 0x10000>; 141 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 clocks = <&bpmp TEGRA186_CLK_I2C1>; 145 clock-names = "div-clk"; 146 resets = <&bpmp TEGRA186_RESET_I2C1>; 147 reset-names = "i2c"; 148 status = "disabled"; 149 }; 150 151 cam_i2c: i2c@3180000 { 152 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 153 reg = <0x0 0x03180000 0x0 0x10000>; 154 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 155 #address-cells = <1>; 156 #size-cells = <0>; 157 clocks = <&bpmp TEGRA186_CLK_I2C3>; 158 clock-names = "div-clk"; 159 resets = <&bpmp TEGRA186_RESET_I2C3>; 160 reset-names = "i2c"; 161 status = "disabled"; 162 }; 163 164 /* shares pads with dpaux1 */ 165 dp_aux_ch1_i2c: i2c@3190000 { 166 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 167 reg = <0x0 0x03190000 0x0 0x10000>; 168 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 169 #address-cells = <1>; 170 #size-cells = <0>; 171 clocks = <&bpmp TEGRA186_CLK_I2C4>; 172 clock-names = "div-clk"; 173 resets = <&bpmp TEGRA186_RESET_I2C4>; 174 reset-names = "i2c"; 175 status = "disabled"; 176 }; 177 178 /* controlled by BPMP, should not be enabled */ 179 pwr_i2c: i2c@31a0000 { 180 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 181 reg = <0x0 0x031a0000 0x0 0x10000>; 182 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 183 #address-cells = <1>; 184 #size-cells = <0>; 185 clocks = <&bpmp TEGRA186_CLK_I2C5>; 186 clock-names = "div-clk"; 187 resets = <&bpmp TEGRA186_RESET_I2C5>; 188 reset-names = "i2c"; 189 status = "disabled"; 190 }; 191 192 /* shares pads with dpaux0 */ 193 dp_aux_ch0_i2c: i2c@31b0000 { 194 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 195 reg = <0x0 0x031b0000 0x0 0x10000>; 196 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 clocks = <&bpmp TEGRA186_CLK_I2C6>; 200 clock-names = "div-clk"; 201 resets = <&bpmp TEGRA186_RESET_I2C6>; 202 reset-names = "i2c"; 203 status = "disabled"; 204 }; 205 206 gen7_i2c: i2c@31c0000 { 207 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 208 reg = <0x0 0x031c0000 0x0 0x10000>; 209 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 clocks = <&bpmp TEGRA186_CLK_I2C7>; 213 clock-names = "div-clk"; 214 resets = <&bpmp TEGRA186_RESET_I2C7>; 215 reset-names = "i2c"; 216 status = "disabled"; 217 }; 218 219 gen9_i2c: i2c@31e0000 { 220 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 221 reg = <0x0 0x031e0000 0x0 0x10000>; 222 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 clocks = <&bpmp TEGRA186_CLK_I2C9>; 226 clock-names = "div-clk"; 227 resets = <&bpmp TEGRA186_RESET_I2C9>; 228 reset-names = "i2c"; 229 status = "disabled"; 230 }; 231 232 sdmmc1: sdhci@3400000 { 233 compatible = "nvidia,tegra186-sdhci"; 234 reg = <0x0 0x03400000 0x0 0x10000>; 235 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 237 clock-names = "sdhci"; 238 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 239 reset-names = "sdhci"; 240 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 241 pinctrl-0 = <&sdmmc1_3v3>; 242 pinctrl-1 = <&sdmmc1_1v8>; 243 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 244 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 245 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 246 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 247 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 248 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 249 status = "disabled"; 250 }; 251 252 sdmmc2: sdhci@3420000 { 253 compatible = "nvidia,tegra186-sdhci"; 254 reg = <0x0 0x03420000 0x0 0x10000>; 255 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 256 clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 257 clock-names = "sdhci"; 258 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 259 reset-names = "sdhci"; 260 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 261 pinctrl-0 = <&sdmmc2_3v3>; 262 pinctrl-1 = <&sdmmc2_1v8>; 263 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 264 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 265 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 266 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 267 status = "disabled"; 268 }; 269 270 sdmmc3: sdhci@3440000 { 271 compatible = "nvidia,tegra186-sdhci"; 272 reg = <0x0 0x03440000 0x0 0x10000>; 273 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 274 clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 275 clock-names = "sdhci"; 276 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 277 reset-names = "sdhci"; 278 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 279 pinctrl-0 = <&sdmmc3_3v3>; 280 pinctrl-1 = <&sdmmc3_1v8>; 281 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 282 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 283 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 284 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 285 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 286 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 287 status = "disabled"; 288 }; 289 290 sdmmc4: sdhci@3460000 { 291 compatible = "nvidia,tegra186-sdhci"; 292 reg = <0x0 0x03460000 0x0 0x10000>; 293 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 295 clock-names = "sdhci"; 296 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 297 reset-names = "sdhci"; 298 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 299 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 300 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 301 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 302 status = "disabled"; 303 }; 304 305 fuse@3820000 { 306 compatible = "nvidia,tegra186-efuse"; 307 reg = <0x0 0x03820000 0x0 0x10000>; 308 clocks = <&bpmp TEGRA186_CLK_FUSE>; 309 clock-names = "fuse"; 310 }; 311 312 gic: interrupt-controller@3881000 { 313 compatible = "arm,gic-400"; 314 #interrupt-cells = <3>; 315 interrupt-controller; 316 reg = <0x0 0x03881000 0x0 0x1000>, 317 <0x0 0x03882000 0x0 0x2000>; 318 interrupts = <GIC_PPI 9 319 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 320 interrupt-parent = <&gic>; 321 }; 322 323 hsp_top0: hsp@3c00000 { 324 compatible = "nvidia,tegra186-hsp"; 325 reg = <0x0 0x03c00000 0x0 0xa0000>; 326 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 327 interrupt-names = "doorbell"; 328 #mbox-cells = <2>; 329 status = "disabled"; 330 }; 331 332 gen2_i2c: i2c@c240000 { 333 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 334 reg = <0x0 0x0c240000 0x0 0x10000>; 335 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 336 #address-cells = <1>; 337 #size-cells = <0>; 338 clocks = <&bpmp TEGRA186_CLK_I2C2>; 339 clock-names = "div-clk"; 340 resets = <&bpmp TEGRA186_RESET_I2C2>; 341 reset-names = "i2c"; 342 status = "disabled"; 343 }; 344 345 gen8_i2c: i2c@c250000 { 346 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 347 reg = <0x0 0x0c250000 0x0 0x10000>; 348 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 349 #address-cells = <1>; 350 #size-cells = <0>; 351 clocks = <&bpmp TEGRA186_CLK_I2C8>; 352 clock-names = "div-clk"; 353 resets = <&bpmp TEGRA186_RESET_I2C8>; 354 reset-names = "i2c"; 355 status = "disabled"; 356 }; 357 358 uartc: serial@c280000 { 359 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 360 reg = <0x0 0x0c280000 0x0 0x40>; 361 reg-shift = <2>; 362 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 363 clocks = <&bpmp TEGRA186_CLK_UARTC>; 364 clock-names = "serial"; 365 resets = <&bpmp TEGRA186_RESET_UARTC>; 366 reset-names = "serial"; 367 status = "disabled"; 368 }; 369 370 uartg: serial@c290000 { 371 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 372 reg = <0x0 0x0c290000 0x0 0x40>; 373 reg-shift = <2>; 374 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 375 clocks = <&bpmp TEGRA186_CLK_UARTG>; 376 clock-names = "serial"; 377 resets = <&bpmp TEGRA186_RESET_UARTG>; 378 reset-names = "serial"; 379 status = "disabled"; 380 }; 381 382 gpio_aon: gpio@c2f0000 { 383 compatible = "nvidia,tegra186-gpio-aon"; 384 reg-names = "security", "gpio"; 385 reg = <0x0 0xc2f0000 0x0 0x1000>, 386 <0x0 0xc2f1000 0x0 0x1000>; 387 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 388 gpio-controller; 389 #gpio-cells = <2>; 390 interrupt-controller; 391 #interrupt-cells = <2>; 392 }; 393 394 pmc@c360000 { 395 compatible = "nvidia,tegra186-pmc"; 396 reg = <0 0x0c360000 0 0x10000>, 397 <0 0x0c370000 0 0x10000>, 398 <0 0x0c380000 0 0x10000>, 399 <0 0x0c390000 0 0x10000>; 400 reg-names = "pmc", "wake", "aotag", "scratch"; 401 402 sdmmc1_3v3: sdmmc1-3v3 { 403 pins = "sdmmc1-hv"; 404 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 405 }; 406 407 sdmmc1_1v8: sdmmc1-1v8 { 408 pins = "sdmmc1-hv"; 409 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 410 }; 411 412 sdmmc2_3v3: sdmmc2-3v3 { 413 pins = "sdmmc2-hv"; 414 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 415 }; 416 417 sdmmc2_1v8: sdmmc2-1v8 { 418 pins = "sdmmc2-hv"; 419 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 420 }; 421 422 sdmmc3_3v3: sdmmc3-3v3 { 423 pins = "sdmmc3-hv"; 424 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 425 }; 426 427 sdmmc3_1v8: sdmmc3-1v8 { 428 pins = "sdmmc3-hv"; 429 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 430 }; 431 }; 432 433 ccplex@e000000 { 434 compatible = "nvidia,tegra186-ccplex-cluster"; 435 reg = <0x0 0x0e000000 0x0 0x3fffff>; 436 437 nvidia,bpmp = <&bpmp>; 438 }; 439 440 pcie@10003000 { 441 compatible = "nvidia,tegra186-pcie"; 442 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 443 device_type = "pci"; 444 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 445 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 446 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 447 reg-names = "pads", "afi", "cs"; 448 449 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 450 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 451 interrupt-names = "intr", "msi"; 452 453 #interrupt-cells = <1>; 454 interrupt-map-mask = <0 0 0 0>; 455 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 456 457 bus-range = <0x00 0xff>; 458 #address-cells = <3>; 459 #size-cells = <2>; 460 461 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 462 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 463 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 464 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 465 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 466 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 467 468 clocks = <&bpmp TEGRA186_CLK_AFI>, 469 <&bpmp TEGRA186_CLK_PCIE>, 470 <&bpmp TEGRA186_CLK_PLLE>; 471 clock-names = "afi", "pex", "pll_e"; 472 473 resets = <&bpmp TEGRA186_RESET_AFI>, 474 <&bpmp TEGRA186_RESET_PCIE>, 475 <&bpmp TEGRA186_RESET_PCIEXCLK>; 476 reset-names = "afi", "pex", "pcie_x"; 477 478 status = "disabled"; 479 480 pci@1,0 { 481 device_type = "pci"; 482 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 483 reg = <0x000800 0 0 0 0>; 484 status = "disabled"; 485 486 #address-cells = <3>; 487 #size-cells = <2>; 488 ranges; 489 490 nvidia,num-lanes = <2>; 491 }; 492 493 pci@2,0 { 494 device_type = "pci"; 495 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 496 reg = <0x001000 0 0 0 0>; 497 status = "disabled"; 498 499 #address-cells = <3>; 500 #size-cells = <2>; 501 ranges; 502 503 nvidia,num-lanes = <1>; 504 }; 505 506 pci@3,0 { 507 device_type = "pci"; 508 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 509 reg = <0x001800 0 0 0 0>; 510 status = "disabled"; 511 512 #address-cells = <3>; 513 #size-cells = <2>; 514 ranges; 515 516 nvidia,num-lanes = <1>; 517 }; 518 }; 519 520 smmu: iommu@12000000 { 521 compatible = "arm,mmu-500"; 522 reg = <0 0x12000000 0 0x800000>; 523 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 588 stream-match-mask = <0x7f80>; 589 #global-interrupts = <1>; 590 #iommu-cells = <1>; 591 }; 592 593 host1x@13e00000 { 594 compatible = "nvidia,tegra186-host1x", "simple-bus"; 595 reg = <0x0 0x13e00000 0x0 0x10000>, 596 <0x0 0x13e10000 0x0 0x10000>; 597 reg-names = "hypervisor", "vm"; 598 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 600 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 601 clock-names = "host1x"; 602 resets = <&bpmp TEGRA186_RESET_HOST1X>; 603 reset-names = "host1x"; 604 605 #address-cells = <1>; 606 #size-cells = <1>; 607 608 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 609 iommus = <&smmu TEGRA186_SID_HOST1X>; 610 611 dpaux1: dpaux@15040000 { 612 compatible = "nvidia,tegra186-dpaux"; 613 reg = <0x15040000 0x10000>; 614 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 615 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 616 <&bpmp TEGRA186_CLK_PLLDP>; 617 clock-names = "dpaux", "parent"; 618 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 619 reset-names = "dpaux"; 620 status = "disabled"; 621 622 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 623 624 state_dpaux1_aux: pinmux-aux { 625 groups = "dpaux-io"; 626 function = "aux"; 627 }; 628 629 state_dpaux1_i2c: pinmux-i2c { 630 groups = "dpaux-io"; 631 function = "i2c"; 632 }; 633 634 state_dpaux1_off: pinmux-off { 635 groups = "dpaux-io"; 636 function = "off"; 637 }; 638 639 i2c-bus { 640 #address-cells = <1>; 641 #size-cells = <0>; 642 }; 643 }; 644 645 display-hub@15200000 { 646 compatible = "nvidia,tegra186-display", "simple-bus"; 647 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 648 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 649 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 650 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 651 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 652 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 653 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 654 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 655 "wgrp3", "wgrp4", "wgrp5"; 656 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 657 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 658 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 659 clock-names = "disp", "dsc", "hub"; 660 status = "disabled"; 661 662 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 663 664 #address-cells = <1>; 665 #size-cells = <1>; 666 667 ranges = <0x15200000 0x15200000 0x40000>; 668 669 display@15200000 { 670 compatible = "nvidia,tegra186-dc"; 671 reg = <0x15200000 0x10000>; 672 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 673 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 674 clock-names = "dc"; 675 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 676 reset-names = "dc"; 677 678 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 679 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 680 681 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 682 nvidia,head = <0>; 683 }; 684 685 display@15210000 { 686 compatible = "nvidia,tegra186-dc"; 687 reg = <0x15210000 0x10000>; 688 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 689 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 690 clock-names = "dc"; 691 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 692 reset-names = "dc"; 693 694 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 695 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 696 697 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 698 nvidia,head = <1>; 699 }; 700 701 display@15220000 { 702 compatible = "nvidia,tegra186-dc"; 703 reg = <0x15220000 0x10000>; 704 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 705 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 706 clock-names = "dc"; 707 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 708 reset-names = "dc"; 709 710 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 711 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 712 713 nvidia,outputs = <&sor0 &sor1>; 714 nvidia,head = <2>; 715 }; 716 }; 717 718 dsia: dsi@15300000 { 719 compatible = "nvidia,tegra186-dsi"; 720 reg = <0x15300000 0x10000>; 721 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&bpmp TEGRA186_CLK_DSI>, 723 <&bpmp TEGRA186_CLK_DSIA_LP>, 724 <&bpmp TEGRA186_CLK_PLLD>; 725 clock-names = "dsi", "lp", "parent"; 726 resets = <&bpmp TEGRA186_RESET_DSI>; 727 reset-names = "dsi"; 728 status = "disabled"; 729 730 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 731 }; 732 733 vic@15340000 { 734 compatible = "nvidia,tegra186-vic"; 735 reg = <0x15340000 0x40000>; 736 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 737 clocks = <&bpmp TEGRA186_CLK_VIC>; 738 clock-names = "vic"; 739 resets = <&bpmp TEGRA186_RESET_VIC>; 740 reset-names = "vic"; 741 742 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 743 }; 744 745 dsib: dsi@15400000 { 746 compatible = "nvidia,tegra186-dsi"; 747 reg = <0x15400000 0x10000>; 748 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&bpmp TEGRA186_CLK_DSIB>, 750 <&bpmp TEGRA186_CLK_DSIB_LP>, 751 <&bpmp TEGRA186_CLK_PLLD>; 752 clock-names = "dsi", "lp", "parent"; 753 resets = <&bpmp TEGRA186_RESET_DSIB>; 754 reset-names = "dsi"; 755 status = "disabled"; 756 757 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 758 }; 759 760 sor0: sor@15540000 { 761 compatible = "nvidia,tegra186-sor"; 762 reg = <0x15540000 0x10000>; 763 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 764 clocks = <&bpmp TEGRA186_CLK_SOR0>, 765 <&bpmp TEGRA186_CLK_SOR0_OUT>, 766 <&bpmp TEGRA186_CLK_PLLD2>, 767 <&bpmp TEGRA186_CLK_PLLDP>, 768 <&bpmp TEGRA186_CLK_SOR_SAFE>, 769 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 770 clock-names = "sor", "out", "parent", "dp", "safe", 771 "pad"; 772 resets = <&bpmp TEGRA186_RESET_SOR0>; 773 reset-names = "sor"; 774 pinctrl-0 = <&state_dpaux_aux>; 775 pinctrl-1 = <&state_dpaux_i2c>; 776 pinctrl-2 = <&state_dpaux_off>; 777 pinctrl-names = "aux", "i2c", "off"; 778 status = "disabled"; 779 780 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 781 nvidia,interface = <0>; 782 }; 783 784 sor1: sor@15580000 { 785 compatible = "nvidia,tegra186-sor1"; 786 reg = <0x15580000 0x10000>; 787 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 788 clocks = <&bpmp TEGRA186_CLK_SOR1>, 789 <&bpmp TEGRA186_CLK_SOR1_OUT>, 790 <&bpmp TEGRA186_CLK_PLLD3>, 791 <&bpmp TEGRA186_CLK_PLLDP>, 792 <&bpmp TEGRA186_CLK_SOR_SAFE>, 793 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 794 clock-names = "sor", "out", "parent", "dp", "safe", 795 "pad"; 796 resets = <&bpmp TEGRA186_RESET_SOR1>; 797 reset-names = "sor"; 798 pinctrl-0 = <&state_dpaux1_aux>; 799 pinctrl-1 = <&state_dpaux1_i2c>; 800 pinctrl-2 = <&state_dpaux1_off>; 801 pinctrl-names = "aux", "i2c", "off"; 802 status = "disabled"; 803 804 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 805 nvidia,interface = <1>; 806 }; 807 808 dpaux: dpaux@155c0000 { 809 compatible = "nvidia,tegra186-dpaux"; 810 reg = <0x155c0000 0x10000>; 811 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 812 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 813 <&bpmp TEGRA186_CLK_PLLDP>; 814 clock-names = "dpaux", "parent"; 815 resets = <&bpmp TEGRA186_RESET_DPAUX>; 816 reset-names = "dpaux"; 817 status = "disabled"; 818 819 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 820 821 state_dpaux_aux: pinmux-aux { 822 groups = "dpaux-io"; 823 function = "aux"; 824 }; 825 826 state_dpaux_i2c: pinmux-i2c { 827 groups = "dpaux-io"; 828 function = "i2c"; 829 }; 830 831 state_dpaux_off: pinmux-off { 832 groups = "dpaux-io"; 833 function = "off"; 834 }; 835 836 i2c-bus { 837 #address-cells = <1>; 838 #size-cells = <0>; 839 }; 840 }; 841 842 padctl@15880000 { 843 compatible = "nvidia,tegra186-dsi-padctl"; 844 reg = <0x15880000 0x10000>; 845 resets = <&bpmp TEGRA186_RESET_DSI>; 846 reset-names = "dsi"; 847 status = "disabled"; 848 }; 849 850 dsic: dsi@15900000 { 851 compatible = "nvidia,tegra186-dsi"; 852 reg = <0x15900000 0x10000>; 853 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 854 clocks = <&bpmp TEGRA186_CLK_DSIC>, 855 <&bpmp TEGRA186_CLK_DSIC_LP>, 856 <&bpmp TEGRA186_CLK_PLLD>; 857 clock-names = "dsi", "lp", "parent"; 858 resets = <&bpmp TEGRA186_RESET_DSIC>; 859 reset-names = "dsi"; 860 status = "disabled"; 861 862 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 863 }; 864 865 dsid: dsi@15940000 { 866 compatible = "nvidia,tegra186-dsi"; 867 reg = <0x15940000 0x10000>; 868 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 869 clocks = <&bpmp TEGRA186_CLK_DSID>, 870 <&bpmp TEGRA186_CLK_DSID_LP>, 871 <&bpmp TEGRA186_CLK_PLLD>; 872 clock-names = "dsi", "lp", "parent"; 873 resets = <&bpmp TEGRA186_RESET_DSID>; 874 reset-names = "dsi"; 875 status = "disabled"; 876 877 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 878 }; 879 }; 880 881 gpu@17000000 { 882 compatible = "nvidia,gp10b"; 883 reg = <0x0 0x17000000 0x0 0x1000000>, 884 <0x0 0x18000000 0x0 0x1000000>; 885 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 886 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 887 interrupt-names = "stall", "nonstall"; 888 889 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 890 <&bpmp TEGRA186_CLK_GPU>; 891 clock-names = "gpu", "pwr"; 892 resets = <&bpmp TEGRA186_RESET_GPU>; 893 reset-names = "gpu"; 894 status = "disabled"; 895 896 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 897 }; 898 899 sysram@30000000 { 900 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 901 reg = <0x0 0x30000000 0x0 0x50000>; 902 #address-cells = <2>; 903 #size-cells = <2>; 904 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 905 906 cpu_bpmp_tx: shmem@4e000 { 907 compatible = "nvidia,tegra186-bpmp-shmem"; 908 reg = <0x0 0x4e000 0x0 0x1000>; 909 label = "cpu-bpmp-tx"; 910 pool; 911 }; 912 913 cpu_bpmp_rx: shmem@4f000 { 914 compatible = "nvidia,tegra186-bpmp-shmem"; 915 reg = <0x0 0x4f000 0x0 0x1000>; 916 label = "cpu-bpmp-rx"; 917 pool; 918 }; 919 }; 920 921 cpus { 922 #address-cells = <1>; 923 #size-cells = <0>; 924 925 cpu@0 { 926 compatible = "nvidia,tegra186-denver", "arm,armv8"; 927 device_type = "cpu"; 928 reg = <0x000>; 929 }; 930 931 cpu@1 { 932 compatible = "nvidia,tegra186-denver", "arm,armv8"; 933 device_type = "cpu"; 934 reg = <0x001>; 935 }; 936 937 cpu@2 { 938 compatible = "arm,cortex-a57", "arm,armv8"; 939 device_type = "cpu"; 940 reg = <0x100>; 941 }; 942 943 cpu@3 { 944 compatible = "arm,cortex-a57", "arm,armv8"; 945 device_type = "cpu"; 946 reg = <0x101>; 947 }; 948 949 cpu@4 { 950 compatible = "arm,cortex-a57", "arm,armv8"; 951 device_type = "cpu"; 952 reg = <0x102>; 953 }; 954 955 cpu@5 { 956 compatible = "arm,cortex-a57", "arm,armv8"; 957 device_type = "cpu"; 958 reg = <0x103>; 959 }; 960 }; 961 962 bpmp: bpmp { 963 compatible = "nvidia,tegra186-bpmp"; 964 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 965 TEGRA_HSP_DB_MASTER_BPMP>; 966 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 967 #clock-cells = <1>; 968 #reset-cells = <1>; 969 #power-domain-cells = <1>; 970 971 bpmp_i2c: i2c { 972 compatible = "nvidia,tegra186-bpmp-i2c"; 973 nvidia,bpmp-bus-id = <5>; 974 #address-cells = <1>; 975 #size-cells = <0>; 976 status = "disabled"; 977 }; 978 979 bpmp_thermal: thermal { 980 compatible = "nvidia,tegra186-bpmp-thermal"; 981 #thermal-sensor-cells = <1>; 982 }; 983 }; 984 985 thermal-zones { 986 a57 { 987 polling-delay = <0>; 988 polling-delay-passive = <1000>; 989 990 thermal-sensors = 991 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 992 993 trips { 994 critical { 995 temperature = <101000>; 996 hysteresis = <0>; 997 type = "critical"; 998 }; 999 }; 1000 1001 cooling-maps { 1002 }; 1003 }; 1004 1005 denver { 1006 polling-delay = <0>; 1007 polling-delay-passive = <1000>; 1008 1009 thermal-sensors = 1010 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 1011 1012 trips { 1013 critical { 1014 temperature = <101000>; 1015 hysteresis = <0>; 1016 type = "critical"; 1017 }; 1018 }; 1019 1020 cooling-maps { 1021 }; 1022 }; 1023 1024 gpu { 1025 polling-delay = <0>; 1026 polling-delay-passive = <1000>; 1027 1028 thermal-sensors = 1029 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 1030 1031 trips { 1032 critical { 1033 temperature = <101000>; 1034 hysteresis = <0>; 1035 type = "critical"; 1036 }; 1037 }; 1038 1039 cooling-maps { 1040 }; 1041 }; 1042 1043 pll { 1044 polling-delay = <0>; 1045 polling-delay-passive = <1000>; 1046 1047 thermal-sensors = 1048 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 1049 1050 trips { 1051 critical { 1052 temperature = <101000>; 1053 hysteresis = <0>; 1054 type = "critical"; 1055 }; 1056 }; 1057 1058 cooling-maps { 1059 }; 1060 }; 1061 1062 always_on { 1063 polling-delay = <0>; 1064 polling-delay-passive = <1000>; 1065 1066 thermal-sensors = 1067 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 1068 1069 trips { 1070 critical { 1071 temperature = <101000>; 1072 hysteresis = <0>; 1073 type = "critical"; 1074 }; 1075 }; 1076 1077 cooling-maps { 1078 }; 1079 }; 1080 }; 1081 1082 timer { 1083 compatible = "arm,armv8-timer"; 1084 interrupts = <GIC_PPI 13 1085 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1086 <GIC_PPI 14 1087 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1088 <GIC_PPI 11 1089 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1090 <GIC_PPI 10 1091 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1092 interrupt-parent = <&gic>; 1093 }; 1094}; 1095