1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 status = "disabled"; 64 65 snps,write-requests = <1>; 66 snps,read-requests = <3>; 67 snps,burst-map = <0x7>; 68 snps,txpbl = <32>; 69 snps,rxpbl = <8>; 70 }; 71 72 memory-controller@2c00000 { 73 compatible = "nvidia,tegra186-mc"; 74 reg = <0x0 0x02c00000 0x0 0xb0000>; 75 status = "disabled"; 76 }; 77 78 uarta: serial@3100000 { 79 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 80 reg = <0x0 0x03100000 0x0 0x40>; 81 reg-shift = <2>; 82 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 83 clocks = <&bpmp TEGRA186_CLK_UARTA>; 84 clock-names = "serial"; 85 resets = <&bpmp TEGRA186_RESET_UARTA>; 86 reset-names = "serial"; 87 status = "disabled"; 88 }; 89 90 uartb: serial@3110000 { 91 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 92 reg = <0x0 0x03110000 0x0 0x40>; 93 reg-shift = <2>; 94 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 95 clocks = <&bpmp TEGRA186_CLK_UARTB>; 96 clock-names = "serial"; 97 resets = <&bpmp TEGRA186_RESET_UARTB>; 98 reset-names = "serial"; 99 status = "disabled"; 100 }; 101 102 uartd: serial@3130000 { 103 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 104 reg = <0x0 0x03130000 0x0 0x40>; 105 reg-shift = <2>; 106 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 107 clocks = <&bpmp TEGRA186_CLK_UARTD>; 108 clock-names = "serial"; 109 resets = <&bpmp TEGRA186_RESET_UARTD>; 110 reset-names = "serial"; 111 status = "disabled"; 112 }; 113 114 uarte: serial@3140000 { 115 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 116 reg = <0x0 0x03140000 0x0 0x40>; 117 reg-shift = <2>; 118 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 119 clocks = <&bpmp TEGRA186_CLK_UARTE>; 120 clock-names = "serial"; 121 resets = <&bpmp TEGRA186_RESET_UARTE>; 122 reset-names = "serial"; 123 status = "disabled"; 124 }; 125 126 uartf: serial@3150000 { 127 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 128 reg = <0x0 0x03150000 0x0 0x40>; 129 reg-shift = <2>; 130 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&bpmp TEGRA186_CLK_UARTF>; 132 clock-names = "serial"; 133 resets = <&bpmp TEGRA186_RESET_UARTF>; 134 reset-names = "serial"; 135 status = "disabled"; 136 }; 137 138 gen1_i2c: i2c@3160000 { 139 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 140 reg = <0x0 0x03160000 0x0 0x10000>; 141 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 clocks = <&bpmp TEGRA186_CLK_I2C1>; 145 clock-names = "div-clk"; 146 resets = <&bpmp TEGRA186_RESET_I2C1>; 147 reset-names = "i2c"; 148 status = "disabled"; 149 }; 150 151 cam_i2c: i2c@3180000 { 152 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 153 reg = <0x0 0x03180000 0x0 0x10000>; 154 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 155 #address-cells = <1>; 156 #size-cells = <0>; 157 clocks = <&bpmp TEGRA186_CLK_I2C3>; 158 clock-names = "div-clk"; 159 resets = <&bpmp TEGRA186_RESET_I2C3>; 160 reset-names = "i2c"; 161 status = "disabled"; 162 }; 163 164 /* shares pads with dpaux1 */ 165 dp_aux_ch1_i2c: i2c@3190000 { 166 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 167 reg = <0x0 0x03190000 0x0 0x10000>; 168 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 169 #address-cells = <1>; 170 #size-cells = <0>; 171 clocks = <&bpmp TEGRA186_CLK_I2C4>; 172 clock-names = "div-clk"; 173 resets = <&bpmp TEGRA186_RESET_I2C4>; 174 reset-names = "i2c"; 175 status = "disabled"; 176 }; 177 178 /* controlled by BPMP, should not be enabled */ 179 pwr_i2c: i2c@31a0000 { 180 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 181 reg = <0x0 0x031a0000 0x0 0x10000>; 182 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 183 #address-cells = <1>; 184 #size-cells = <0>; 185 clocks = <&bpmp TEGRA186_CLK_I2C5>; 186 clock-names = "div-clk"; 187 resets = <&bpmp TEGRA186_RESET_I2C5>; 188 reset-names = "i2c"; 189 status = "disabled"; 190 }; 191 192 /* shares pads with dpaux0 */ 193 dp_aux_ch0_i2c: i2c@31b0000 { 194 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 195 reg = <0x0 0x031b0000 0x0 0x10000>; 196 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 clocks = <&bpmp TEGRA186_CLK_I2C6>; 200 clock-names = "div-clk"; 201 resets = <&bpmp TEGRA186_RESET_I2C6>; 202 reset-names = "i2c"; 203 status = "disabled"; 204 }; 205 206 gen7_i2c: i2c@31c0000 { 207 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 208 reg = <0x0 0x031c0000 0x0 0x10000>; 209 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 clocks = <&bpmp TEGRA186_CLK_I2C7>; 213 clock-names = "div-clk"; 214 resets = <&bpmp TEGRA186_RESET_I2C7>; 215 reset-names = "i2c"; 216 status = "disabled"; 217 }; 218 219 gen9_i2c: i2c@31e0000 { 220 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 221 reg = <0x0 0x031e0000 0x0 0x10000>; 222 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 clocks = <&bpmp TEGRA186_CLK_I2C9>; 226 clock-names = "div-clk"; 227 resets = <&bpmp TEGRA186_RESET_I2C9>; 228 reset-names = "i2c"; 229 status = "disabled"; 230 }; 231 232 sdmmc1: sdhci@3400000 { 233 compatible = "nvidia,tegra186-sdhci"; 234 reg = <0x0 0x03400000 0x0 0x10000>; 235 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 237 clock-names = "sdhci"; 238 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 239 reset-names = "sdhci"; 240 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 241 pinctrl-0 = <&sdmmc1_3v3>; 242 pinctrl-1 = <&sdmmc1_1v8>; 243 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 244 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 245 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 246 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 247 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 248 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 249 nvidia,default-tap = <0x5>; 250 nvidia,default-trim = <0xb>; 251 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 252 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 253 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 254 status = "disabled"; 255 }; 256 257 sdmmc2: sdhci@3420000 { 258 compatible = "nvidia,tegra186-sdhci"; 259 reg = <0x0 0x03420000 0x0 0x10000>; 260 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 262 clock-names = "sdhci"; 263 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 264 reset-names = "sdhci"; 265 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 266 pinctrl-0 = <&sdmmc2_3v3>; 267 pinctrl-1 = <&sdmmc2_1v8>; 268 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 269 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 270 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 271 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 272 nvidia,default-tap = <0x5>; 273 nvidia,default-trim = <0xb>; 274 status = "disabled"; 275 }; 276 277 sdmmc3: sdhci@3440000 { 278 compatible = "nvidia,tegra186-sdhci"; 279 reg = <0x0 0x03440000 0x0 0x10000>; 280 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 282 clock-names = "sdhci"; 283 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 284 reset-names = "sdhci"; 285 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 286 pinctrl-0 = <&sdmmc3_3v3>; 287 pinctrl-1 = <&sdmmc3_1v8>; 288 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 289 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 290 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 291 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 292 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 293 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 294 nvidia,default-tap = <0x5>; 295 nvidia,default-trim = <0xb>; 296 status = "disabled"; 297 }; 298 299 sdmmc4: sdhci@3460000 { 300 compatible = "nvidia,tegra186-sdhci"; 301 reg = <0x0 0x03460000 0x0 0x10000>; 302 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 303 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 304 clock-names = "sdhci"; 305 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 306 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 307 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 308 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 309 reset-names = "sdhci"; 310 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 311 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 312 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 313 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 314 nvidia,default-tap = <0x5>; 315 nvidia,default-trim = <0x9>; 316 nvidia,dqs-trim = <63>; 317 mmc-hs400-1_8v; 318 status = "disabled"; 319 }; 320 321 fuse@3820000 { 322 compatible = "nvidia,tegra186-efuse"; 323 reg = <0x0 0x03820000 0x0 0x10000>; 324 clocks = <&bpmp TEGRA186_CLK_FUSE>; 325 clock-names = "fuse"; 326 }; 327 328 gic: interrupt-controller@3881000 { 329 compatible = "arm,gic-400"; 330 #interrupt-cells = <3>; 331 interrupt-controller; 332 reg = <0x0 0x03881000 0x0 0x1000>, 333 <0x0 0x03882000 0x0 0x2000>; 334 interrupts = <GIC_PPI 9 335 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 336 interrupt-parent = <&gic>; 337 }; 338 339 hsp_top0: hsp@3c00000 { 340 compatible = "nvidia,tegra186-hsp"; 341 reg = <0x0 0x03c00000 0x0 0xa0000>; 342 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 343 interrupt-names = "doorbell"; 344 #mbox-cells = <2>; 345 status = "disabled"; 346 }; 347 348 gen2_i2c: i2c@c240000 { 349 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 350 reg = <0x0 0x0c240000 0x0 0x10000>; 351 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 352 #address-cells = <1>; 353 #size-cells = <0>; 354 clocks = <&bpmp TEGRA186_CLK_I2C2>; 355 clock-names = "div-clk"; 356 resets = <&bpmp TEGRA186_RESET_I2C2>; 357 reset-names = "i2c"; 358 status = "disabled"; 359 }; 360 361 gen8_i2c: i2c@c250000 { 362 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 363 reg = <0x0 0x0c250000 0x0 0x10000>; 364 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 365 #address-cells = <1>; 366 #size-cells = <0>; 367 clocks = <&bpmp TEGRA186_CLK_I2C8>; 368 clock-names = "div-clk"; 369 resets = <&bpmp TEGRA186_RESET_I2C8>; 370 reset-names = "i2c"; 371 status = "disabled"; 372 }; 373 374 uartc: serial@c280000 { 375 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 376 reg = <0x0 0x0c280000 0x0 0x40>; 377 reg-shift = <2>; 378 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&bpmp TEGRA186_CLK_UARTC>; 380 clock-names = "serial"; 381 resets = <&bpmp TEGRA186_RESET_UARTC>; 382 reset-names = "serial"; 383 status = "disabled"; 384 }; 385 386 uartg: serial@c290000 { 387 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 388 reg = <0x0 0x0c290000 0x0 0x40>; 389 reg-shift = <2>; 390 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 391 clocks = <&bpmp TEGRA186_CLK_UARTG>; 392 clock-names = "serial"; 393 resets = <&bpmp TEGRA186_RESET_UARTG>; 394 reset-names = "serial"; 395 status = "disabled"; 396 }; 397 398 gpio_aon: gpio@c2f0000 { 399 compatible = "nvidia,tegra186-gpio-aon"; 400 reg-names = "security", "gpio"; 401 reg = <0x0 0xc2f0000 0x0 0x1000>, 402 <0x0 0xc2f1000 0x0 0x1000>; 403 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 404 gpio-controller; 405 #gpio-cells = <2>; 406 interrupt-controller; 407 #interrupt-cells = <2>; 408 }; 409 410 pmc: pmc@c360000 { 411 compatible = "nvidia,tegra186-pmc"; 412 reg = <0 0x0c360000 0 0x10000>, 413 <0 0x0c370000 0 0x10000>, 414 <0 0x0c380000 0 0x10000>, 415 <0 0x0c390000 0 0x10000>; 416 reg-names = "pmc", "wake", "aotag", "scratch"; 417 418 #interrupt-cells = <2>; 419 interrupt-controller; 420 421 sdmmc1_3v3: sdmmc1-3v3 { 422 pins = "sdmmc1-hv"; 423 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 424 }; 425 426 sdmmc1_1v8: sdmmc1-1v8 { 427 pins = "sdmmc1-hv"; 428 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 429 }; 430 431 sdmmc2_3v3: sdmmc2-3v3 { 432 pins = "sdmmc2-hv"; 433 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 434 }; 435 436 sdmmc2_1v8: sdmmc2-1v8 { 437 pins = "sdmmc2-hv"; 438 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 439 }; 440 441 sdmmc3_3v3: sdmmc3-3v3 { 442 pins = "sdmmc3-hv"; 443 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 444 }; 445 446 sdmmc3_1v8: sdmmc3-1v8 { 447 pins = "sdmmc3-hv"; 448 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 449 }; 450 }; 451 452 ccplex@e000000 { 453 compatible = "nvidia,tegra186-ccplex-cluster"; 454 reg = <0x0 0x0e000000 0x0 0x3fffff>; 455 456 nvidia,bpmp = <&bpmp>; 457 }; 458 459 pcie@10003000 { 460 compatible = "nvidia,tegra186-pcie"; 461 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 462 device_type = "pci"; 463 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 464 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 465 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 466 reg-names = "pads", "afi", "cs"; 467 468 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 469 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 470 interrupt-names = "intr", "msi"; 471 472 #interrupt-cells = <1>; 473 interrupt-map-mask = <0 0 0 0>; 474 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 475 476 bus-range = <0x00 0xff>; 477 #address-cells = <3>; 478 #size-cells = <2>; 479 480 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 481 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 482 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 483 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 484 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 485 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 486 487 clocks = <&bpmp TEGRA186_CLK_AFI>, 488 <&bpmp TEGRA186_CLK_PCIE>, 489 <&bpmp TEGRA186_CLK_PLLE>; 490 clock-names = "afi", "pex", "pll_e"; 491 492 resets = <&bpmp TEGRA186_RESET_AFI>, 493 <&bpmp TEGRA186_RESET_PCIE>, 494 <&bpmp TEGRA186_RESET_PCIEXCLK>; 495 reset-names = "afi", "pex", "pcie_x"; 496 497 status = "disabled"; 498 499 pci@1,0 { 500 device_type = "pci"; 501 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 502 reg = <0x000800 0 0 0 0>; 503 status = "disabled"; 504 505 #address-cells = <3>; 506 #size-cells = <2>; 507 ranges; 508 509 nvidia,num-lanes = <2>; 510 }; 511 512 pci@2,0 { 513 device_type = "pci"; 514 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 515 reg = <0x001000 0 0 0 0>; 516 status = "disabled"; 517 518 #address-cells = <3>; 519 #size-cells = <2>; 520 ranges; 521 522 nvidia,num-lanes = <1>; 523 }; 524 525 pci@3,0 { 526 device_type = "pci"; 527 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 528 reg = <0x001800 0 0 0 0>; 529 status = "disabled"; 530 531 #address-cells = <3>; 532 #size-cells = <2>; 533 ranges; 534 535 nvidia,num-lanes = <1>; 536 }; 537 }; 538 539 smmu: iommu@12000000 { 540 compatible = "arm,mmu-500"; 541 reg = <0 0x12000000 0 0x800000>; 542 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 607 stream-match-mask = <0x7f80>; 608 #global-interrupts = <1>; 609 #iommu-cells = <1>; 610 }; 611 612 host1x@13e00000 { 613 compatible = "nvidia,tegra186-host1x", "simple-bus"; 614 reg = <0x0 0x13e00000 0x0 0x10000>, 615 <0x0 0x13e10000 0x0 0x10000>; 616 reg-names = "hypervisor", "vm"; 617 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 620 clock-names = "host1x"; 621 resets = <&bpmp TEGRA186_RESET_HOST1X>; 622 reset-names = "host1x"; 623 624 #address-cells = <1>; 625 #size-cells = <1>; 626 627 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 628 iommus = <&smmu TEGRA186_SID_HOST1X>; 629 630 dpaux1: dpaux@15040000 { 631 compatible = "nvidia,tegra186-dpaux"; 632 reg = <0x15040000 0x10000>; 633 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 635 <&bpmp TEGRA186_CLK_PLLDP>; 636 clock-names = "dpaux", "parent"; 637 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 638 reset-names = "dpaux"; 639 status = "disabled"; 640 641 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 642 643 state_dpaux1_aux: pinmux-aux { 644 groups = "dpaux-io"; 645 function = "aux"; 646 }; 647 648 state_dpaux1_i2c: pinmux-i2c { 649 groups = "dpaux-io"; 650 function = "i2c"; 651 }; 652 653 state_dpaux1_off: pinmux-off { 654 groups = "dpaux-io"; 655 function = "off"; 656 }; 657 658 i2c-bus { 659 #address-cells = <1>; 660 #size-cells = <0>; 661 }; 662 }; 663 664 display-hub@15200000 { 665 compatible = "nvidia,tegra186-display", "simple-bus"; 666 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 667 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 668 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 669 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 670 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 671 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 672 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 673 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 674 "wgrp3", "wgrp4", "wgrp5"; 675 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 676 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 677 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 678 clock-names = "disp", "dsc", "hub"; 679 status = "disabled"; 680 681 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 682 683 #address-cells = <1>; 684 #size-cells = <1>; 685 686 ranges = <0x15200000 0x15200000 0x40000>; 687 688 display@15200000 { 689 compatible = "nvidia,tegra186-dc"; 690 reg = <0x15200000 0x10000>; 691 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 692 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 693 clock-names = "dc"; 694 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 695 reset-names = "dc"; 696 697 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 698 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 699 700 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 701 nvidia,head = <0>; 702 }; 703 704 display@15210000 { 705 compatible = "nvidia,tegra186-dc"; 706 reg = <0x15210000 0x10000>; 707 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 708 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 709 clock-names = "dc"; 710 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 711 reset-names = "dc"; 712 713 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 714 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 715 716 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 717 nvidia,head = <1>; 718 }; 719 720 display@15220000 { 721 compatible = "nvidia,tegra186-dc"; 722 reg = <0x15220000 0x10000>; 723 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 724 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 725 clock-names = "dc"; 726 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 727 reset-names = "dc"; 728 729 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 730 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 731 732 nvidia,outputs = <&sor0 &sor1>; 733 nvidia,head = <2>; 734 }; 735 }; 736 737 dsia: dsi@15300000 { 738 compatible = "nvidia,tegra186-dsi"; 739 reg = <0x15300000 0x10000>; 740 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 741 clocks = <&bpmp TEGRA186_CLK_DSI>, 742 <&bpmp TEGRA186_CLK_DSIA_LP>, 743 <&bpmp TEGRA186_CLK_PLLD>; 744 clock-names = "dsi", "lp", "parent"; 745 resets = <&bpmp TEGRA186_RESET_DSI>; 746 reset-names = "dsi"; 747 status = "disabled"; 748 749 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 750 }; 751 752 vic@15340000 { 753 compatible = "nvidia,tegra186-vic"; 754 reg = <0x15340000 0x40000>; 755 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 756 clocks = <&bpmp TEGRA186_CLK_VIC>; 757 clock-names = "vic"; 758 resets = <&bpmp TEGRA186_RESET_VIC>; 759 reset-names = "vic"; 760 761 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 762 }; 763 764 dsib: dsi@15400000 { 765 compatible = "nvidia,tegra186-dsi"; 766 reg = <0x15400000 0x10000>; 767 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 768 clocks = <&bpmp TEGRA186_CLK_DSIB>, 769 <&bpmp TEGRA186_CLK_DSIB_LP>, 770 <&bpmp TEGRA186_CLK_PLLD>; 771 clock-names = "dsi", "lp", "parent"; 772 resets = <&bpmp TEGRA186_RESET_DSIB>; 773 reset-names = "dsi"; 774 status = "disabled"; 775 776 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 777 }; 778 779 sor0: sor@15540000 { 780 compatible = "nvidia,tegra186-sor"; 781 reg = <0x15540000 0x10000>; 782 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 783 clocks = <&bpmp TEGRA186_CLK_SOR0>, 784 <&bpmp TEGRA186_CLK_SOR0_OUT>, 785 <&bpmp TEGRA186_CLK_PLLD2>, 786 <&bpmp TEGRA186_CLK_PLLDP>, 787 <&bpmp TEGRA186_CLK_SOR_SAFE>, 788 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 789 clock-names = "sor", "out", "parent", "dp", "safe", 790 "pad"; 791 resets = <&bpmp TEGRA186_RESET_SOR0>; 792 reset-names = "sor"; 793 pinctrl-0 = <&state_dpaux_aux>; 794 pinctrl-1 = <&state_dpaux_i2c>; 795 pinctrl-2 = <&state_dpaux_off>; 796 pinctrl-names = "aux", "i2c", "off"; 797 status = "disabled"; 798 799 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 800 nvidia,interface = <0>; 801 }; 802 803 sor1: sor@15580000 { 804 compatible = "nvidia,tegra186-sor1"; 805 reg = <0x15580000 0x10000>; 806 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 807 clocks = <&bpmp TEGRA186_CLK_SOR1>, 808 <&bpmp TEGRA186_CLK_SOR1_OUT>, 809 <&bpmp TEGRA186_CLK_PLLD3>, 810 <&bpmp TEGRA186_CLK_PLLDP>, 811 <&bpmp TEGRA186_CLK_SOR_SAFE>, 812 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 813 clock-names = "sor", "out", "parent", "dp", "safe", 814 "pad"; 815 resets = <&bpmp TEGRA186_RESET_SOR1>; 816 reset-names = "sor"; 817 pinctrl-0 = <&state_dpaux1_aux>; 818 pinctrl-1 = <&state_dpaux1_i2c>; 819 pinctrl-2 = <&state_dpaux1_off>; 820 pinctrl-names = "aux", "i2c", "off"; 821 status = "disabled"; 822 823 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 824 nvidia,interface = <1>; 825 }; 826 827 dpaux: dpaux@155c0000 { 828 compatible = "nvidia,tegra186-dpaux"; 829 reg = <0x155c0000 0x10000>; 830 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 831 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 832 <&bpmp TEGRA186_CLK_PLLDP>; 833 clock-names = "dpaux", "parent"; 834 resets = <&bpmp TEGRA186_RESET_DPAUX>; 835 reset-names = "dpaux"; 836 status = "disabled"; 837 838 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 839 840 state_dpaux_aux: pinmux-aux { 841 groups = "dpaux-io"; 842 function = "aux"; 843 }; 844 845 state_dpaux_i2c: pinmux-i2c { 846 groups = "dpaux-io"; 847 function = "i2c"; 848 }; 849 850 state_dpaux_off: pinmux-off { 851 groups = "dpaux-io"; 852 function = "off"; 853 }; 854 855 i2c-bus { 856 #address-cells = <1>; 857 #size-cells = <0>; 858 }; 859 }; 860 861 padctl@15880000 { 862 compatible = "nvidia,tegra186-dsi-padctl"; 863 reg = <0x15880000 0x10000>; 864 resets = <&bpmp TEGRA186_RESET_DSI>; 865 reset-names = "dsi"; 866 status = "disabled"; 867 }; 868 869 dsic: dsi@15900000 { 870 compatible = "nvidia,tegra186-dsi"; 871 reg = <0x15900000 0x10000>; 872 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 873 clocks = <&bpmp TEGRA186_CLK_DSIC>, 874 <&bpmp TEGRA186_CLK_DSIC_LP>, 875 <&bpmp TEGRA186_CLK_PLLD>; 876 clock-names = "dsi", "lp", "parent"; 877 resets = <&bpmp TEGRA186_RESET_DSIC>; 878 reset-names = "dsi"; 879 status = "disabled"; 880 881 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 882 }; 883 884 dsid: dsi@15940000 { 885 compatible = "nvidia,tegra186-dsi"; 886 reg = <0x15940000 0x10000>; 887 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 888 clocks = <&bpmp TEGRA186_CLK_DSID>, 889 <&bpmp TEGRA186_CLK_DSID_LP>, 890 <&bpmp TEGRA186_CLK_PLLD>; 891 clock-names = "dsi", "lp", "parent"; 892 resets = <&bpmp TEGRA186_RESET_DSID>; 893 reset-names = "dsi"; 894 status = "disabled"; 895 896 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 897 }; 898 }; 899 900 gpu@17000000 { 901 compatible = "nvidia,gp10b"; 902 reg = <0x0 0x17000000 0x0 0x1000000>, 903 <0x0 0x18000000 0x0 0x1000000>; 904 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 905 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 906 interrupt-names = "stall", "nonstall"; 907 908 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 909 <&bpmp TEGRA186_CLK_GPU>; 910 clock-names = "gpu", "pwr"; 911 resets = <&bpmp TEGRA186_RESET_GPU>; 912 reset-names = "gpu"; 913 status = "disabled"; 914 915 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 916 }; 917 918 sysram@30000000 { 919 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 920 reg = <0x0 0x30000000 0x0 0x50000>; 921 #address-cells = <2>; 922 #size-cells = <2>; 923 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 924 925 cpu_bpmp_tx: shmem@4e000 { 926 compatible = "nvidia,tegra186-bpmp-shmem"; 927 reg = <0x0 0x4e000 0x0 0x1000>; 928 label = "cpu-bpmp-tx"; 929 pool; 930 }; 931 932 cpu_bpmp_rx: shmem@4f000 { 933 compatible = "nvidia,tegra186-bpmp-shmem"; 934 reg = <0x0 0x4f000 0x0 0x1000>; 935 label = "cpu-bpmp-rx"; 936 pool; 937 }; 938 }; 939 940 cpus { 941 #address-cells = <1>; 942 #size-cells = <0>; 943 944 cpu@0 { 945 compatible = "nvidia,tegra186-denver", "arm,armv8"; 946 device_type = "cpu"; 947 reg = <0x000>; 948 }; 949 950 cpu@1 { 951 compatible = "nvidia,tegra186-denver", "arm,armv8"; 952 device_type = "cpu"; 953 reg = <0x001>; 954 }; 955 956 cpu@2 { 957 compatible = "arm,cortex-a57", "arm,armv8"; 958 device_type = "cpu"; 959 reg = <0x100>; 960 }; 961 962 cpu@3 { 963 compatible = "arm,cortex-a57", "arm,armv8"; 964 device_type = "cpu"; 965 reg = <0x101>; 966 }; 967 968 cpu@4 { 969 compatible = "arm,cortex-a57", "arm,armv8"; 970 device_type = "cpu"; 971 reg = <0x102>; 972 }; 973 974 cpu@5 { 975 compatible = "arm,cortex-a57", "arm,armv8"; 976 device_type = "cpu"; 977 reg = <0x103>; 978 }; 979 }; 980 981 bpmp: bpmp { 982 compatible = "nvidia,tegra186-bpmp"; 983 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 984 TEGRA_HSP_DB_MASTER_BPMP>; 985 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 986 #clock-cells = <1>; 987 #reset-cells = <1>; 988 #power-domain-cells = <1>; 989 990 bpmp_i2c: i2c { 991 compatible = "nvidia,tegra186-bpmp-i2c"; 992 nvidia,bpmp-bus-id = <5>; 993 #address-cells = <1>; 994 #size-cells = <0>; 995 status = "disabled"; 996 }; 997 998 bpmp_thermal: thermal { 999 compatible = "nvidia,tegra186-bpmp-thermal"; 1000 #thermal-sensor-cells = <1>; 1001 }; 1002 }; 1003 1004 thermal-zones { 1005 a57 { 1006 polling-delay = <0>; 1007 polling-delay-passive = <1000>; 1008 1009 thermal-sensors = 1010 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 1011 1012 trips { 1013 critical { 1014 temperature = <101000>; 1015 hysteresis = <0>; 1016 type = "critical"; 1017 }; 1018 }; 1019 1020 cooling-maps { 1021 }; 1022 }; 1023 1024 denver { 1025 polling-delay = <0>; 1026 polling-delay-passive = <1000>; 1027 1028 thermal-sensors = 1029 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 1030 1031 trips { 1032 critical { 1033 temperature = <101000>; 1034 hysteresis = <0>; 1035 type = "critical"; 1036 }; 1037 }; 1038 1039 cooling-maps { 1040 }; 1041 }; 1042 1043 gpu { 1044 polling-delay = <0>; 1045 polling-delay-passive = <1000>; 1046 1047 thermal-sensors = 1048 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 1049 1050 trips { 1051 critical { 1052 temperature = <101000>; 1053 hysteresis = <0>; 1054 type = "critical"; 1055 }; 1056 }; 1057 1058 cooling-maps { 1059 }; 1060 }; 1061 1062 pll { 1063 polling-delay = <0>; 1064 polling-delay-passive = <1000>; 1065 1066 thermal-sensors = 1067 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 1068 1069 trips { 1070 critical { 1071 temperature = <101000>; 1072 hysteresis = <0>; 1073 type = "critical"; 1074 }; 1075 }; 1076 1077 cooling-maps { 1078 }; 1079 }; 1080 1081 always_on { 1082 polling-delay = <0>; 1083 polling-delay-passive = <1000>; 1084 1085 thermal-sensors = 1086 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 1087 1088 trips { 1089 critical { 1090 temperature = <101000>; 1091 hysteresis = <0>; 1092 type = "critical"; 1093 }; 1094 }; 1095 1096 cooling-maps { 1097 }; 1098 }; 1099 }; 1100 1101 timer { 1102 compatible = "arm,armv8-timer"; 1103 interrupts = <GIC_PPI 13 1104 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1105 <GIC_PPI 14 1106 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1107 <GIC_PPI 11 1108 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1109 <GIC_PPI 10 1110 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1111 interrupt-parent = <&gic>; 1112 }; 1113}; 1114