1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 status = "disabled"; 64 65 snps,write-requests = <1>; 66 snps,read-requests = <3>; 67 snps,burst-map = <0x7>; 68 snps,txpbl = <32>; 69 snps,rxpbl = <8>; 70 }; 71 72 memory-controller@2c00000 { 73 compatible = "nvidia,tegra186-mc"; 74 reg = <0x0 0x02c00000 0x0 0xb0000>; 75 status = "disabled"; 76 }; 77 78 uarta: serial@3100000 { 79 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 80 reg = <0x0 0x03100000 0x0 0x40>; 81 reg-shift = <2>; 82 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 83 clocks = <&bpmp TEGRA186_CLK_UARTA>; 84 clock-names = "serial"; 85 resets = <&bpmp TEGRA186_RESET_UARTA>; 86 reset-names = "serial"; 87 status = "disabled"; 88 }; 89 90 uartb: serial@3110000 { 91 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 92 reg = <0x0 0x03110000 0x0 0x40>; 93 reg-shift = <2>; 94 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 95 clocks = <&bpmp TEGRA186_CLK_UARTB>; 96 clock-names = "serial"; 97 resets = <&bpmp TEGRA186_RESET_UARTB>; 98 reset-names = "serial"; 99 status = "disabled"; 100 }; 101 102 uartd: serial@3130000 { 103 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 104 reg = <0x0 0x03130000 0x0 0x40>; 105 reg-shift = <2>; 106 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 107 clocks = <&bpmp TEGRA186_CLK_UARTD>; 108 clock-names = "serial"; 109 resets = <&bpmp TEGRA186_RESET_UARTD>; 110 reset-names = "serial"; 111 status = "disabled"; 112 }; 113 114 uarte: serial@3140000 { 115 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 116 reg = <0x0 0x03140000 0x0 0x40>; 117 reg-shift = <2>; 118 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 119 clocks = <&bpmp TEGRA186_CLK_UARTE>; 120 clock-names = "serial"; 121 resets = <&bpmp TEGRA186_RESET_UARTE>; 122 reset-names = "serial"; 123 status = "disabled"; 124 }; 125 126 uartf: serial@3150000 { 127 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 128 reg = <0x0 0x03150000 0x0 0x40>; 129 reg-shift = <2>; 130 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&bpmp TEGRA186_CLK_UARTF>; 132 clock-names = "serial"; 133 resets = <&bpmp TEGRA186_RESET_UARTF>; 134 reset-names = "serial"; 135 status = "disabled"; 136 }; 137 138 gen1_i2c: i2c@3160000 { 139 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 140 reg = <0x0 0x03160000 0x0 0x10000>; 141 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 clocks = <&bpmp TEGRA186_CLK_I2C1>; 145 clock-names = "div-clk"; 146 resets = <&bpmp TEGRA186_RESET_I2C1>; 147 reset-names = "i2c"; 148 status = "disabled"; 149 }; 150 151 cam_i2c: i2c@3180000 { 152 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 153 reg = <0x0 0x03180000 0x0 0x10000>; 154 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 155 #address-cells = <1>; 156 #size-cells = <0>; 157 clocks = <&bpmp TEGRA186_CLK_I2C3>; 158 clock-names = "div-clk"; 159 resets = <&bpmp TEGRA186_RESET_I2C3>; 160 reset-names = "i2c"; 161 status = "disabled"; 162 }; 163 164 /* shares pads with dpaux1 */ 165 dp_aux_ch1_i2c: i2c@3190000 { 166 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 167 reg = <0x0 0x03190000 0x0 0x10000>; 168 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 169 #address-cells = <1>; 170 #size-cells = <0>; 171 clocks = <&bpmp TEGRA186_CLK_I2C4>; 172 clock-names = "div-clk"; 173 resets = <&bpmp TEGRA186_RESET_I2C4>; 174 reset-names = "i2c"; 175 status = "disabled"; 176 }; 177 178 /* controlled by BPMP, should not be enabled */ 179 pwr_i2c: i2c@31a0000 { 180 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 181 reg = <0x0 0x031a0000 0x0 0x10000>; 182 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 183 #address-cells = <1>; 184 #size-cells = <0>; 185 clocks = <&bpmp TEGRA186_CLK_I2C5>; 186 clock-names = "div-clk"; 187 resets = <&bpmp TEGRA186_RESET_I2C5>; 188 reset-names = "i2c"; 189 status = "disabled"; 190 }; 191 192 /* shares pads with dpaux0 */ 193 dp_aux_ch0_i2c: i2c@31b0000 { 194 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 195 reg = <0x0 0x031b0000 0x0 0x10000>; 196 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 clocks = <&bpmp TEGRA186_CLK_I2C6>; 200 clock-names = "div-clk"; 201 resets = <&bpmp TEGRA186_RESET_I2C6>; 202 reset-names = "i2c"; 203 status = "disabled"; 204 }; 205 206 gen7_i2c: i2c@31c0000 { 207 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 208 reg = <0x0 0x031c0000 0x0 0x10000>; 209 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 clocks = <&bpmp TEGRA186_CLK_I2C7>; 213 clock-names = "div-clk"; 214 resets = <&bpmp TEGRA186_RESET_I2C7>; 215 reset-names = "i2c"; 216 status = "disabled"; 217 }; 218 219 gen9_i2c: i2c@31e0000 { 220 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 221 reg = <0x0 0x031e0000 0x0 0x10000>; 222 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 clocks = <&bpmp TEGRA186_CLK_I2C9>; 226 clock-names = "div-clk"; 227 resets = <&bpmp TEGRA186_RESET_I2C9>; 228 reset-names = "i2c"; 229 status = "disabled"; 230 }; 231 232 sdmmc1: sdhci@3400000 { 233 compatible = "nvidia,tegra186-sdhci"; 234 reg = <0x0 0x03400000 0x0 0x10000>; 235 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 237 clock-names = "sdhci"; 238 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 239 reset-names = "sdhci"; 240 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 241 pinctrl-0 = <&sdmmc1_3v3>; 242 pinctrl-1 = <&sdmmc1_1v8>; 243 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 244 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 245 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 246 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 247 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 248 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 249 nvidia,default-tap = <0x5>; 250 nvidia,default-trim = <0xb>; 251 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 252 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 253 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 254 status = "disabled"; 255 }; 256 257 sdmmc2: sdhci@3420000 { 258 compatible = "nvidia,tegra186-sdhci"; 259 reg = <0x0 0x03420000 0x0 0x10000>; 260 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 262 clock-names = "sdhci"; 263 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 264 reset-names = "sdhci"; 265 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 266 pinctrl-0 = <&sdmmc2_3v3>; 267 pinctrl-1 = <&sdmmc2_1v8>; 268 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 269 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 270 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 271 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 272 nvidia,default-tap = <0x5>; 273 nvidia,default-trim = <0xb>; 274 status = "disabled"; 275 }; 276 277 sdmmc3: sdhci@3440000 { 278 compatible = "nvidia,tegra186-sdhci"; 279 reg = <0x0 0x03440000 0x0 0x10000>; 280 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 282 clock-names = "sdhci"; 283 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 284 reset-names = "sdhci"; 285 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 286 pinctrl-0 = <&sdmmc3_3v3>; 287 pinctrl-1 = <&sdmmc3_1v8>; 288 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 289 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 290 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 291 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 292 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 293 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 294 nvidia,default-tap = <0x5>; 295 nvidia,default-trim = <0xb>; 296 status = "disabled"; 297 }; 298 299 sdmmc4: sdhci@3460000 { 300 compatible = "nvidia,tegra186-sdhci"; 301 reg = <0x0 0x03460000 0x0 0x10000>; 302 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 303 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 304 clock-names = "sdhci"; 305 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 306 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 307 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 308 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 309 reset-names = "sdhci"; 310 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 311 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 312 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 313 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 314 nvidia,default-tap = <0x5>; 315 nvidia,default-trim = <0x9>; 316 nvidia,dqs-trim = <63>; 317 status = "disabled"; 318 }; 319 320 fuse@3820000 { 321 compatible = "nvidia,tegra186-efuse"; 322 reg = <0x0 0x03820000 0x0 0x10000>; 323 clocks = <&bpmp TEGRA186_CLK_FUSE>; 324 clock-names = "fuse"; 325 }; 326 327 gic: interrupt-controller@3881000 { 328 compatible = "arm,gic-400"; 329 #interrupt-cells = <3>; 330 interrupt-controller; 331 reg = <0x0 0x03881000 0x0 0x1000>, 332 <0x0 0x03882000 0x0 0x2000>; 333 interrupts = <GIC_PPI 9 334 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 335 interrupt-parent = <&gic>; 336 }; 337 338 hsp_top0: hsp@3c00000 { 339 compatible = "nvidia,tegra186-hsp"; 340 reg = <0x0 0x03c00000 0x0 0xa0000>; 341 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 342 interrupt-names = "doorbell"; 343 #mbox-cells = <2>; 344 status = "disabled"; 345 }; 346 347 gen2_i2c: i2c@c240000 { 348 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 349 reg = <0x0 0x0c240000 0x0 0x10000>; 350 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 351 #address-cells = <1>; 352 #size-cells = <0>; 353 clocks = <&bpmp TEGRA186_CLK_I2C2>; 354 clock-names = "div-clk"; 355 resets = <&bpmp TEGRA186_RESET_I2C2>; 356 reset-names = "i2c"; 357 status = "disabled"; 358 }; 359 360 gen8_i2c: i2c@c250000 { 361 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 362 reg = <0x0 0x0c250000 0x0 0x10000>; 363 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 364 #address-cells = <1>; 365 #size-cells = <0>; 366 clocks = <&bpmp TEGRA186_CLK_I2C8>; 367 clock-names = "div-clk"; 368 resets = <&bpmp TEGRA186_RESET_I2C8>; 369 reset-names = "i2c"; 370 status = "disabled"; 371 }; 372 373 uartc: serial@c280000 { 374 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 375 reg = <0x0 0x0c280000 0x0 0x40>; 376 reg-shift = <2>; 377 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&bpmp TEGRA186_CLK_UARTC>; 379 clock-names = "serial"; 380 resets = <&bpmp TEGRA186_RESET_UARTC>; 381 reset-names = "serial"; 382 status = "disabled"; 383 }; 384 385 uartg: serial@c290000 { 386 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 387 reg = <0x0 0x0c290000 0x0 0x40>; 388 reg-shift = <2>; 389 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&bpmp TEGRA186_CLK_UARTG>; 391 clock-names = "serial"; 392 resets = <&bpmp TEGRA186_RESET_UARTG>; 393 reset-names = "serial"; 394 status = "disabled"; 395 }; 396 397 gpio_aon: gpio@c2f0000 { 398 compatible = "nvidia,tegra186-gpio-aon"; 399 reg-names = "security", "gpio"; 400 reg = <0x0 0xc2f0000 0x0 0x1000>, 401 <0x0 0xc2f1000 0x0 0x1000>; 402 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 403 gpio-controller; 404 #gpio-cells = <2>; 405 interrupt-controller; 406 #interrupt-cells = <2>; 407 }; 408 409 pmc@c360000 { 410 compatible = "nvidia,tegra186-pmc"; 411 reg = <0 0x0c360000 0 0x10000>, 412 <0 0x0c370000 0 0x10000>, 413 <0 0x0c380000 0 0x10000>, 414 <0 0x0c390000 0 0x10000>; 415 reg-names = "pmc", "wake", "aotag", "scratch"; 416 417 sdmmc1_3v3: sdmmc1-3v3 { 418 pins = "sdmmc1-hv"; 419 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 420 }; 421 422 sdmmc1_1v8: sdmmc1-1v8 { 423 pins = "sdmmc1-hv"; 424 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 425 }; 426 427 sdmmc2_3v3: sdmmc2-3v3 { 428 pins = "sdmmc2-hv"; 429 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 430 }; 431 432 sdmmc2_1v8: sdmmc2-1v8 { 433 pins = "sdmmc2-hv"; 434 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 435 }; 436 437 sdmmc3_3v3: sdmmc3-3v3 { 438 pins = "sdmmc3-hv"; 439 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 440 }; 441 442 sdmmc3_1v8: sdmmc3-1v8 { 443 pins = "sdmmc3-hv"; 444 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 445 }; 446 }; 447 448 ccplex@e000000 { 449 compatible = "nvidia,tegra186-ccplex-cluster"; 450 reg = <0x0 0x0e000000 0x0 0x3fffff>; 451 452 nvidia,bpmp = <&bpmp>; 453 }; 454 455 pcie@10003000 { 456 compatible = "nvidia,tegra186-pcie"; 457 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 458 device_type = "pci"; 459 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 460 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 461 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 462 reg-names = "pads", "afi", "cs"; 463 464 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 465 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 466 interrupt-names = "intr", "msi"; 467 468 #interrupt-cells = <1>; 469 interrupt-map-mask = <0 0 0 0>; 470 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 471 472 bus-range = <0x00 0xff>; 473 #address-cells = <3>; 474 #size-cells = <2>; 475 476 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 477 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 478 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 479 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 480 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 481 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 482 483 clocks = <&bpmp TEGRA186_CLK_AFI>, 484 <&bpmp TEGRA186_CLK_PCIE>, 485 <&bpmp TEGRA186_CLK_PLLE>; 486 clock-names = "afi", "pex", "pll_e"; 487 488 resets = <&bpmp TEGRA186_RESET_AFI>, 489 <&bpmp TEGRA186_RESET_PCIE>, 490 <&bpmp TEGRA186_RESET_PCIEXCLK>; 491 reset-names = "afi", "pex", "pcie_x"; 492 493 status = "disabled"; 494 495 pci@1,0 { 496 device_type = "pci"; 497 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 498 reg = <0x000800 0 0 0 0>; 499 status = "disabled"; 500 501 #address-cells = <3>; 502 #size-cells = <2>; 503 ranges; 504 505 nvidia,num-lanes = <2>; 506 }; 507 508 pci@2,0 { 509 device_type = "pci"; 510 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 511 reg = <0x001000 0 0 0 0>; 512 status = "disabled"; 513 514 #address-cells = <3>; 515 #size-cells = <2>; 516 ranges; 517 518 nvidia,num-lanes = <1>; 519 }; 520 521 pci@3,0 { 522 device_type = "pci"; 523 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 524 reg = <0x001800 0 0 0 0>; 525 status = "disabled"; 526 527 #address-cells = <3>; 528 #size-cells = <2>; 529 ranges; 530 531 nvidia,num-lanes = <1>; 532 }; 533 }; 534 535 smmu: iommu@12000000 { 536 compatible = "arm,mmu-500"; 537 reg = <0 0x12000000 0 0x800000>; 538 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 603 stream-match-mask = <0x7f80>; 604 #global-interrupts = <1>; 605 #iommu-cells = <1>; 606 }; 607 608 host1x@13e00000 { 609 compatible = "nvidia,tegra186-host1x", "simple-bus"; 610 reg = <0x0 0x13e00000 0x0 0x10000>, 611 <0x0 0x13e10000 0x0 0x10000>; 612 reg-names = "hypervisor", "vm"; 613 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 615 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 616 clock-names = "host1x"; 617 resets = <&bpmp TEGRA186_RESET_HOST1X>; 618 reset-names = "host1x"; 619 620 #address-cells = <1>; 621 #size-cells = <1>; 622 623 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 624 iommus = <&smmu TEGRA186_SID_HOST1X>; 625 626 dpaux1: dpaux@15040000 { 627 compatible = "nvidia,tegra186-dpaux"; 628 reg = <0x15040000 0x10000>; 629 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 630 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 631 <&bpmp TEGRA186_CLK_PLLDP>; 632 clock-names = "dpaux", "parent"; 633 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 634 reset-names = "dpaux"; 635 status = "disabled"; 636 637 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 638 639 state_dpaux1_aux: pinmux-aux { 640 groups = "dpaux-io"; 641 function = "aux"; 642 }; 643 644 state_dpaux1_i2c: pinmux-i2c { 645 groups = "dpaux-io"; 646 function = "i2c"; 647 }; 648 649 state_dpaux1_off: pinmux-off { 650 groups = "dpaux-io"; 651 function = "off"; 652 }; 653 654 i2c-bus { 655 #address-cells = <1>; 656 #size-cells = <0>; 657 }; 658 }; 659 660 display-hub@15200000 { 661 compatible = "nvidia,tegra186-display", "simple-bus"; 662 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 663 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 664 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 665 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 666 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 667 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 668 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 669 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 670 "wgrp3", "wgrp4", "wgrp5"; 671 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 672 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 673 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 674 clock-names = "disp", "dsc", "hub"; 675 status = "disabled"; 676 677 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 678 679 #address-cells = <1>; 680 #size-cells = <1>; 681 682 ranges = <0x15200000 0x15200000 0x40000>; 683 684 display@15200000 { 685 compatible = "nvidia,tegra186-dc"; 686 reg = <0x15200000 0x10000>; 687 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 688 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 689 clock-names = "dc"; 690 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 691 reset-names = "dc"; 692 693 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 694 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 695 696 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 697 nvidia,head = <0>; 698 }; 699 700 display@15210000 { 701 compatible = "nvidia,tegra186-dc"; 702 reg = <0x15210000 0x10000>; 703 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 704 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 705 clock-names = "dc"; 706 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 707 reset-names = "dc"; 708 709 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 710 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 711 712 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 713 nvidia,head = <1>; 714 }; 715 716 display@15220000 { 717 compatible = "nvidia,tegra186-dc"; 718 reg = <0x15220000 0x10000>; 719 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 720 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 721 clock-names = "dc"; 722 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 723 reset-names = "dc"; 724 725 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 726 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 727 728 nvidia,outputs = <&sor0 &sor1>; 729 nvidia,head = <2>; 730 }; 731 }; 732 733 dsia: dsi@15300000 { 734 compatible = "nvidia,tegra186-dsi"; 735 reg = <0x15300000 0x10000>; 736 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 737 clocks = <&bpmp TEGRA186_CLK_DSI>, 738 <&bpmp TEGRA186_CLK_DSIA_LP>, 739 <&bpmp TEGRA186_CLK_PLLD>; 740 clock-names = "dsi", "lp", "parent"; 741 resets = <&bpmp TEGRA186_RESET_DSI>; 742 reset-names = "dsi"; 743 status = "disabled"; 744 745 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 746 }; 747 748 vic@15340000 { 749 compatible = "nvidia,tegra186-vic"; 750 reg = <0x15340000 0x40000>; 751 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 752 clocks = <&bpmp TEGRA186_CLK_VIC>; 753 clock-names = "vic"; 754 resets = <&bpmp TEGRA186_RESET_VIC>; 755 reset-names = "vic"; 756 757 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 758 }; 759 760 dsib: dsi@15400000 { 761 compatible = "nvidia,tegra186-dsi"; 762 reg = <0x15400000 0x10000>; 763 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 764 clocks = <&bpmp TEGRA186_CLK_DSIB>, 765 <&bpmp TEGRA186_CLK_DSIB_LP>, 766 <&bpmp TEGRA186_CLK_PLLD>; 767 clock-names = "dsi", "lp", "parent"; 768 resets = <&bpmp TEGRA186_RESET_DSIB>; 769 reset-names = "dsi"; 770 status = "disabled"; 771 772 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 773 }; 774 775 sor0: sor@15540000 { 776 compatible = "nvidia,tegra186-sor"; 777 reg = <0x15540000 0x10000>; 778 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&bpmp TEGRA186_CLK_SOR0>, 780 <&bpmp TEGRA186_CLK_SOR0_OUT>, 781 <&bpmp TEGRA186_CLK_PLLD2>, 782 <&bpmp TEGRA186_CLK_PLLDP>, 783 <&bpmp TEGRA186_CLK_SOR_SAFE>, 784 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 785 clock-names = "sor", "out", "parent", "dp", "safe", 786 "pad"; 787 resets = <&bpmp TEGRA186_RESET_SOR0>; 788 reset-names = "sor"; 789 pinctrl-0 = <&state_dpaux_aux>; 790 pinctrl-1 = <&state_dpaux_i2c>; 791 pinctrl-2 = <&state_dpaux_off>; 792 pinctrl-names = "aux", "i2c", "off"; 793 status = "disabled"; 794 795 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 796 nvidia,interface = <0>; 797 }; 798 799 sor1: sor@15580000 { 800 compatible = "nvidia,tegra186-sor1"; 801 reg = <0x15580000 0x10000>; 802 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 803 clocks = <&bpmp TEGRA186_CLK_SOR1>, 804 <&bpmp TEGRA186_CLK_SOR1_OUT>, 805 <&bpmp TEGRA186_CLK_PLLD3>, 806 <&bpmp TEGRA186_CLK_PLLDP>, 807 <&bpmp TEGRA186_CLK_SOR_SAFE>, 808 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 809 clock-names = "sor", "out", "parent", "dp", "safe", 810 "pad"; 811 resets = <&bpmp TEGRA186_RESET_SOR1>; 812 reset-names = "sor"; 813 pinctrl-0 = <&state_dpaux1_aux>; 814 pinctrl-1 = <&state_dpaux1_i2c>; 815 pinctrl-2 = <&state_dpaux1_off>; 816 pinctrl-names = "aux", "i2c", "off"; 817 status = "disabled"; 818 819 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 820 nvidia,interface = <1>; 821 }; 822 823 dpaux: dpaux@155c0000 { 824 compatible = "nvidia,tegra186-dpaux"; 825 reg = <0x155c0000 0x10000>; 826 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 827 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 828 <&bpmp TEGRA186_CLK_PLLDP>; 829 clock-names = "dpaux", "parent"; 830 resets = <&bpmp TEGRA186_RESET_DPAUX>; 831 reset-names = "dpaux"; 832 status = "disabled"; 833 834 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 835 836 state_dpaux_aux: pinmux-aux { 837 groups = "dpaux-io"; 838 function = "aux"; 839 }; 840 841 state_dpaux_i2c: pinmux-i2c { 842 groups = "dpaux-io"; 843 function = "i2c"; 844 }; 845 846 state_dpaux_off: pinmux-off { 847 groups = "dpaux-io"; 848 function = "off"; 849 }; 850 851 i2c-bus { 852 #address-cells = <1>; 853 #size-cells = <0>; 854 }; 855 }; 856 857 padctl@15880000 { 858 compatible = "nvidia,tegra186-dsi-padctl"; 859 reg = <0x15880000 0x10000>; 860 resets = <&bpmp TEGRA186_RESET_DSI>; 861 reset-names = "dsi"; 862 status = "disabled"; 863 }; 864 865 dsic: dsi@15900000 { 866 compatible = "nvidia,tegra186-dsi"; 867 reg = <0x15900000 0x10000>; 868 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 869 clocks = <&bpmp TEGRA186_CLK_DSIC>, 870 <&bpmp TEGRA186_CLK_DSIC_LP>, 871 <&bpmp TEGRA186_CLK_PLLD>; 872 clock-names = "dsi", "lp", "parent"; 873 resets = <&bpmp TEGRA186_RESET_DSIC>; 874 reset-names = "dsi"; 875 status = "disabled"; 876 877 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 878 }; 879 880 dsid: dsi@15940000 { 881 compatible = "nvidia,tegra186-dsi"; 882 reg = <0x15940000 0x10000>; 883 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 884 clocks = <&bpmp TEGRA186_CLK_DSID>, 885 <&bpmp TEGRA186_CLK_DSID_LP>, 886 <&bpmp TEGRA186_CLK_PLLD>; 887 clock-names = "dsi", "lp", "parent"; 888 resets = <&bpmp TEGRA186_RESET_DSID>; 889 reset-names = "dsi"; 890 status = "disabled"; 891 892 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 893 }; 894 }; 895 896 gpu@17000000 { 897 compatible = "nvidia,gp10b"; 898 reg = <0x0 0x17000000 0x0 0x1000000>, 899 <0x0 0x18000000 0x0 0x1000000>; 900 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 901 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 902 interrupt-names = "stall", "nonstall"; 903 904 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 905 <&bpmp TEGRA186_CLK_GPU>; 906 clock-names = "gpu", "pwr"; 907 resets = <&bpmp TEGRA186_RESET_GPU>; 908 reset-names = "gpu"; 909 status = "disabled"; 910 911 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 912 }; 913 914 sysram@30000000 { 915 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 916 reg = <0x0 0x30000000 0x0 0x50000>; 917 #address-cells = <2>; 918 #size-cells = <2>; 919 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 920 921 cpu_bpmp_tx: shmem@4e000 { 922 compatible = "nvidia,tegra186-bpmp-shmem"; 923 reg = <0x0 0x4e000 0x0 0x1000>; 924 label = "cpu-bpmp-tx"; 925 pool; 926 }; 927 928 cpu_bpmp_rx: shmem@4f000 { 929 compatible = "nvidia,tegra186-bpmp-shmem"; 930 reg = <0x0 0x4f000 0x0 0x1000>; 931 label = "cpu-bpmp-rx"; 932 pool; 933 }; 934 }; 935 936 cpus { 937 #address-cells = <1>; 938 #size-cells = <0>; 939 940 cpu@0 { 941 compatible = "nvidia,tegra186-denver", "arm,armv8"; 942 device_type = "cpu"; 943 reg = <0x000>; 944 }; 945 946 cpu@1 { 947 compatible = "nvidia,tegra186-denver", "arm,armv8"; 948 device_type = "cpu"; 949 reg = <0x001>; 950 }; 951 952 cpu@2 { 953 compatible = "arm,cortex-a57", "arm,armv8"; 954 device_type = "cpu"; 955 reg = <0x100>; 956 }; 957 958 cpu@3 { 959 compatible = "arm,cortex-a57", "arm,armv8"; 960 device_type = "cpu"; 961 reg = <0x101>; 962 }; 963 964 cpu@4 { 965 compatible = "arm,cortex-a57", "arm,armv8"; 966 device_type = "cpu"; 967 reg = <0x102>; 968 }; 969 970 cpu@5 { 971 compatible = "arm,cortex-a57", "arm,armv8"; 972 device_type = "cpu"; 973 reg = <0x103>; 974 }; 975 }; 976 977 bpmp: bpmp { 978 compatible = "nvidia,tegra186-bpmp"; 979 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 980 TEGRA_HSP_DB_MASTER_BPMP>; 981 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 982 #clock-cells = <1>; 983 #reset-cells = <1>; 984 #power-domain-cells = <1>; 985 986 bpmp_i2c: i2c { 987 compatible = "nvidia,tegra186-bpmp-i2c"; 988 nvidia,bpmp-bus-id = <5>; 989 #address-cells = <1>; 990 #size-cells = <0>; 991 status = "disabled"; 992 }; 993 994 bpmp_thermal: thermal { 995 compatible = "nvidia,tegra186-bpmp-thermal"; 996 #thermal-sensor-cells = <1>; 997 }; 998 }; 999 1000 thermal-zones { 1001 a57 { 1002 polling-delay = <0>; 1003 polling-delay-passive = <1000>; 1004 1005 thermal-sensors = 1006 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 1007 1008 trips { 1009 critical { 1010 temperature = <101000>; 1011 hysteresis = <0>; 1012 type = "critical"; 1013 }; 1014 }; 1015 1016 cooling-maps { 1017 }; 1018 }; 1019 1020 denver { 1021 polling-delay = <0>; 1022 polling-delay-passive = <1000>; 1023 1024 thermal-sensors = 1025 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 1026 1027 trips { 1028 critical { 1029 temperature = <101000>; 1030 hysteresis = <0>; 1031 type = "critical"; 1032 }; 1033 }; 1034 1035 cooling-maps { 1036 }; 1037 }; 1038 1039 gpu { 1040 polling-delay = <0>; 1041 polling-delay-passive = <1000>; 1042 1043 thermal-sensors = 1044 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 1045 1046 trips { 1047 critical { 1048 temperature = <101000>; 1049 hysteresis = <0>; 1050 type = "critical"; 1051 }; 1052 }; 1053 1054 cooling-maps { 1055 }; 1056 }; 1057 1058 pll { 1059 polling-delay = <0>; 1060 polling-delay-passive = <1000>; 1061 1062 thermal-sensors = 1063 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 1064 1065 trips { 1066 critical { 1067 temperature = <101000>; 1068 hysteresis = <0>; 1069 type = "critical"; 1070 }; 1071 }; 1072 1073 cooling-maps { 1074 }; 1075 }; 1076 1077 always_on { 1078 polling-delay = <0>; 1079 polling-delay-passive = <1000>; 1080 1081 thermal-sensors = 1082 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 1083 1084 trips { 1085 critical { 1086 temperature = <101000>; 1087 hysteresis = <0>; 1088 type = "critical"; 1089 }; 1090 }; 1091 1092 cooling-maps { 1093 }; 1094 }; 1095 }; 1096 1097 timer { 1098 compatible = "arm,armv8-timer"; 1099 interrupts = <GIC_PPI 13 1100 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1101 <GIC_PPI 14 1102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1103 <GIC_PPI 11 1104 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1105 <GIC_PPI 10 1106 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1107 interrupt-parent = <&gic>; 1108 }; 1109}; 1110