1#include <dt-bindings/clock/tegra186-clock.h> 2#include <dt-bindings/gpio/tegra186-gpio.h> 3#include <dt-bindings/interrupt-controller/arm-gic.h> 4#include <dt-bindings/mailbox/tegra186-hsp.h> 5#include <dt-bindings/power/tegra186-powergate.h> 6#include <dt-bindings/reset/tegra186-reset.h> 7 8/ { 9 compatible = "nvidia,tegra186"; 10 interrupt-parent = <&gic>; 11 #address-cells = <2>; 12 #size-cells = <2>; 13 14 gpio: gpio@2200000 { 15 compatible = "nvidia,tegra186-gpio"; 16 reg-names = "security", "gpio"; 17 reg = <0x0 0x2200000 0x0 0x10000>, 18 <0x0 0x2210000 0x0 0x10000>; 19 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 20 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 21 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 22 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 23 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 24 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 25 #interrupt-cells = <2>; 26 interrupt-controller; 27 #gpio-cells = <2>; 28 gpio-controller; 29 }; 30 31 ethernet@2490000 { 32 compatible = "nvidia,tegra186-eqos", 33 "snps,dwc-qos-ethernet-4.10"; 34 reg = <0x0 0x02490000 0x0 0x10000>; 35 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 36 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 37 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 38 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 39 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 40 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 41 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 42 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 43 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 44 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 45 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 46 <&bpmp TEGRA186_CLK_EQOS_AXI>, 47 <&bpmp TEGRA186_CLK_EQOS_RX>, 48 <&bpmp TEGRA186_CLK_EQOS_TX>, 49 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 50 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 51 resets = <&bpmp TEGRA186_RESET_EQOS>; 52 reset-names = "eqos"; 53 status = "disabled"; 54 55 snps,write-requests = <1>; 56 snps,read-requests = <3>; 57 snps,burst-map = <0x7>; 58 snps,txpbl = <32>; 59 snps,rxpbl = <8>; 60 }; 61 62 uarta: serial@3100000 { 63 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 64 reg = <0x0 0x03100000 0x0 0x40>; 65 reg-shift = <2>; 66 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 67 clocks = <&bpmp TEGRA186_CLK_UARTA>; 68 clock-names = "serial"; 69 resets = <&bpmp TEGRA186_RESET_UARTA>; 70 reset-names = "serial"; 71 status = "disabled"; 72 }; 73 74 uartb: serial@3110000 { 75 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 76 reg = <0x0 0x03110000 0x0 0x40>; 77 reg-shift = <2>; 78 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 79 clocks = <&bpmp TEGRA186_CLK_UARTB>; 80 clock-names = "serial"; 81 resets = <&bpmp TEGRA186_RESET_UARTB>; 82 reset-names = "serial"; 83 status = "disabled"; 84 }; 85 86 uartd: serial@3130000 { 87 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 88 reg = <0x0 0x03130000 0x0 0x40>; 89 reg-shift = <2>; 90 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 91 clocks = <&bpmp TEGRA186_CLK_UARTD>; 92 clock-names = "serial"; 93 resets = <&bpmp TEGRA186_RESET_UARTD>; 94 reset-names = "serial"; 95 status = "disabled"; 96 }; 97 98 uarte: serial@3140000 { 99 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 100 reg = <0x0 0x03140000 0x0 0x40>; 101 reg-shift = <2>; 102 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 103 clocks = <&bpmp TEGRA186_CLK_UARTE>; 104 clock-names = "serial"; 105 resets = <&bpmp TEGRA186_RESET_UARTE>; 106 reset-names = "serial"; 107 status = "disabled"; 108 }; 109 110 uartf: serial@3150000 { 111 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 112 reg = <0x0 0x03150000 0x0 0x40>; 113 reg-shift = <2>; 114 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 115 clocks = <&bpmp TEGRA186_CLK_UARTF>; 116 clock-names = "serial"; 117 resets = <&bpmp TEGRA186_RESET_UARTF>; 118 reset-names = "serial"; 119 status = "disabled"; 120 }; 121 122 gen1_i2c: i2c@3160000 { 123 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 124 reg = <0x0 0x03160000 0x0 0x10000>; 125 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 126 #address-cells = <1>; 127 #size-cells = <0>; 128 clocks = <&bpmp TEGRA186_CLK_I2C1>; 129 clock-names = "div-clk"; 130 resets = <&bpmp TEGRA186_RESET_I2C1>; 131 reset-names = "i2c"; 132 status = "disabled"; 133 }; 134 135 cam_i2c: i2c@3180000 { 136 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 137 reg = <0x0 0x03180000 0x0 0x10000>; 138 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 139 #address-cells = <1>; 140 #size-cells = <0>; 141 clocks = <&bpmp TEGRA186_CLK_I2C3>; 142 clock-names = "div-clk"; 143 resets = <&bpmp TEGRA186_RESET_I2C3>; 144 reset-names = "i2c"; 145 status = "disabled"; 146 }; 147 148 /* shares pads with dpaux1 */ 149 dp_aux_ch1_i2c: i2c@3190000 { 150 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 151 reg = <0x0 0x03190000 0x0 0x10000>; 152 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 153 #address-cells = <1>; 154 #size-cells = <0>; 155 clocks = <&bpmp TEGRA186_CLK_I2C4>; 156 clock-names = "div-clk"; 157 resets = <&bpmp TEGRA186_RESET_I2C4>; 158 reset-names = "i2c"; 159 status = "disabled"; 160 }; 161 162 /* controlled by BPMP, should not be enabled */ 163 pwr_i2c: i2c@31a0000 { 164 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 165 reg = <0x0 0x031a0000 0x0 0x10000>; 166 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 167 #address-cells = <1>; 168 #size-cells = <0>; 169 clocks = <&bpmp TEGRA186_CLK_I2C5>; 170 clock-names = "div-clk"; 171 resets = <&bpmp TEGRA186_RESET_I2C5>; 172 reset-names = "i2c"; 173 status = "disabled"; 174 }; 175 176 /* shares pads with dpaux0 */ 177 dp_aux_ch0_i2c: i2c@31b0000 { 178 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 179 reg = <0x0 0x031b0000 0x0 0x10000>; 180 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 181 #address-cells = <1>; 182 #size-cells = <0>; 183 clocks = <&bpmp TEGRA186_CLK_I2C6>; 184 clock-names = "div-clk"; 185 resets = <&bpmp TEGRA186_RESET_I2C6>; 186 reset-names = "i2c"; 187 status = "disabled"; 188 }; 189 190 gen7_i2c: i2c@31c0000 { 191 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 192 reg = <0x0 0x031c0000 0x0 0x10000>; 193 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 194 #address-cells = <1>; 195 #size-cells = <0>; 196 clocks = <&bpmp TEGRA186_CLK_I2C7>; 197 clock-names = "div-clk"; 198 resets = <&bpmp TEGRA186_RESET_I2C7>; 199 reset-names = "i2c"; 200 status = "disabled"; 201 }; 202 203 gen9_i2c: i2c@31e0000 { 204 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 205 reg = <0x0 0x031e0000 0x0 0x10000>; 206 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 207 #address-cells = <1>; 208 #size-cells = <0>; 209 clocks = <&bpmp TEGRA186_CLK_I2C9>; 210 clock-names = "div-clk"; 211 resets = <&bpmp TEGRA186_RESET_I2C9>; 212 reset-names = "i2c"; 213 status = "disabled"; 214 }; 215 216 sdmmc1: sdhci@3400000 { 217 compatible = "nvidia,tegra186-sdhci"; 218 reg = <0x0 0x03400000 0x0 0x10000>; 219 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 220 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 221 clock-names = "sdhci"; 222 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 223 reset-names = "sdhci"; 224 status = "disabled"; 225 }; 226 227 sdmmc2: sdhci@3420000 { 228 compatible = "nvidia,tegra186-sdhci"; 229 reg = <0x0 0x03420000 0x0 0x10000>; 230 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 232 clock-names = "sdhci"; 233 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 234 reset-names = "sdhci"; 235 status = "disabled"; 236 }; 237 238 sdmmc3: sdhci@3440000 { 239 compatible = "nvidia,tegra186-sdhci"; 240 reg = <0x0 0x03440000 0x0 0x10000>; 241 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 243 clock-names = "sdhci"; 244 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 245 reset-names = "sdhci"; 246 status = "disabled"; 247 }; 248 249 sdmmc4: sdhci@3460000 { 250 compatible = "nvidia,tegra186-sdhci"; 251 reg = <0x0 0x03460000 0x0 0x10000>; 252 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 254 clock-names = "sdhci"; 255 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 256 reset-names = "sdhci"; 257 status = "disabled"; 258 }; 259 260 gic: interrupt-controller@3881000 { 261 compatible = "arm,gic-400"; 262 #interrupt-cells = <3>; 263 interrupt-controller; 264 reg = <0x0 0x03881000 0x0 0x1000>, 265 <0x0 0x03882000 0x0 0x2000>; 266 interrupts = <GIC_PPI 9 267 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 268 interrupt-parent = <&gic>; 269 }; 270 271 hsp_top0: hsp@3c00000 { 272 compatible = "nvidia,tegra186-hsp"; 273 reg = <0x0 0x03c00000 0x0 0xa0000>; 274 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 275 interrupt-names = "doorbell"; 276 #mbox-cells = <2>; 277 status = "disabled"; 278 }; 279 280 gen2_i2c: i2c@c240000 { 281 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 282 reg = <0x0 0x0c240000 0x0 0x10000>; 283 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 clocks = <&bpmp TEGRA186_CLK_I2C2>; 287 clock-names = "div-clk"; 288 resets = <&bpmp TEGRA186_RESET_I2C2>; 289 reset-names = "i2c"; 290 status = "disabled"; 291 }; 292 293 gen8_i2c: i2c@c250000 { 294 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 295 reg = <0x0 0x0c250000 0x0 0x10000>; 296 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 clocks = <&bpmp TEGRA186_CLK_I2C8>; 300 clock-names = "div-clk"; 301 resets = <&bpmp TEGRA186_RESET_I2C8>; 302 reset-names = "i2c"; 303 status = "disabled"; 304 }; 305 306 uartc: serial@c280000 { 307 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 308 reg = <0x0 0x0c280000 0x0 0x40>; 309 reg-shift = <2>; 310 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&bpmp TEGRA186_CLK_UARTC>; 312 clock-names = "serial"; 313 resets = <&bpmp TEGRA186_RESET_UARTC>; 314 reset-names = "serial"; 315 status = "disabled"; 316 }; 317 318 uartg: serial@c290000 { 319 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 320 reg = <0x0 0x0c290000 0x0 0x40>; 321 reg-shift = <2>; 322 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&bpmp TEGRA186_CLK_UARTG>; 324 clock-names = "serial"; 325 resets = <&bpmp TEGRA186_RESET_UARTG>; 326 reset-names = "serial"; 327 status = "disabled"; 328 }; 329 330 gpio_aon: gpio@c2f0000 { 331 compatible = "nvidia,tegra186-gpio-aon"; 332 reg-names = "security", "gpio"; 333 reg = <0x0 0xc2f0000 0x0 0x1000>, 334 <0x0 0xc2f1000 0x0 0x1000>; 335 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 336 gpio-controller; 337 #gpio-cells = <2>; 338 interrupt-controller; 339 #interrupt-cells = <2>; 340 }; 341 342 pmc@c360000 { 343 compatible = "nvidia,tegra186-pmc"; 344 reg = <0 0x0c360000 0 0x10000>, 345 <0 0x0c370000 0 0x10000>, 346 <0 0x0c380000 0 0x10000>, 347 <0 0x0c390000 0 0x10000>; 348 reg-names = "pmc", "wake", "aotag", "scratch"; 349 }; 350 351 ccplex@e000000 { 352 compatible = "nvidia,tegra186-ccplex-cluster"; 353 reg = <0x0 0x0e000000 0x0 0x3fffff>; 354 355 nvidia,bpmp = <&bpmp>; 356 }; 357 358 host1x@13e00000 { 359 compatible = "nvidia,tegra186-host1x", "simple-bus"; 360 reg = <0x0 0x13e00000 0x0 0x10000>, 361 <0x0 0x13e10000 0x0 0x10000>; 362 reg-names = "hypervisor", "vm"; 363 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 366 clock-names = "host1x"; 367 resets = <&bpmp TEGRA186_RESET_HOST1X>; 368 reset-names = "host1x"; 369 370 #address-cells = <1>; 371 #size-cells = <1>; 372 373 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 374 375 vic@15340000 { 376 compatible = "nvidia,tegra186-vic"; 377 reg = <0x15340000 0x40000>; 378 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&bpmp TEGRA186_CLK_VIC>; 380 clock-names = "vic"; 381 resets = <&bpmp TEGRA186_RESET_VIC>; 382 reset-names = "vic"; 383 384 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 385 }; 386 }; 387 388 gpu@17000000 { 389 compatible = "nvidia,gp10b"; 390 reg = <0x0 0x17000000 0x0 0x1000000>, 391 <0x0 0x18000000 0x0 0x1000000>; 392 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 393 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 394 interrupt-names = "stall", "nonstall"; 395 396 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 397 <&bpmp TEGRA186_CLK_GPU>; 398 clock-names = "gpu", "pwr"; 399 resets = <&bpmp TEGRA186_RESET_GPU>; 400 reset-names = "gpu"; 401 status = "disabled"; 402 403 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 404 }; 405 406 sysram@30000000 { 407 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 408 reg = <0x0 0x30000000 0x0 0x50000>; 409 #address-cells = <2>; 410 #size-cells = <2>; 411 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 412 413 cpu_bpmp_tx: shmem@4e000 { 414 compatible = "nvidia,tegra186-bpmp-shmem"; 415 reg = <0x0 0x4e000 0x0 0x1000>; 416 label = "cpu-bpmp-tx"; 417 pool; 418 }; 419 420 cpu_bpmp_rx: shmem@4f000 { 421 compatible = "nvidia,tegra186-bpmp-shmem"; 422 reg = <0x0 0x4f000 0x0 0x1000>; 423 label = "cpu-bpmp-rx"; 424 pool; 425 }; 426 }; 427 428 cpus { 429 #address-cells = <1>; 430 #size-cells = <0>; 431 432 cpu@0 { 433 compatible = "nvidia,tegra186-denver", "arm,armv8"; 434 device_type = "cpu"; 435 reg = <0x000>; 436 }; 437 438 cpu@1 { 439 compatible = "nvidia,tegra186-denver", "arm,armv8"; 440 device_type = "cpu"; 441 reg = <0x001>; 442 }; 443 444 cpu@2 { 445 compatible = "arm,cortex-a57", "arm,armv8"; 446 device_type = "cpu"; 447 reg = <0x100>; 448 }; 449 450 cpu@3 { 451 compatible = "arm,cortex-a57", "arm,armv8"; 452 device_type = "cpu"; 453 reg = <0x101>; 454 }; 455 456 cpu@4 { 457 compatible = "arm,cortex-a57", "arm,armv8"; 458 device_type = "cpu"; 459 reg = <0x102>; 460 }; 461 462 cpu@5 { 463 compatible = "arm,cortex-a57", "arm,armv8"; 464 device_type = "cpu"; 465 reg = <0x103>; 466 }; 467 }; 468 469 bpmp: bpmp { 470 compatible = "nvidia,tegra186-bpmp"; 471 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 472 TEGRA_HSP_DB_MASTER_BPMP>; 473 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 474 #clock-cells = <1>; 475 #reset-cells = <1>; 476 #power-domain-cells = <1>; 477 478 bpmp_i2c: i2c { 479 compatible = "nvidia,tegra186-bpmp-i2c"; 480 nvidia,bpmp-bus-id = <5>; 481 #address-cells = <1>; 482 #size-cells = <0>; 483 status = "disabled"; 484 }; 485 }; 486 487 timer { 488 compatible = "arm,armv8-timer"; 489 interrupts = <GIC_PPI 13 490 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 491 <GIC_PPI 14 492 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 493 <GIC_PPI 11 494 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 495 <GIC_PPI 10 496 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 497 interrupt-parent = <&gic>; 498 }; 499}; 500