1#include <dt-bindings/clock/tegra186-clock.h> 2#include <dt-bindings/gpio/tegra186-gpio.h> 3#include <dt-bindings/interrupt-controller/arm-gic.h> 4#include <dt-bindings/mailbox/tegra186-hsp.h> 5#include <dt-bindings/reset/tegra186-reset.h> 6 7/ { 8 compatible = "nvidia,tegra186"; 9 interrupt-parent = <&gic>; 10 #address-cells = <2>; 11 #size-cells = <2>; 12 13 gpio: gpio@2200000 { 14 compatible = "nvidia,tegra186-gpio"; 15 reg-names = "security", "gpio"; 16 reg = <0x0 0x2200000 0x0 0x10000>, 17 <0x0 0x2210000 0x0 0x10000>; 18 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 19 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 20 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 21 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 22 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 23 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 24 #interrupt-cells = <2>; 25 interrupt-controller; 26 #gpio-cells = <2>; 27 gpio-controller; 28 }; 29 30 ethernet@2490000 { 31 compatible = "nvidia,tegra186-eqos", 32 "snps,dwc-qos-ethernet-4.10"; 33 reg = <0x0 0x02490000 0x0 0x10000>; 34 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 35 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 36 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 37 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 38 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 39 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 40 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 41 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 42 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 43 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 44 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 45 <&bpmp TEGRA186_CLK_EQOS_AXI>, 46 <&bpmp TEGRA186_CLK_EQOS_RX>, 47 <&bpmp TEGRA186_CLK_EQOS_TX>, 48 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 49 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 50 resets = <&bpmp TEGRA186_RESET_EQOS>; 51 reset-names = "eqos"; 52 status = "disabled"; 53 54 snps,write-requests = <1>; 55 snps,read-requests = <3>; 56 snps,burst-map = <0x7>; 57 snps,txpbl = <32>; 58 snps,rxpbl = <8>; 59 }; 60 61 uarta: serial@3100000 { 62 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 63 reg = <0x0 0x03100000 0x0 0x40>; 64 reg-shift = <2>; 65 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 66 clocks = <&bpmp TEGRA186_CLK_UARTA>; 67 clock-names = "serial"; 68 resets = <&bpmp TEGRA186_RESET_UARTA>; 69 reset-names = "serial"; 70 status = "disabled"; 71 }; 72 73 uartb: serial@3110000 { 74 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 75 reg = <0x0 0x03110000 0x0 0x40>; 76 reg-shift = <2>; 77 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 78 clocks = <&bpmp TEGRA186_CLK_UARTB>; 79 clock-names = "serial"; 80 resets = <&bpmp TEGRA186_RESET_UARTB>; 81 reset-names = "serial"; 82 status = "disabled"; 83 }; 84 85 uartd: serial@3130000 { 86 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 87 reg = <0x0 0x03130000 0x0 0x40>; 88 reg-shift = <2>; 89 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 90 clocks = <&bpmp TEGRA186_CLK_UARTD>; 91 clock-names = "serial"; 92 resets = <&bpmp TEGRA186_RESET_UARTD>; 93 reset-names = "serial"; 94 status = "disabled"; 95 }; 96 97 uarte: serial@3140000 { 98 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 99 reg = <0x0 0x03140000 0x0 0x40>; 100 reg-shift = <2>; 101 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 102 clocks = <&bpmp TEGRA186_CLK_UARTE>; 103 clock-names = "serial"; 104 resets = <&bpmp TEGRA186_RESET_UARTE>; 105 reset-names = "serial"; 106 status = "disabled"; 107 }; 108 109 uartf: serial@3150000 { 110 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 111 reg = <0x0 0x03150000 0x0 0x40>; 112 reg-shift = <2>; 113 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 114 clocks = <&bpmp TEGRA186_CLK_UARTF>; 115 clock-names = "serial"; 116 resets = <&bpmp TEGRA186_RESET_UARTF>; 117 reset-names = "serial"; 118 status = "disabled"; 119 }; 120 121 gen1_i2c: i2c@3160000 { 122 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 123 reg = <0x0 0x03160000 0x0 0x10000>; 124 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 125 #address-cells = <1>; 126 #size-cells = <0>; 127 clocks = <&bpmp TEGRA186_CLK_I2C1>; 128 clock-names = "div-clk"; 129 resets = <&bpmp TEGRA186_RESET_I2C1>; 130 reset-names = "i2c"; 131 status = "disabled"; 132 }; 133 134 cam_i2c: i2c@3180000 { 135 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 136 reg = <0x0 0x03180000 0x0 0x10000>; 137 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 138 #address-cells = <1>; 139 #size-cells = <0>; 140 clocks = <&bpmp TEGRA186_CLK_I2C3>; 141 clock-names = "div-clk"; 142 resets = <&bpmp TEGRA186_RESET_I2C3>; 143 reset-names = "i2c"; 144 status = "disabled"; 145 }; 146 147 /* shares pads with dpaux1 */ 148 dp_aux_ch1_i2c: i2c@3190000 { 149 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 150 reg = <0x0 0x03190000 0x0 0x10000>; 151 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 152 #address-cells = <1>; 153 #size-cells = <0>; 154 clocks = <&bpmp TEGRA186_CLK_I2C4>; 155 clock-names = "div-clk"; 156 resets = <&bpmp TEGRA186_RESET_I2C4>; 157 reset-names = "i2c"; 158 status = "disabled"; 159 }; 160 161 /* controlled by BPMP, should not be enabled */ 162 pwr_i2c: i2c@31a0000 { 163 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 164 reg = <0x0 0x031a0000 0x0 0x10000>; 165 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 166 #address-cells = <1>; 167 #size-cells = <0>; 168 clocks = <&bpmp TEGRA186_CLK_I2C5>; 169 clock-names = "div-clk"; 170 resets = <&bpmp TEGRA186_RESET_I2C5>; 171 reset-names = "i2c"; 172 status = "disabled"; 173 }; 174 175 /* shares pads with dpaux0 */ 176 dp_aux_ch0_i2c: i2c@31b0000 { 177 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 178 reg = <0x0 0x031b0000 0x0 0x10000>; 179 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 180 #address-cells = <1>; 181 #size-cells = <0>; 182 clocks = <&bpmp TEGRA186_CLK_I2C6>; 183 clock-names = "div-clk"; 184 resets = <&bpmp TEGRA186_RESET_I2C6>; 185 reset-names = "i2c"; 186 status = "disabled"; 187 }; 188 189 gen7_i2c: i2c@31c0000 { 190 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 191 reg = <0x0 0x031c0000 0x0 0x10000>; 192 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 193 #address-cells = <1>; 194 #size-cells = <0>; 195 clocks = <&bpmp TEGRA186_CLK_I2C7>; 196 clock-names = "div-clk"; 197 resets = <&bpmp TEGRA186_RESET_I2C7>; 198 reset-names = "i2c"; 199 status = "disabled"; 200 }; 201 202 gen9_i2c: i2c@31e0000 { 203 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 204 reg = <0x0 0x031e0000 0x0 0x10000>; 205 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 206 #address-cells = <1>; 207 #size-cells = <0>; 208 clocks = <&bpmp TEGRA186_CLK_I2C9>; 209 clock-names = "div-clk"; 210 resets = <&bpmp TEGRA186_RESET_I2C9>; 211 reset-names = "i2c"; 212 status = "disabled"; 213 }; 214 215 sdmmc1: sdhci@3400000 { 216 compatible = "nvidia,tegra186-sdhci"; 217 reg = <0x0 0x03400000 0x0 0x10000>; 218 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 219 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 220 clock-names = "sdhci"; 221 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 222 reset-names = "sdhci"; 223 status = "disabled"; 224 }; 225 226 sdmmc2: sdhci@3420000 { 227 compatible = "nvidia,tegra186-sdhci"; 228 reg = <0x0 0x03420000 0x0 0x10000>; 229 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 230 clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 231 clock-names = "sdhci"; 232 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 233 reset-names = "sdhci"; 234 status = "disabled"; 235 }; 236 237 sdmmc3: sdhci@3440000 { 238 compatible = "nvidia,tegra186-sdhci"; 239 reg = <0x0 0x03440000 0x0 0x10000>; 240 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 241 clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 242 clock-names = "sdhci"; 243 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 244 reset-names = "sdhci"; 245 status = "disabled"; 246 }; 247 248 sdmmc4: sdhci@3460000 { 249 compatible = "nvidia,tegra186-sdhci"; 250 reg = <0x0 0x03460000 0x0 0x10000>; 251 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 253 clock-names = "sdhci"; 254 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 255 reset-names = "sdhci"; 256 status = "disabled"; 257 }; 258 259 gic: interrupt-controller@3881000 { 260 compatible = "arm,gic-400"; 261 #interrupt-cells = <3>; 262 interrupt-controller; 263 reg = <0x0 0x03881000 0x0 0x1000>, 264 <0x0 0x03882000 0x0 0x2000>; 265 interrupts = <GIC_PPI 9 266 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 267 interrupt-parent = <&gic>; 268 }; 269 270 hsp_top0: hsp@3c00000 { 271 compatible = "nvidia,tegra186-hsp"; 272 reg = <0x0 0x03c00000 0x0 0xa0000>; 273 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 274 interrupt-names = "doorbell"; 275 #mbox-cells = <2>; 276 status = "disabled"; 277 }; 278 279 gen2_i2c: i2c@c240000 { 280 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 281 reg = <0x0 0x0c240000 0x0 0x10000>; 282 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 283 #address-cells = <1>; 284 #size-cells = <0>; 285 clocks = <&bpmp TEGRA186_CLK_I2C2>; 286 clock-names = "div-clk"; 287 resets = <&bpmp TEGRA186_RESET_I2C2>; 288 reset-names = "i2c"; 289 status = "disabled"; 290 }; 291 292 gen8_i2c: i2c@c250000 { 293 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 294 reg = <0x0 0x0c250000 0x0 0x10000>; 295 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 clocks = <&bpmp TEGRA186_CLK_I2C8>; 299 clock-names = "div-clk"; 300 resets = <&bpmp TEGRA186_RESET_I2C8>; 301 reset-names = "i2c"; 302 status = "disabled"; 303 }; 304 305 uartc: serial@c280000 { 306 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 307 reg = <0x0 0x0c280000 0x0 0x40>; 308 reg-shift = <2>; 309 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&bpmp TEGRA186_CLK_UARTC>; 311 clock-names = "serial"; 312 resets = <&bpmp TEGRA186_RESET_UARTC>; 313 reset-names = "serial"; 314 status = "disabled"; 315 }; 316 317 uartg: serial@c290000 { 318 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 319 reg = <0x0 0x0c290000 0x0 0x40>; 320 reg-shift = <2>; 321 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&bpmp TEGRA186_CLK_UARTG>; 323 clock-names = "serial"; 324 resets = <&bpmp TEGRA186_RESET_UARTG>; 325 reset-names = "serial"; 326 status = "disabled"; 327 }; 328 329 gpio_aon: gpio@c2f0000 { 330 compatible = "nvidia,tegra186-gpio-aon"; 331 reg-names = "security", "gpio"; 332 reg = <0x0 0xc2f0000 0x0 0x1000>, 333 <0x0 0xc2f1000 0x0 0x1000>; 334 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 335 gpio-controller; 336 #gpio-cells = <2>; 337 interrupt-controller; 338 #interrupt-cells = <2>; 339 }; 340 341 pmc@c360000 { 342 compatible = "nvidia,tegra186-pmc"; 343 reg = <0 0x0c360000 0 0x10000>, 344 <0 0x0c370000 0 0x10000>, 345 <0 0x0c380000 0 0x10000>, 346 <0 0x0c390000 0 0x10000>; 347 reg-names = "pmc", "wake", "aotag", "scratch"; 348 }; 349 350 sysram@30000000 { 351 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 352 reg = <0x0 0x30000000 0x0 0x50000>; 353 #address-cells = <2>; 354 #size-cells = <2>; 355 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 356 357 cpu_bpmp_tx: shmem@4e000 { 358 compatible = "nvidia,tegra186-bpmp-shmem"; 359 reg = <0x0 0x4e000 0x0 0x1000>; 360 label = "cpu-bpmp-tx"; 361 pool; 362 }; 363 364 cpu_bpmp_rx: shmem@4f000 { 365 compatible = "nvidia,tegra186-bpmp-shmem"; 366 reg = <0x0 0x4f000 0x0 0x1000>; 367 label = "cpu-bpmp-rx"; 368 pool; 369 }; 370 }; 371 372 cpus { 373 #address-cells = <1>; 374 #size-cells = <0>; 375 376 cpu@0 { 377 compatible = "nvidia,tegra186-denver", "arm,armv8"; 378 device_type = "cpu"; 379 reg = <0x000>; 380 }; 381 382 cpu@1 { 383 compatible = "nvidia,tegra186-denver", "arm,armv8"; 384 device_type = "cpu"; 385 reg = <0x001>; 386 }; 387 388 cpu@2 { 389 compatible = "arm,cortex-a57", "arm,armv8"; 390 device_type = "cpu"; 391 reg = <0x100>; 392 }; 393 394 cpu@3 { 395 compatible = "arm,cortex-a57", "arm,armv8"; 396 device_type = "cpu"; 397 reg = <0x101>; 398 }; 399 400 cpu@4 { 401 compatible = "arm,cortex-a57", "arm,armv8"; 402 device_type = "cpu"; 403 reg = <0x102>; 404 }; 405 406 cpu@5 { 407 compatible = "arm,cortex-a57", "arm,armv8"; 408 device_type = "cpu"; 409 reg = <0x103>; 410 }; 411 }; 412 413 bpmp: bpmp { 414 compatible = "nvidia,tegra186-bpmp"; 415 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 416 TEGRA_HSP_DB_MASTER_BPMP>; 417 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 418 #clock-cells = <1>; 419 #reset-cells = <1>; 420 421 bpmp_i2c: i2c { 422 compatible = "nvidia,tegra186-bpmp-i2c"; 423 nvidia,bpmp-bus-id = <5>; 424 #address-cells = <1>; 425 #size-cells = <0>; 426 status = "disabled"; 427 }; 428 }; 429 430 timer { 431 compatible = "arm,armv8-timer"; 432 interrupts = <GIC_PPI 13 433 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 434 <GIC_PPI 14 435 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 436 <GIC_PPI 11 437 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 438 <GIC_PPI 10 439 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 440 interrupt-parent = <&gic>; 441 }; 442}; 443