1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/power/tegra186-powergate.h> 8#include <dt-bindings/reset/tegra186-reset.h> 9#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 10 11/ { 12 compatible = "nvidia,tegra186"; 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 misc@100000 { 18 compatible = "nvidia,tegra186-misc"; 19 reg = <0x0 0x00100000 0x0 0xf000>, 20 <0x0 0x0010f000 0x0 0x1000>; 21 }; 22 23 gpio: gpio@2200000 { 24 compatible = "nvidia,tegra186-gpio"; 25 reg-names = "security", "gpio"; 26 reg = <0x0 0x2200000 0x0 0x10000>, 27 <0x0 0x2210000 0x0 0x10000>; 28 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 29 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 34 #interrupt-cells = <2>; 35 interrupt-controller; 36 #gpio-cells = <2>; 37 gpio-controller; 38 }; 39 40 ethernet@2490000 { 41 compatible = "nvidia,tegra186-eqos", 42 "snps,dwc-qos-ethernet-4.10"; 43 reg = <0x0 0x02490000 0x0 0x10000>; 44 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 45 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 46 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 47 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 48 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 49 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 50 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 51 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 52 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 53 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 54 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 55 <&bpmp TEGRA186_CLK_EQOS_AXI>, 56 <&bpmp TEGRA186_CLK_EQOS_RX>, 57 <&bpmp TEGRA186_CLK_EQOS_TX>, 58 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 59 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 60 resets = <&bpmp TEGRA186_RESET_EQOS>; 61 reset-names = "eqos"; 62 status = "disabled"; 63 64 snps,write-requests = <1>; 65 snps,read-requests = <3>; 66 snps,burst-map = <0x7>; 67 snps,txpbl = <32>; 68 snps,rxpbl = <8>; 69 }; 70 71 memory-controller@2c00000 { 72 compatible = "nvidia,tegra186-mc"; 73 reg = <0x0 0x02c00000 0x0 0xb0000>; 74 status = "disabled"; 75 }; 76 77 uarta: serial@3100000 { 78 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 79 reg = <0x0 0x03100000 0x0 0x40>; 80 reg-shift = <2>; 81 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 82 clocks = <&bpmp TEGRA186_CLK_UARTA>; 83 clock-names = "serial"; 84 resets = <&bpmp TEGRA186_RESET_UARTA>; 85 reset-names = "serial"; 86 status = "disabled"; 87 }; 88 89 uartb: serial@3110000 { 90 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 91 reg = <0x0 0x03110000 0x0 0x40>; 92 reg-shift = <2>; 93 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 94 clocks = <&bpmp TEGRA186_CLK_UARTB>; 95 clock-names = "serial"; 96 resets = <&bpmp TEGRA186_RESET_UARTB>; 97 reset-names = "serial"; 98 status = "disabled"; 99 }; 100 101 uartd: serial@3130000 { 102 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 103 reg = <0x0 0x03130000 0x0 0x40>; 104 reg-shift = <2>; 105 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 106 clocks = <&bpmp TEGRA186_CLK_UARTD>; 107 clock-names = "serial"; 108 resets = <&bpmp TEGRA186_RESET_UARTD>; 109 reset-names = "serial"; 110 status = "disabled"; 111 }; 112 113 uarte: serial@3140000 { 114 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 115 reg = <0x0 0x03140000 0x0 0x40>; 116 reg-shift = <2>; 117 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 118 clocks = <&bpmp TEGRA186_CLK_UARTE>; 119 clock-names = "serial"; 120 resets = <&bpmp TEGRA186_RESET_UARTE>; 121 reset-names = "serial"; 122 status = "disabled"; 123 }; 124 125 uartf: serial@3150000 { 126 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 127 reg = <0x0 0x03150000 0x0 0x40>; 128 reg-shift = <2>; 129 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 130 clocks = <&bpmp TEGRA186_CLK_UARTF>; 131 clock-names = "serial"; 132 resets = <&bpmp TEGRA186_RESET_UARTF>; 133 reset-names = "serial"; 134 status = "disabled"; 135 }; 136 137 gen1_i2c: i2c@3160000 { 138 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 139 reg = <0x0 0x03160000 0x0 0x10000>; 140 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 141 #address-cells = <1>; 142 #size-cells = <0>; 143 clocks = <&bpmp TEGRA186_CLK_I2C1>; 144 clock-names = "div-clk"; 145 resets = <&bpmp TEGRA186_RESET_I2C1>; 146 reset-names = "i2c"; 147 status = "disabled"; 148 }; 149 150 cam_i2c: i2c@3180000 { 151 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 152 reg = <0x0 0x03180000 0x0 0x10000>; 153 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 154 #address-cells = <1>; 155 #size-cells = <0>; 156 clocks = <&bpmp TEGRA186_CLK_I2C3>; 157 clock-names = "div-clk"; 158 resets = <&bpmp TEGRA186_RESET_I2C3>; 159 reset-names = "i2c"; 160 status = "disabled"; 161 }; 162 163 /* shares pads with dpaux1 */ 164 dp_aux_ch1_i2c: i2c@3190000 { 165 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 166 reg = <0x0 0x03190000 0x0 0x10000>; 167 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 clocks = <&bpmp TEGRA186_CLK_I2C4>; 171 clock-names = "div-clk"; 172 resets = <&bpmp TEGRA186_RESET_I2C4>; 173 reset-names = "i2c"; 174 status = "disabled"; 175 }; 176 177 /* controlled by BPMP, should not be enabled */ 178 pwr_i2c: i2c@31a0000 { 179 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 180 reg = <0x0 0x031a0000 0x0 0x10000>; 181 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 182 #address-cells = <1>; 183 #size-cells = <0>; 184 clocks = <&bpmp TEGRA186_CLK_I2C5>; 185 clock-names = "div-clk"; 186 resets = <&bpmp TEGRA186_RESET_I2C5>; 187 reset-names = "i2c"; 188 status = "disabled"; 189 }; 190 191 /* shares pads with dpaux0 */ 192 dp_aux_ch0_i2c: i2c@31b0000 { 193 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 194 reg = <0x0 0x031b0000 0x0 0x10000>; 195 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 196 #address-cells = <1>; 197 #size-cells = <0>; 198 clocks = <&bpmp TEGRA186_CLK_I2C6>; 199 clock-names = "div-clk"; 200 resets = <&bpmp TEGRA186_RESET_I2C6>; 201 reset-names = "i2c"; 202 status = "disabled"; 203 }; 204 205 gen7_i2c: i2c@31c0000 { 206 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 207 reg = <0x0 0x031c0000 0x0 0x10000>; 208 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 209 #address-cells = <1>; 210 #size-cells = <0>; 211 clocks = <&bpmp TEGRA186_CLK_I2C7>; 212 clock-names = "div-clk"; 213 resets = <&bpmp TEGRA186_RESET_I2C7>; 214 reset-names = "i2c"; 215 status = "disabled"; 216 }; 217 218 gen9_i2c: i2c@31e0000 { 219 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 220 reg = <0x0 0x031e0000 0x0 0x10000>; 221 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 222 #address-cells = <1>; 223 #size-cells = <0>; 224 clocks = <&bpmp TEGRA186_CLK_I2C9>; 225 clock-names = "div-clk"; 226 resets = <&bpmp TEGRA186_RESET_I2C9>; 227 reset-names = "i2c"; 228 status = "disabled"; 229 }; 230 231 sdmmc1: sdhci@3400000 { 232 compatible = "nvidia,tegra186-sdhci"; 233 reg = <0x0 0x03400000 0x0 0x10000>; 234 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 235 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 236 clock-names = "sdhci"; 237 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 238 reset-names = "sdhci"; 239 status = "disabled"; 240 }; 241 242 sdmmc2: sdhci@3420000 { 243 compatible = "nvidia,tegra186-sdhci"; 244 reg = <0x0 0x03420000 0x0 0x10000>; 245 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 247 clock-names = "sdhci"; 248 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 249 reset-names = "sdhci"; 250 status = "disabled"; 251 }; 252 253 sdmmc3: sdhci@3440000 { 254 compatible = "nvidia,tegra186-sdhci"; 255 reg = <0x0 0x03440000 0x0 0x10000>; 256 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 258 clock-names = "sdhci"; 259 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 260 reset-names = "sdhci"; 261 status = "disabled"; 262 }; 263 264 sdmmc4: sdhci@3460000 { 265 compatible = "nvidia,tegra186-sdhci"; 266 reg = <0x0 0x03460000 0x0 0x10000>; 267 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 269 clock-names = "sdhci"; 270 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 271 reset-names = "sdhci"; 272 status = "disabled"; 273 }; 274 275 fuse@3820000 { 276 compatible = "nvidia,tegra186-efuse"; 277 reg = <0x0 0x03820000 0x0 0x10000>; 278 clocks = <&bpmp TEGRA186_CLK_FUSE>; 279 clock-names = "fuse"; 280 }; 281 282 gic: interrupt-controller@3881000 { 283 compatible = "arm,gic-400"; 284 #interrupt-cells = <3>; 285 interrupt-controller; 286 reg = <0x0 0x03881000 0x0 0x1000>, 287 <0x0 0x03882000 0x0 0x2000>; 288 interrupts = <GIC_PPI 9 289 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 290 interrupt-parent = <&gic>; 291 }; 292 293 hsp_top0: hsp@3c00000 { 294 compatible = "nvidia,tegra186-hsp"; 295 reg = <0x0 0x03c00000 0x0 0xa0000>; 296 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 297 interrupt-names = "doorbell"; 298 #mbox-cells = <2>; 299 status = "disabled"; 300 }; 301 302 gen2_i2c: i2c@c240000 { 303 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 304 reg = <0x0 0x0c240000 0x0 0x10000>; 305 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 306 #address-cells = <1>; 307 #size-cells = <0>; 308 clocks = <&bpmp TEGRA186_CLK_I2C2>; 309 clock-names = "div-clk"; 310 resets = <&bpmp TEGRA186_RESET_I2C2>; 311 reset-names = "i2c"; 312 status = "disabled"; 313 }; 314 315 gen8_i2c: i2c@c250000 { 316 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 317 reg = <0x0 0x0c250000 0x0 0x10000>; 318 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 319 #address-cells = <1>; 320 #size-cells = <0>; 321 clocks = <&bpmp TEGRA186_CLK_I2C8>; 322 clock-names = "div-clk"; 323 resets = <&bpmp TEGRA186_RESET_I2C8>; 324 reset-names = "i2c"; 325 status = "disabled"; 326 }; 327 328 uartc: serial@c280000 { 329 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 330 reg = <0x0 0x0c280000 0x0 0x40>; 331 reg-shift = <2>; 332 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&bpmp TEGRA186_CLK_UARTC>; 334 clock-names = "serial"; 335 resets = <&bpmp TEGRA186_RESET_UARTC>; 336 reset-names = "serial"; 337 status = "disabled"; 338 }; 339 340 uartg: serial@c290000 { 341 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 342 reg = <0x0 0x0c290000 0x0 0x40>; 343 reg-shift = <2>; 344 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&bpmp TEGRA186_CLK_UARTG>; 346 clock-names = "serial"; 347 resets = <&bpmp TEGRA186_RESET_UARTG>; 348 reset-names = "serial"; 349 status = "disabled"; 350 }; 351 352 gpio_aon: gpio@c2f0000 { 353 compatible = "nvidia,tegra186-gpio-aon"; 354 reg-names = "security", "gpio"; 355 reg = <0x0 0xc2f0000 0x0 0x1000>, 356 <0x0 0xc2f1000 0x0 0x1000>; 357 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 358 gpio-controller; 359 #gpio-cells = <2>; 360 interrupt-controller; 361 #interrupt-cells = <2>; 362 }; 363 364 pmc@c360000 { 365 compatible = "nvidia,tegra186-pmc"; 366 reg = <0 0x0c360000 0 0x10000>, 367 <0 0x0c370000 0 0x10000>, 368 <0 0x0c380000 0 0x10000>, 369 <0 0x0c390000 0 0x10000>; 370 reg-names = "pmc", "wake", "aotag", "scratch"; 371 }; 372 373 ccplex@e000000 { 374 compatible = "nvidia,tegra186-ccplex-cluster"; 375 reg = <0x0 0x0e000000 0x0 0x3fffff>; 376 377 nvidia,bpmp = <&bpmp>; 378 }; 379 380 pcie@10003000 { 381 compatible = "nvidia,tegra186-pcie"; 382 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 383 device_type = "pci"; 384 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 385 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 386 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 387 reg-names = "pads", "afi", "cs"; 388 389 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 390 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 391 interrupt-names = "intr", "msi"; 392 393 #interrupt-cells = <1>; 394 interrupt-map-mask = <0 0 0 0>; 395 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 396 397 bus-range = <0x00 0xff>; 398 #address-cells = <3>; 399 #size-cells = <2>; 400 401 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 402 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 403 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 404 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 405 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 406 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 407 408 clocks = <&bpmp TEGRA186_CLK_AFI>, 409 <&bpmp TEGRA186_CLK_PCIE>, 410 <&bpmp TEGRA186_CLK_PLLE>; 411 clock-names = "afi", "pex", "pll_e"; 412 413 resets = <&bpmp TEGRA186_RESET_AFI>, 414 <&bpmp TEGRA186_RESET_PCIE>, 415 <&bpmp TEGRA186_RESET_PCIEXCLK>; 416 reset-names = "afi", "pex", "pcie_x"; 417 418 status = "disabled"; 419 420 pci@1,0 { 421 device_type = "pci"; 422 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 423 reg = <0x000800 0 0 0 0>; 424 status = "disabled"; 425 426 #address-cells = <3>; 427 #size-cells = <2>; 428 ranges; 429 430 nvidia,num-lanes = <2>; 431 }; 432 433 pci@2,0 { 434 device_type = "pci"; 435 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 436 reg = <0x001000 0 0 0 0>; 437 status = "disabled"; 438 439 #address-cells = <3>; 440 #size-cells = <2>; 441 ranges; 442 443 nvidia,num-lanes = <1>; 444 }; 445 446 pci@3,0 { 447 device_type = "pci"; 448 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 449 reg = <0x001800 0 0 0 0>; 450 status = "disabled"; 451 452 #address-cells = <3>; 453 #size-cells = <2>; 454 ranges; 455 456 nvidia,num-lanes = <1>; 457 }; 458 }; 459 460 smmu: iommu@12000000 { 461 compatible = "arm,mmu-500"; 462 reg = <0 0x12000000 0 0x800000>; 463 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 528 stream-match-mask = <0x7f80>; 529 #global-interrupts = <1>; 530 #iommu-cells = <1>; 531 }; 532 533 host1x@13e00000 { 534 compatible = "nvidia,tegra186-host1x", "simple-bus"; 535 reg = <0x0 0x13e00000 0x0 0x10000>, 536 <0x0 0x13e10000 0x0 0x10000>; 537 reg-names = "hypervisor", "vm"; 538 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 541 clock-names = "host1x"; 542 resets = <&bpmp TEGRA186_RESET_HOST1X>; 543 reset-names = "host1x"; 544 545 #address-cells = <1>; 546 #size-cells = <1>; 547 548 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 549 550 vic@15340000 { 551 compatible = "nvidia,tegra186-vic"; 552 reg = <0x15340000 0x40000>; 553 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 554 clocks = <&bpmp TEGRA186_CLK_VIC>; 555 clock-names = "vic"; 556 resets = <&bpmp TEGRA186_RESET_VIC>; 557 reset-names = "vic"; 558 559 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 560 }; 561 }; 562 563 gpu@17000000 { 564 compatible = "nvidia,gp10b"; 565 reg = <0x0 0x17000000 0x0 0x1000000>, 566 <0x0 0x18000000 0x0 0x1000000>; 567 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 568 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 569 interrupt-names = "stall", "nonstall"; 570 571 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 572 <&bpmp TEGRA186_CLK_GPU>; 573 clock-names = "gpu", "pwr"; 574 resets = <&bpmp TEGRA186_RESET_GPU>; 575 reset-names = "gpu"; 576 status = "disabled"; 577 578 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 579 }; 580 581 sysram@30000000 { 582 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 583 reg = <0x0 0x30000000 0x0 0x50000>; 584 #address-cells = <2>; 585 #size-cells = <2>; 586 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 587 588 cpu_bpmp_tx: shmem@4e000 { 589 compatible = "nvidia,tegra186-bpmp-shmem"; 590 reg = <0x0 0x4e000 0x0 0x1000>; 591 label = "cpu-bpmp-tx"; 592 pool; 593 }; 594 595 cpu_bpmp_rx: shmem@4f000 { 596 compatible = "nvidia,tegra186-bpmp-shmem"; 597 reg = <0x0 0x4f000 0x0 0x1000>; 598 label = "cpu-bpmp-rx"; 599 pool; 600 }; 601 }; 602 603 cpus { 604 #address-cells = <1>; 605 #size-cells = <0>; 606 607 cpu@0 { 608 compatible = "nvidia,tegra186-denver", "arm,armv8"; 609 device_type = "cpu"; 610 reg = <0x000>; 611 }; 612 613 cpu@1 { 614 compatible = "nvidia,tegra186-denver", "arm,armv8"; 615 device_type = "cpu"; 616 reg = <0x001>; 617 }; 618 619 cpu@2 { 620 compatible = "arm,cortex-a57", "arm,armv8"; 621 device_type = "cpu"; 622 reg = <0x100>; 623 }; 624 625 cpu@3 { 626 compatible = "arm,cortex-a57", "arm,armv8"; 627 device_type = "cpu"; 628 reg = <0x101>; 629 }; 630 631 cpu@4 { 632 compatible = "arm,cortex-a57", "arm,armv8"; 633 device_type = "cpu"; 634 reg = <0x102>; 635 }; 636 637 cpu@5 { 638 compatible = "arm,cortex-a57", "arm,armv8"; 639 device_type = "cpu"; 640 reg = <0x103>; 641 }; 642 }; 643 644 bpmp: bpmp { 645 compatible = "nvidia,tegra186-bpmp"; 646 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 647 TEGRA_HSP_DB_MASTER_BPMP>; 648 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 649 #clock-cells = <1>; 650 #reset-cells = <1>; 651 #power-domain-cells = <1>; 652 653 bpmp_i2c: i2c { 654 compatible = "nvidia,tegra186-bpmp-i2c"; 655 nvidia,bpmp-bus-id = <5>; 656 #address-cells = <1>; 657 #size-cells = <0>; 658 status = "disabled"; 659 }; 660 661 bpmp_thermal: thermal { 662 compatible = "nvidia,tegra186-bpmp-thermal"; 663 #thermal-sensor-cells = <1>; 664 }; 665 }; 666 667 thermal-zones { 668 a57 { 669 polling-delay = <0>; 670 polling-delay-passive = <1000>; 671 672 thermal-sensors = 673 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 674 675 trips { 676 critical { 677 temperature = <101000>; 678 hysteresis = <0>; 679 type = "critical"; 680 }; 681 }; 682 683 cooling-maps { 684 }; 685 }; 686 687 denver { 688 polling-delay = <0>; 689 polling-delay-passive = <1000>; 690 691 thermal-sensors = 692 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 693 694 trips { 695 critical { 696 temperature = <101000>; 697 hysteresis = <0>; 698 type = "critical"; 699 }; 700 }; 701 702 cooling-maps { 703 }; 704 }; 705 706 gpu { 707 polling-delay = <0>; 708 polling-delay-passive = <1000>; 709 710 thermal-sensors = 711 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 712 713 trips { 714 critical { 715 temperature = <101000>; 716 hysteresis = <0>; 717 type = "critical"; 718 }; 719 }; 720 721 cooling-maps { 722 }; 723 }; 724 725 pll { 726 polling-delay = <0>; 727 polling-delay-passive = <1000>; 728 729 thermal-sensors = 730 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 731 732 trips { 733 critical { 734 temperature = <101000>; 735 hysteresis = <0>; 736 type = "critical"; 737 }; 738 }; 739 740 cooling-maps { 741 }; 742 }; 743 744 always_on { 745 polling-delay = <0>; 746 polling-delay-passive = <1000>; 747 748 thermal-sensors = 749 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 750 751 trips { 752 critical { 753 temperature = <101000>; 754 hysteresis = <0>; 755 type = "critical"; 756 }; 757 }; 758 759 cooling-maps { 760 }; 761 }; 762 }; 763 764 timer { 765 compatible = "arm,armv8-timer"; 766 interrupts = <GIC_PPI 13 767 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 768 <GIC_PPI 14 769 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 770 <GIC_PPI 11 771 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 772 <GIC_PPI 10 773 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 774 interrupt-parent = <&gic>; 775 }; 776}; 777