1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 status = "disabled"; 64 65 snps,write-requests = <1>; 66 snps,read-requests = <3>; 67 snps,burst-map = <0x7>; 68 snps,txpbl = <32>; 69 snps,rxpbl = <8>; 70 }; 71 72 memory-controller@2c00000 { 73 compatible = "nvidia,tegra186-mc"; 74 reg = <0x0 0x02c00000 0x0 0xb0000>; 75 status = "disabled"; 76 }; 77 78 uarta: serial@3100000 { 79 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 80 reg = <0x0 0x03100000 0x0 0x40>; 81 reg-shift = <2>; 82 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 83 clocks = <&bpmp TEGRA186_CLK_UARTA>; 84 clock-names = "serial"; 85 resets = <&bpmp TEGRA186_RESET_UARTA>; 86 reset-names = "serial"; 87 status = "disabled"; 88 }; 89 90 uartb: serial@3110000 { 91 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 92 reg = <0x0 0x03110000 0x0 0x40>; 93 reg-shift = <2>; 94 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 95 clocks = <&bpmp TEGRA186_CLK_UARTB>; 96 clock-names = "serial"; 97 resets = <&bpmp TEGRA186_RESET_UARTB>; 98 reset-names = "serial"; 99 status = "disabled"; 100 }; 101 102 uartd: serial@3130000 { 103 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 104 reg = <0x0 0x03130000 0x0 0x40>; 105 reg-shift = <2>; 106 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 107 clocks = <&bpmp TEGRA186_CLK_UARTD>; 108 clock-names = "serial"; 109 resets = <&bpmp TEGRA186_RESET_UARTD>; 110 reset-names = "serial"; 111 status = "disabled"; 112 }; 113 114 uarte: serial@3140000 { 115 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 116 reg = <0x0 0x03140000 0x0 0x40>; 117 reg-shift = <2>; 118 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 119 clocks = <&bpmp TEGRA186_CLK_UARTE>; 120 clock-names = "serial"; 121 resets = <&bpmp TEGRA186_RESET_UARTE>; 122 reset-names = "serial"; 123 status = "disabled"; 124 }; 125 126 uartf: serial@3150000 { 127 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 128 reg = <0x0 0x03150000 0x0 0x40>; 129 reg-shift = <2>; 130 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&bpmp TEGRA186_CLK_UARTF>; 132 clock-names = "serial"; 133 resets = <&bpmp TEGRA186_RESET_UARTF>; 134 reset-names = "serial"; 135 status = "disabled"; 136 }; 137 138 gen1_i2c: i2c@3160000 { 139 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 140 reg = <0x0 0x03160000 0x0 0x10000>; 141 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 clocks = <&bpmp TEGRA186_CLK_I2C1>; 145 clock-names = "div-clk"; 146 resets = <&bpmp TEGRA186_RESET_I2C1>; 147 reset-names = "i2c"; 148 status = "disabled"; 149 }; 150 151 cam_i2c: i2c@3180000 { 152 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 153 reg = <0x0 0x03180000 0x0 0x10000>; 154 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 155 #address-cells = <1>; 156 #size-cells = <0>; 157 clocks = <&bpmp TEGRA186_CLK_I2C3>; 158 clock-names = "div-clk"; 159 resets = <&bpmp TEGRA186_RESET_I2C3>; 160 reset-names = "i2c"; 161 status = "disabled"; 162 }; 163 164 /* shares pads with dpaux1 */ 165 dp_aux_ch1_i2c: i2c@3190000 { 166 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 167 reg = <0x0 0x03190000 0x0 0x10000>; 168 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 169 #address-cells = <1>; 170 #size-cells = <0>; 171 clocks = <&bpmp TEGRA186_CLK_I2C4>; 172 clock-names = "div-clk"; 173 resets = <&bpmp TEGRA186_RESET_I2C4>; 174 reset-names = "i2c"; 175 status = "disabled"; 176 }; 177 178 /* controlled by BPMP, should not be enabled */ 179 pwr_i2c: i2c@31a0000 { 180 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 181 reg = <0x0 0x031a0000 0x0 0x10000>; 182 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 183 #address-cells = <1>; 184 #size-cells = <0>; 185 clocks = <&bpmp TEGRA186_CLK_I2C5>; 186 clock-names = "div-clk"; 187 resets = <&bpmp TEGRA186_RESET_I2C5>; 188 reset-names = "i2c"; 189 status = "disabled"; 190 }; 191 192 /* shares pads with dpaux0 */ 193 dp_aux_ch0_i2c: i2c@31b0000 { 194 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 195 reg = <0x0 0x031b0000 0x0 0x10000>; 196 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 clocks = <&bpmp TEGRA186_CLK_I2C6>; 200 clock-names = "div-clk"; 201 resets = <&bpmp TEGRA186_RESET_I2C6>; 202 reset-names = "i2c"; 203 status = "disabled"; 204 }; 205 206 gen7_i2c: i2c@31c0000 { 207 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 208 reg = <0x0 0x031c0000 0x0 0x10000>; 209 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 clocks = <&bpmp TEGRA186_CLK_I2C7>; 213 clock-names = "div-clk"; 214 resets = <&bpmp TEGRA186_RESET_I2C7>; 215 reset-names = "i2c"; 216 status = "disabled"; 217 }; 218 219 gen9_i2c: i2c@31e0000 { 220 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 221 reg = <0x0 0x031e0000 0x0 0x10000>; 222 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 clocks = <&bpmp TEGRA186_CLK_I2C9>; 226 clock-names = "div-clk"; 227 resets = <&bpmp TEGRA186_RESET_I2C9>; 228 reset-names = "i2c"; 229 status = "disabled"; 230 }; 231 232 sdmmc1: sdhci@3400000 { 233 compatible = "nvidia,tegra186-sdhci"; 234 reg = <0x0 0x03400000 0x0 0x10000>; 235 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 237 clock-names = "sdhci"; 238 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 239 reset-names = "sdhci"; 240 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 241 pinctrl-0 = <&sdmmc1_3v3>; 242 pinctrl-1 = <&sdmmc1_1v8>; 243 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 244 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 245 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 246 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 247 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 248 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 249 nvidia,default-tap = <0x5>; 250 nvidia,default-trim = <0xb>; 251 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 252 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 253 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 254 status = "disabled"; 255 }; 256 257 sdmmc2: sdhci@3420000 { 258 compatible = "nvidia,tegra186-sdhci"; 259 reg = <0x0 0x03420000 0x0 0x10000>; 260 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 262 clock-names = "sdhci"; 263 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 264 reset-names = "sdhci"; 265 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 266 pinctrl-0 = <&sdmmc2_3v3>; 267 pinctrl-1 = <&sdmmc2_1v8>; 268 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 269 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 270 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 271 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 272 nvidia,default-tap = <0x5>; 273 nvidia,default-trim = <0xb>; 274 status = "disabled"; 275 }; 276 277 sdmmc3: sdhci@3440000 { 278 compatible = "nvidia,tegra186-sdhci"; 279 reg = <0x0 0x03440000 0x0 0x10000>; 280 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 282 clock-names = "sdhci"; 283 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 284 reset-names = "sdhci"; 285 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 286 pinctrl-0 = <&sdmmc3_3v3>; 287 pinctrl-1 = <&sdmmc3_1v8>; 288 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 289 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 290 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 291 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 292 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 293 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 294 nvidia,default-tap = <0x5>; 295 nvidia,default-trim = <0xb>; 296 status = "disabled"; 297 }; 298 299 sdmmc4: sdhci@3460000 { 300 compatible = "nvidia,tegra186-sdhci"; 301 reg = <0x0 0x03460000 0x0 0x10000>; 302 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 303 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 304 clock-names = "sdhci"; 305 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 306 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 307 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 308 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 309 reset-names = "sdhci"; 310 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 311 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 312 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 313 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 314 nvidia,default-tap = <0x5>; 315 nvidia,default-trim = <0x9>; 316 nvidia,dqs-trim = <63>; 317 mmc-hs400-1_8v; 318 status = "disabled"; 319 }; 320 321 fuse@3820000 { 322 compatible = "nvidia,tegra186-efuse"; 323 reg = <0x0 0x03820000 0x0 0x10000>; 324 clocks = <&bpmp TEGRA186_CLK_FUSE>; 325 clock-names = "fuse"; 326 }; 327 328 gic: interrupt-controller@3881000 { 329 compatible = "arm,gic-400"; 330 #interrupt-cells = <3>; 331 interrupt-controller; 332 reg = <0x0 0x03881000 0x0 0x1000>, 333 <0x0 0x03882000 0x0 0x2000>; 334 interrupts = <GIC_PPI 9 335 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 336 interrupt-parent = <&gic>; 337 }; 338 339 hsp_top0: hsp@3c00000 { 340 compatible = "nvidia,tegra186-hsp"; 341 reg = <0x0 0x03c00000 0x0 0xa0000>; 342 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 343 interrupt-names = "doorbell"; 344 #mbox-cells = <2>; 345 status = "disabled"; 346 }; 347 348 gen2_i2c: i2c@c240000 { 349 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 350 reg = <0x0 0x0c240000 0x0 0x10000>; 351 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 352 #address-cells = <1>; 353 #size-cells = <0>; 354 clocks = <&bpmp TEGRA186_CLK_I2C2>; 355 clock-names = "div-clk"; 356 resets = <&bpmp TEGRA186_RESET_I2C2>; 357 reset-names = "i2c"; 358 status = "disabled"; 359 }; 360 361 gen8_i2c: i2c@c250000 { 362 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 363 reg = <0x0 0x0c250000 0x0 0x10000>; 364 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 365 #address-cells = <1>; 366 #size-cells = <0>; 367 clocks = <&bpmp TEGRA186_CLK_I2C8>; 368 clock-names = "div-clk"; 369 resets = <&bpmp TEGRA186_RESET_I2C8>; 370 reset-names = "i2c"; 371 status = "disabled"; 372 }; 373 374 uartc: serial@c280000 { 375 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 376 reg = <0x0 0x0c280000 0x0 0x40>; 377 reg-shift = <2>; 378 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&bpmp TEGRA186_CLK_UARTC>; 380 clock-names = "serial"; 381 resets = <&bpmp TEGRA186_RESET_UARTC>; 382 reset-names = "serial"; 383 status = "disabled"; 384 }; 385 386 uartg: serial@c290000 { 387 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 388 reg = <0x0 0x0c290000 0x0 0x40>; 389 reg-shift = <2>; 390 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 391 clocks = <&bpmp TEGRA186_CLK_UARTG>; 392 clock-names = "serial"; 393 resets = <&bpmp TEGRA186_RESET_UARTG>; 394 reset-names = "serial"; 395 status = "disabled"; 396 }; 397 398 rtc: rtc@c2a0000 { 399 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 400 reg = <0 0x0c2a0000 0 0x10000>; 401 interrupt-parent = <&pmc>; 402 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 404 clock-names = "rtc"; 405 status = "disabled"; 406 }; 407 408 gpio_aon: gpio@c2f0000 { 409 compatible = "nvidia,tegra186-gpio-aon"; 410 reg-names = "security", "gpio"; 411 reg = <0x0 0xc2f0000 0x0 0x1000>, 412 <0x0 0xc2f1000 0x0 0x1000>; 413 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 414 gpio-controller; 415 #gpio-cells = <2>; 416 interrupt-controller; 417 #interrupt-cells = <2>; 418 }; 419 420 pmc: pmc@c360000 { 421 compatible = "nvidia,tegra186-pmc"; 422 reg = <0 0x0c360000 0 0x10000>, 423 <0 0x0c370000 0 0x10000>, 424 <0 0x0c380000 0 0x10000>, 425 <0 0x0c390000 0 0x10000>; 426 reg-names = "pmc", "wake", "aotag", "scratch"; 427 428 #interrupt-cells = <2>; 429 interrupt-controller; 430 431 sdmmc1_3v3: sdmmc1-3v3 { 432 pins = "sdmmc1-hv"; 433 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 434 }; 435 436 sdmmc1_1v8: sdmmc1-1v8 { 437 pins = "sdmmc1-hv"; 438 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 439 }; 440 441 sdmmc2_3v3: sdmmc2-3v3 { 442 pins = "sdmmc2-hv"; 443 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 444 }; 445 446 sdmmc2_1v8: sdmmc2-1v8 { 447 pins = "sdmmc2-hv"; 448 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 449 }; 450 451 sdmmc3_3v3: sdmmc3-3v3 { 452 pins = "sdmmc3-hv"; 453 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 454 }; 455 456 sdmmc3_1v8: sdmmc3-1v8 { 457 pins = "sdmmc3-hv"; 458 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 459 }; 460 }; 461 462 ccplex@e000000 { 463 compatible = "nvidia,tegra186-ccplex-cluster"; 464 reg = <0x0 0x0e000000 0x0 0x3fffff>; 465 466 nvidia,bpmp = <&bpmp>; 467 }; 468 469 pcie@10003000 { 470 compatible = "nvidia,tegra186-pcie"; 471 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 472 device_type = "pci"; 473 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 474 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 475 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 476 reg-names = "pads", "afi", "cs"; 477 478 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 479 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 480 interrupt-names = "intr", "msi"; 481 482 #interrupt-cells = <1>; 483 interrupt-map-mask = <0 0 0 0>; 484 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 485 486 bus-range = <0x00 0xff>; 487 #address-cells = <3>; 488 #size-cells = <2>; 489 490 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 491 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 492 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 493 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 494 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 495 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 496 497 clocks = <&bpmp TEGRA186_CLK_AFI>, 498 <&bpmp TEGRA186_CLK_PCIE>, 499 <&bpmp TEGRA186_CLK_PLLE>; 500 clock-names = "afi", "pex", "pll_e"; 501 502 resets = <&bpmp TEGRA186_RESET_AFI>, 503 <&bpmp TEGRA186_RESET_PCIE>, 504 <&bpmp TEGRA186_RESET_PCIEXCLK>; 505 reset-names = "afi", "pex", "pcie_x"; 506 507 status = "disabled"; 508 509 pci@1,0 { 510 device_type = "pci"; 511 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 512 reg = <0x000800 0 0 0 0>; 513 status = "disabled"; 514 515 #address-cells = <3>; 516 #size-cells = <2>; 517 ranges; 518 519 nvidia,num-lanes = <2>; 520 }; 521 522 pci@2,0 { 523 device_type = "pci"; 524 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 525 reg = <0x001000 0 0 0 0>; 526 status = "disabled"; 527 528 #address-cells = <3>; 529 #size-cells = <2>; 530 ranges; 531 532 nvidia,num-lanes = <1>; 533 }; 534 535 pci@3,0 { 536 device_type = "pci"; 537 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 538 reg = <0x001800 0 0 0 0>; 539 status = "disabled"; 540 541 #address-cells = <3>; 542 #size-cells = <2>; 543 ranges; 544 545 nvidia,num-lanes = <1>; 546 }; 547 }; 548 549 smmu: iommu@12000000 { 550 compatible = "arm,mmu-500"; 551 reg = <0 0x12000000 0 0x800000>; 552 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 617 stream-match-mask = <0x7f80>; 618 #global-interrupts = <1>; 619 #iommu-cells = <1>; 620 }; 621 622 host1x@13e00000 { 623 compatible = "nvidia,tegra186-host1x", "simple-bus"; 624 reg = <0x0 0x13e00000 0x0 0x10000>, 625 <0x0 0x13e10000 0x0 0x10000>; 626 reg-names = "hypervisor", "vm"; 627 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 629 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 630 clock-names = "host1x"; 631 resets = <&bpmp TEGRA186_RESET_HOST1X>; 632 reset-names = "host1x"; 633 634 #address-cells = <1>; 635 #size-cells = <1>; 636 637 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 638 iommus = <&smmu TEGRA186_SID_HOST1X>; 639 640 dpaux1: dpaux@15040000 { 641 compatible = "nvidia,tegra186-dpaux"; 642 reg = <0x15040000 0x10000>; 643 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 645 <&bpmp TEGRA186_CLK_PLLDP>; 646 clock-names = "dpaux", "parent"; 647 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 648 reset-names = "dpaux"; 649 status = "disabled"; 650 651 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 652 653 state_dpaux1_aux: pinmux-aux { 654 groups = "dpaux-io"; 655 function = "aux"; 656 }; 657 658 state_dpaux1_i2c: pinmux-i2c { 659 groups = "dpaux-io"; 660 function = "i2c"; 661 }; 662 663 state_dpaux1_off: pinmux-off { 664 groups = "dpaux-io"; 665 function = "off"; 666 }; 667 668 i2c-bus { 669 #address-cells = <1>; 670 #size-cells = <0>; 671 }; 672 }; 673 674 display-hub@15200000 { 675 compatible = "nvidia,tegra186-display", "simple-bus"; 676 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 677 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 678 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 679 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 680 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 681 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 682 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 683 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 684 "wgrp3", "wgrp4", "wgrp5"; 685 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 686 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 687 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 688 clock-names = "disp", "dsc", "hub"; 689 status = "disabled"; 690 691 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 692 693 #address-cells = <1>; 694 #size-cells = <1>; 695 696 ranges = <0x15200000 0x15200000 0x40000>; 697 698 display@15200000 { 699 compatible = "nvidia,tegra186-dc"; 700 reg = <0x15200000 0x10000>; 701 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 703 clock-names = "dc"; 704 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 705 reset-names = "dc"; 706 707 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 708 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 709 710 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 711 nvidia,head = <0>; 712 }; 713 714 display@15210000 { 715 compatible = "nvidia,tegra186-dc"; 716 reg = <0x15210000 0x10000>; 717 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 718 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 719 clock-names = "dc"; 720 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 721 reset-names = "dc"; 722 723 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 724 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 725 726 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 727 nvidia,head = <1>; 728 }; 729 730 display@15220000 { 731 compatible = "nvidia,tegra186-dc"; 732 reg = <0x15220000 0x10000>; 733 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 734 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 735 clock-names = "dc"; 736 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 737 reset-names = "dc"; 738 739 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 740 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 741 742 nvidia,outputs = <&sor0 &sor1>; 743 nvidia,head = <2>; 744 }; 745 }; 746 747 dsia: dsi@15300000 { 748 compatible = "nvidia,tegra186-dsi"; 749 reg = <0x15300000 0x10000>; 750 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 751 clocks = <&bpmp TEGRA186_CLK_DSI>, 752 <&bpmp TEGRA186_CLK_DSIA_LP>, 753 <&bpmp TEGRA186_CLK_PLLD>; 754 clock-names = "dsi", "lp", "parent"; 755 resets = <&bpmp TEGRA186_RESET_DSI>; 756 reset-names = "dsi"; 757 status = "disabled"; 758 759 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 760 }; 761 762 vic@15340000 { 763 compatible = "nvidia,tegra186-vic"; 764 reg = <0x15340000 0x40000>; 765 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 766 clocks = <&bpmp TEGRA186_CLK_VIC>; 767 clock-names = "vic"; 768 resets = <&bpmp TEGRA186_RESET_VIC>; 769 reset-names = "vic"; 770 771 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 772 }; 773 774 dsib: dsi@15400000 { 775 compatible = "nvidia,tegra186-dsi"; 776 reg = <0x15400000 0x10000>; 777 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 778 clocks = <&bpmp TEGRA186_CLK_DSIB>, 779 <&bpmp TEGRA186_CLK_DSIB_LP>, 780 <&bpmp TEGRA186_CLK_PLLD>; 781 clock-names = "dsi", "lp", "parent"; 782 resets = <&bpmp TEGRA186_RESET_DSIB>; 783 reset-names = "dsi"; 784 status = "disabled"; 785 786 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 787 }; 788 789 sor0: sor@15540000 { 790 compatible = "nvidia,tegra186-sor"; 791 reg = <0x15540000 0x10000>; 792 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 793 clocks = <&bpmp TEGRA186_CLK_SOR0>, 794 <&bpmp TEGRA186_CLK_SOR0_OUT>, 795 <&bpmp TEGRA186_CLK_PLLD2>, 796 <&bpmp TEGRA186_CLK_PLLDP>, 797 <&bpmp TEGRA186_CLK_SOR_SAFE>, 798 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 799 clock-names = "sor", "out", "parent", "dp", "safe", 800 "pad"; 801 resets = <&bpmp TEGRA186_RESET_SOR0>; 802 reset-names = "sor"; 803 pinctrl-0 = <&state_dpaux_aux>; 804 pinctrl-1 = <&state_dpaux_i2c>; 805 pinctrl-2 = <&state_dpaux_off>; 806 pinctrl-names = "aux", "i2c", "off"; 807 status = "disabled"; 808 809 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 810 nvidia,interface = <0>; 811 }; 812 813 sor1: sor@15580000 { 814 compatible = "nvidia,tegra186-sor1"; 815 reg = <0x15580000 0x10000>; 816 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 817 clocks = <&bpmp TEGRA186_CLK_SOR1>, 818 <&bpmp TEGRA186_CLK_SOR1_OUT>, 819 <&bpmp TEGRA186_CLK_PLLD3>, 820 <&bpmp TEGRA186_CLK_PLLDP>, 821 <&bpmp TEGRA186_CLK_SOR_SAFE>, 822 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 823 clock-names = "sor", "out", "parent", "dp", "safe", 824 "pad"; 825 resets = <&bpmp TEGRA186_RESET_SOR1>; 826 reset-names = "sor"; 827 pinctrl-0 = <&state_dpaux1_aux>; 828 pinctrl-1 = <&state_dpaux1_i2c>; 829 pinctrl-2 = <&state_dpaux1_off>; 830 pinctrl-names = "aux", "i2c", "off"; 831 status = "disabled"; 832 833 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 834 nvidia,interface = <1>; 835 }; 836 837 dpaux: dpaux@155c0000 { 838 compatible = "nvidia,tegra186-dpaux"; 839 reg = <0x155c0000 0x10000>; 840 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 841 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 842 <&bpmp TEGRA186_CLK_PLLDP>; 843 clock-names = "dpaux", "parent"; 844 resets = <&bpmp TEGRA186_RESET_DPAUX>; 845 reset-names = "dpaux"; 846 status = "disabled"; 847 848 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 849 850 state_dpaux_aux: pinmux-aux { 851 groups = "dpaux-io"; 852 function = "aux"; 853 }; 854 855 state_dpaux_i2c: pinmux-i2c { 856 groups = "dpaux-io"; 857 function = "i2c"; 858 }; 859 860 state_dpaux_off: pinmux-off { 861 groups = "dpaux-io"; 862 function = "off"; 863 }; 864 865 i2c-bus { 866 #address-cells = <1>; 867 #size-cells = <0>; 868 }; 869 }; 870 871 padctl@15880000 { 872 compatible = "nvidia,tegra186-dsi-padctl"; 873 reg = <0x15880000 0x10000>; 874 resets = <&bpmp TEGRA186_RESET_DSI>; 875 reset-names = "dsi"; 876 status = "disabled"; 877 }; 878 879 dsic: dsi@15900000 { 880 compatible = "nvidia,tegra186-dsi"; 881 reg = <0x15900000 0x10000>; 882 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 883 clocks = <&bpmp TEGRA186_CLK_DSIC>, 884 <&bpmp TEGRA186_CLK_DSIC_LP>, 885 <&bpmp TEGRA186_CLK_PLLD>; 886 clock-names = "dsi", "lp", "parent"; 887 resets = <&bpmp TEGRA186_RESET_DSIC>; 888 reset-names = "dsi"; 889 status = "disabled"; 890 891 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 892 }; 893 894 dsid: dsi@15940000 { 895 compatible = "nvidia,tegra186-dsi"; 896 reg = <0x15940000 0x10000>; 897 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 898 clocks = <&bpmp TEGRA186_CLK_DSID>, 899 <&bpmp TEGRA186_CLK_DSID_LP>, 900 <&bpmp TEGRA186_CLK_PLLD>; 901 clock-names = "dsi", "lp", "parent"; 902 resets = <&bpmp TEGRA186_RESET_DSID>; 903 reset-names = "dsi"; 904 status = "disabled"; 905 906 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 907 }; 908 }; 909 910 gpu@17000000 { 911 compatible = "nvidia,gp10b"; 912 reg = <0x0 0x17000000 0x0 0x1000000>, 913 <0x0 0x18000000 0x0 0x1000000>; 914 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 915 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 916 interrupt-names = "stall", "nonstall"; 917 918 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 919 <&bpmp TEGRA186_CLK_GPU>; 920 clock-names = "gpu", "pwr"; 921 resets = <&bpmp TEGRA186_RESET_GPU>; 922 reset-names = "gpu"; 923 status = "disabled"; 924 925 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 926 }; 927 928 sysram@30000000 { 929 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 930 reg = <0x0 0x30000000 0x0 0x50000>; 931 #address-cells = <2>; 932 #size-cells = <2>; 933 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 934 935 cpu_bpmp_tx: shmem@4e000 { 936 compatible = "nvidia,tegra186-bpmp-shmem"; 937 reg = <0x0 0x4e000 0x0 0x1000>; 938 label = "cpu-bpmp-tx"; 939 pool; 940 }; 941 942 cpu_bpmp_rx: shmem@4f000 { 943 compatible = "nvidia,tegra186-bpmp-shmem"; 944 reg = <0x0 0x4f000 0x0 0x1000>; 945 label = "cpu-bpmp-rx"; 946 pool; 947 }; 948 }; 949 950 cpus { 951 #address-cells = <1>; 952 #size-cells = <0>; 953 954 cpu@0 { 955 compatible = "nvidia,tegra186-denver", "arm,armv8"; 956 device_type = "cpu"; 957 reg = <0x000>; 958 }; 959 960 cpu@1 { 961 compatible = "nvidia,tegra186-denver", "arm,armv8"; 962 device_type = "cpu"; 963 reg = <0x001>; 964 }; 965 966 cpu@2 { 967 compatible = "arm,cortex-a57", "arm,armv8"; 968 device_type = "cpu"; 969 reg = <0x100>; 970 }; 971 972 cpu@3 { 973 compatible = "arm,cortex-a57", "arm,armv8"; 974 device_type = "cpu"; 975 reg = <0x101>; 976 }; 977 978 cpu@4 { 979 compatible = "arm,cortex-a57", "arm,armv8"; 980 device_type = "cpu"; 981 reg = <0x102>; 982 }; 983 984 cpu@5 { 985 compatible = "arm,cortex-a57", "arm,armv8"; 986 device_type = "cpu"; 987 reg = <0x103>; 988 }; 989 }; 990 991 bpmp: bpmp { 992 compatible = "nvidia,tegra186-bpmp"; 993 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 994 TEGRA_HSP_DB_MASTER_BPMP>; 995 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 996 #clock-cells = <1>; 997 #reset-cells = <1>; 998 #power-domain-cells = <1>; 999 1000 bpmp_i2c: i2c { 1001 compatible = "nvidia,tegra186-bpmp-i2c"; 1002 nvidia,bpmp-bus-id = <5>; 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 status = "disabled"; 1006 }; 1007 1008 bpmp_thermal: thermal { 1009 compatible = "nvidia,tegra186-bpmp-thermal"; 1010 #thermal-sensor-cells = <1>; 1011 }; 1012 }; 1013 1014 thermal-zones { 1015 a57 { 1016 polling-delay = <0>; 1017 polling-delay-passive = <1000>; 1018 1019 thermal-sensors = 1020 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 1021 1022 trips { 1023 critical { 1024 temperature = <101000>; 1025 hysteresis = <0>; 1026 type = "critical"; 1027 }; 1028 }; 1029 1030 cooling-maps { 1031 }; 1032 }; 1033 1034 denver { 1035 polling-delay = <0>; 1036 polling-delay-passive = <1000>; 1037 1038 thermal-sensors = 1039 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 1040 1041 trips { 1042 critical { 1043 temperature = <101000>; 1044 hysteresis = <0>; 1045 type = "critical"; 1046 }; 1047 }; 1048 1049 cooling-maps { 1050 }; 1051 }; 1052 1053 gpu { 1054 polling-delay = <0>; 1055 polling-delay-passive = <1000>; 1056 1057 thermal-sensors = 1058 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 1059 1060 trips { 1061 critical { 1062 temperature = <101000>; 1063 hysteresis = <0>; 1064 type = "critical"; 1065 }; 1066 }; 1067 1068 cooling-maps { 1069 }; 1070 }; 1071 1072 pll { 1073 polling-delay = <0>; 1074 polling-delay-passive = <1000>; 1075 1076 thermal-sensors = 1077 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 1078 1079 trips { 1080 critical { 1081 temperature = <101000>; 1082 hysteresis = <0>; 1083 type = "critical"; 1084 }; 1085 }; 1086 1087 cooling-maps { 1088 }; 1089 }; 1090 1091 always_on { 1092 polling-delay = <0>; 1093 polling-delay-passive = <1000>; 1094 1095 thermal-sensors = 1096 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 1097 1098 trips { 1099 critical { 1100 temperature = <101000>; 1101 hysteresis = <0>; 1102 type = "critical"; 1103 }; 1104 }; 1105 1106 cooling-maps { 1107 }; 1108 }; 1109 }; 1110 1111 timer { 1112 compatible = "arm,armv8-timer"; 1113 interrupts = <GIC_PPI 13 1114 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1115 <GIC_PPI 14 1116 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1117 <GIC_PPI 11 1118 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1119 <GIC_PPI 10 1120 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1121 interrupt-parent = <&gic>; 1122 }; 1123}; 1124